Abstract: A display device can include a flexible substrate including an active area, a bending area, and an area outside the bending area, the bending area configured to be bent flexibly; a plurality of pixels to display an image in the active area, each of the plurality of pixels including an organic light emitting diode (OLED); at least one signal line and at least one power line disposed on the flexible first substrate, the at least one signal line and the at least one power ling being disposed on a same layer in the bending area; and a planarization layer disposed in the active area and covering the at least one signal line and the at least one power line disposed on the same layer in the bending area, wherein the OLEDs in the plurality of pixels are disposed on the planarization layer.

Abstract: A method of passivating a silicon substrate for use in a photovoltaic device, comprising providing a silicon substrate having a bulk and exhibiting a front surface and a rear surface, and forming by liquid phase application a dielectric layer on at least said rear surface. The dielectric layer formed at the rear surface is capable of acting as a reflector to enhance reflection of light into the bulk of the silicon substrate, and the dielectric layer is capable of releasing hydrogen into the bulk as well as onto a surface of the silicon substrate in order to provide hydrogenation and passivation. The present invention provides an inexpensive, low cost method of improving the electrical and/or optical performance of photovoltaic devices through the application of coating chemicals onto the backside of the silicon substrate.

Abstract: An electronic device including: a substrate; a first electrically-conductive layer; a second electrically-conductive layer; and an intermediate layer. The first electrically-conductive layer is disposed on the substrate and composed of aluminum or an aluminum alloy. The second electrically-conductive layer is spaced away from the first electrically-conductive layer. The intermediate layer is disposed between the first electrically-conductive layer and the second electrically-conductive layer, is in contact with both the first electrically-conductive layer and the second electrically-conductive layer, and contains aluminum and fluorine.

Abstract: A semiconductor structure is provided, which includes a semiconductor device, a first conductive layer, and a gate runner. The semiconductor device includes an upper surface, a gate terminal, a source terminal, and a drain terminal. The first conductive layer is deposited on the upper surface and coupled to the source terminal. The gate runner is overlapped with the first conductive layer and coupled to the gate terminal. The gate runner and the first conductive layer are configured to contribute a parasitic capacitance between the gate terminal and the source terminal.

Abstract: Provided is a display device including: a substrate including an active area, a non-active area, a bending area and a pad area; the active area including pixels to display images, each pixel including an organic light emitting layer and a thin-film transistor (TFT); the non-active area located between the active area and the bending area; and the bending area configured to be bent and located between the non-active area and the pad area, the bending area including a signal line and a power line that are made of a same material as a source electrode or a drain electrode of the TFT in the active area.

Abstract: A finned semiconductor structure including sets of relatively wide and relatively narrow fins is obtained by employing hard masks having different quality. A relatively porous hard mask is formed over a first region of a semiconductor substrate and a relatively dense hard mask is formed over a second region of the substrate. Patterning of the different hard masks using a sidewall image transfer process causes greater lateral etching of the relatively porous hard mask than the relatively dense hard mask. A subsequent reactive ion etch to form semiconductor fins causes relatively narrow fins to be formed beneath the relatively porous hard mask and relatively wide fins to be formed beneath the relatively dense hard mask.

Abstract: A method for making a micro LED display panel includes: providing a transferring plate and a growth substrate with at least one micro LED; transferring the micro LED from the growth substrate to the transfer plate; providing a TFT substrate including a driving circuit including TFTs; the TFT substrate provided with a conductive connecting element, an insulating layer covering the conductive connecting element, and a contact electrode on a side of the insulating layer; and powering the driving circuit to apply a reference voltage to the contact electrode, and a voltage different from the reference voltage is applied to the conductive connecting element, and making the contact electrode on the TFT substrate contact with the first electrode of the micro LED; the micro LED is detached from the transferring plate onto the TFT substrate; and bonding the conductive connecting element to the micro LED. The making method is simple.

Abstract: The present invention provides a metal-oxide-metal (MOM) capacitor including a first metal layer and a second metal layer. The first metal layer includes a plurality of first metal stripes and second metal stripes extending along a first direction and a plurality of first metal jogs and second metal jogs extending along a second direction. Each of the first metal jogs is connected to one of the first metal stripes and each of the second metal jogs is connected to one of the second metal stripes. The second metal layer includes a plurality of third metal stripes and fourth metal stripes extending along the first direction and includes a plurality of third metal jogs and fourth metal jogs. Each of the third metal jogs is connected to one of the third metal stripes and each of the fourth metal jogs is connected to one of the fourth metal stripes.

Abstract: The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

Abstract: A semiconductor structure includes a semiconductor substrate, n-type source and drain stressors, and a gate stack. The semiconductor substrate has source and drain recesses therein. The n-type source and drain stressors are respectively present in the source and drain recesses. At least one of the n-type source and drain stressors has a hydrogen terminated surface. A gate stack is present on the semiconductor substrate and between the n-type source and drain stressors.

Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, an upper second p+-type region, a lower second p+-type region and a first p+-type region are provided. The lower second p+-type region is provided orthogonal to a trench, and a total mathematical area regions that are between the first p+-type region and the p-type base layer and that include the n-type region is at least two times a total mathematical area of regions that are between the first p+-type region and the p-type base layer and that include the upper second p+-type region.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.

Abstract: A pixel array structure and a display device are provided. The pixel array structure includes pixel groups arranged repeatedly, wherein each pixel group at least includes a first pixel (21), a second pixel (22) and a third pixel (23), each type of pixels include sub-pixels of at least two colors, and sub-pixels included in different types of pixels are different in color or sequence, which can improve aperture ratios of part of color sub-pixels.

Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.

Abstract: A micro light-emitting diode display device including a driving transistor and a micro light-emitting diode is provided. The driving transistor includes a substrate, a bottom gate, a gate insulator, a semiconductor layer, an etch stopper, a drain electrode, a source electrode, and an insulating layer. The drain electrode is ring-shaped and a contact portion between the drain electrode and the semiconductor layer surrounds the semiconductor layer. The source electrode is in contact with the semiconductor layer and is enclosed by the drain electrode. The insulating layer has a via therein to expose a portion of the source electrode. The micro light-emitting diode is electrically connected to the source electrode. The micro light-emitting diode includes a current injection channel present in the micro-light emitting diode. The current injection channel is separated from a side surface of the micro light-emitting diode.

Abstract: A micro-light-emitting diode device includes a first semiconductor layer, an active layer, and a second semiconductor layer. The first semiconductor layer has a first bottom surface. The active layer is disposed on the first semiconductor layer. The second semiconductor layer is disposed on the active layer. The second semiconductor layer and the active layer have an interface. A surface of the second semiconductor layer opposite to the active layer is a light-exiting surface of the micro-light-emitting diode device. A distance between the light-exiting surface and the interface decreases from a central axis of the second semiconductor layer to an edge of the second semiconductor layer, so as to provide a focusing effect for the light by the light-exiting surface.

Abstract: A light-emitting device includes a light-emitting element disposed on a mount substrate, a reflective member disposed around the light-emitting element to cover the light-emitting element, and a dam disposed on opposite sides of the reflective member. The dam includes a resin dam, and a surface layer covering at least part of a surface of the resin dam. The inner lateral surface of the resin dam facing the light-emitting element is covered with the surface layer, and at least part of the outer lateral surface of the resin dam not facing the light-emitting element is an exposed surface.

Abstract: A light emitting element including at least a first trench portion having an indented shape within a single light emitting region. The first trench portion includes a first electrode, an EL layer, and a second electrode. The first electrode, the EL layer, and the second electrode are layered in this order and in contact with each other. At least one of the first electrode or the second electrode includes a reflective electrode.

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.