Abstract: A method includes forming a shallow trench isolation (STI) region in a semiconductor substrate, the STI region bordering an active region in the semiconductor substrate; forming a plurality of gate structures over the semiconductor substrate; and forming a plurality of conductive contacts between the gate structures and in contact with the STI region, wherein a portion of the active region is between the conductive contacts.

Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of silicon carbide, a device structure provided on top of the first semiconductor layer, a second semiconductor layer of silicon carbide having a higher impurity concentration than the first semiconductor layer, provided under the first semiconductor layer, the second semiconductor layer implementing an ohmic-contact, and a metallic electrode film provided under the second semiconductor layer. A thickness of a carbon-containing region in which carbon-atoms are precipitated between the second semiconductor layer and the metallic electrode film is 10 nm or less.

Abstract: A method for producing an optoelectronic semiconductor component and an optoelectronic semiconductor component are disclosed. In an embodiment a method include providing a semiconductor layer sequence having an active region and a plurality of emission regions, forming a plurality of first contact points, filling spacings between the first contact points with a molding compound, removing a growth substrate of the semiconductor layer sequence and arranging the semiconductor layer sequence on a connection carrier comprising a control circuit and a plurality of connection surfaces, wherein each of the first contact points is electrically conductively connected to a connection surface, wherein the emission regions are independently controllable by the control circuit, and wherein the molding compound serves as a temporary auxiliary carrier that mechanically stabilizes the semiconductor layer sequence during the removal of the growth substrate.

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In some embodiments, a first precursor forms a layer on the first surface and is subsequently reacted or converted to form a metallic layer. The deposition temperature may be selected such that a selectivity of above about 50% or even about 90% is achieved.

Abstract: Described herein is a technique capable of selectively forming a film in a film-forming step. According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device including: (a) selectively forming a film on a substrate by supplying a process gas into a process chamber accommodating the substrate, wherein an inhibitor layer is formed on a portion of the substrate such that the substrate acquires a selectivity in an adsorption of the process gas; (b) supplying a cleaning gas containing a component contained in the inhibitor layer into the process chamber accommodating no substrate; and (c) removing a residual component of the cleaning gas in the process chamber.

Abstract: A field effect transistor according to the present invention includes a semiconductor substrate, a plurality of drain electrodes provided on a first surface of the semiconductor substrate and extending in a first direction, an input terminal, an output terminal, and a plurality of metal layers provided in the semiconductor substrate apart from the first surface and extending in a second direction crossing the first direction, in which the plurality of metal layers include a first metal layer and a second metal layer which is longer than the first metal layer and which crosses more drain electrodes than the first metal layer when seen from a direction perpendicular to the first surface, and among the plurality of drain electrodes, those having a smaller length of line from the input terminal to the output terminal are provided with more metal layers directly thereunder.

Abstract: Methods and apparatuses to detect particles in dense particle fields are described. A time varying signal is partitioned into a plurality of segments. Parameters are determined from the segments. The time varying signal is parsed into a plurality of individual particle signal components based on the plurality of parameters.

Abstract: In some embodiments, a photodetector is provided. The photodetector includes a first well having a first doping type disposed in a semiconductor substrate. A second well having a second doping type opposite the first doping type is disposed in the semiconductor substrate on a side of the first well. A first doped buried region having the second doping type is disposed in the semiconductor substrate, where the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well. A second doped buried region having the second doping type is disposed in the semiconductor substrate and vertically between the first doped buried region and the first well, where the second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.

Abstract: The semiconductor device of the present invention includes a semiconductor layer which includes an active portion and a gate finger portion, an MIS transistor which is formed at the active portion and includes a gate trench as well as a source region, a channel region and a drain region sequentially along a side surface of the gate trench, a plurality of first gate finger trenches arranged by an extended portion of the gate trench at the gate finger portion, a gate electrode embedded each in the gate trench and the first gate finger trench, a second conductive-type first bottom-portion impurity region formed at least at a bottom portion of the first gate finger trench, a gate finger which crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and a second conductive-type electric field relaxation region which is formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches.

Abstract: An organic light-emitting display apparatus includes a thin-film transistor on a substrate, a planarization layer on the thin-film transistor, and a pixel-defining spacer on the planarization layer. The pixel-defining spacer defines a pixel area between two pixels that are adjacent in a first direction.

Abstract: A light emitting diode includes a first light emitting cell and a second light emitting cell comprising an n-type semiconductor layer, and a p-type semiconductor layer, respectively; reflection structures contacting the p-type semiconductor layers; a first contact layer in ohmic contact with the n-type semiconductor layer of the first light emitting cell; a second contact layer in ohmic contact with the n-type semiconductor layer of the second light emitting cell and connected to the reflection structure on the first light emitting cell. An n-electrode pad is connected to the first contact layer; and a p-electrode pad is connected to the reflection structure on the second light emitting cell. The first light emitting cell and the second light emitting cell are isolated from each other, and their outer side surfaces are inclined steeper than the inner sides. Therefore, a forward voltage may be lowered and light output may be improved.

Abstract: A device comprising a light emitting diode (LED) substrate, and a meta-molecule wavelength converting layer positioned within an emitted light path from the LED substrate, the a meta-molecule wavelength converting layer including a plurality of nanoparticles, the plurality of nanoparticles configured to increase a light path length in the wavelength converting layer.

Abstract: The present invention is equipped with: a substrate (10) that has a surface upon which a drive circuit containing a TFT (20) is formed; a planarization film (30) that makes the surface of the substrate planar by covering the drive circuit; and an organic light-emitting element (40) that is provided with a first electrode (41) formed upon the surface of the planarization film and connected to the drive circuit, an organic light-emitting layer (43) formed upon the first electrode, and a second electrode (44) formed upon the organic light-emitting layer. In addition, the planarization film has a two-layer structure comprising an inorganic insulating film (31) and an organic insulating film (32) that are layered upon the TFT, a conductor layer containing a titanium layer and a copper layer is embedded in the interior of a contact hole, and the first electrode is formed electrically connected to the conductor layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to n-well resistors and methods of manufacture. The structure includes: a substrate composed of a N-well implant region and a deep N-well implant region; and a plurality of shallow trench isolation regions extending into both the N-well implant region and a deep N-well implant region.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

Abstract: A display panel and a method of fabricating the same, and a display device are provided, the display panel includes a display substrate a package substrate opposite to each other, the display substrate includes a first base substrate; and a first electrode, an electroluminescent layer and a second electrode disposed on the first base substrate in sequence; the package substrate includes a second base substrate; and a conductive layer on the second base substrate, the conductive layer and the second electrode facing towards each other; the display panel further includes a conductive adhesive between the second electrode and the conductive layer, the conductive adhesive is configured to bond the display substrate with the package substrate, and electrically connect the second electrode with the conductive layer.

Abstract: The present disclosure relates to a flat panel display embedding an optical imaging sensor such as a fingerprint image sensor. The present disclosure provides a flat panel display embedding an optical image sensor comprising: a display panel including a display area and a sensing area defined in the display area; a barrier plate having a light transparent area corresponding to the sensing area and disposed at a rear surface of the display panel; and a light sensor disposed under the barrier plate corresponding to the light transparent area.

Abstract: To reduce the influence of generation of after-pulses when a pixel including a SPAD is used. In a SPAD pixel, a PN junction part of a P+ type semiconductor layer and an N+ type semiconductor layer is formed, a P type semiconductor layer having a concentration higher than the concentration of a silicon substrate is formed in a region deeper than the PN junction part and close to a light absorption layer. With no quenching operation generating no after-pulse, electrons generated in the light absorption layer are guided to the PN junction part and subjected to avalanche amplification. When the quenching operation is performed after avalanche amplification, the electrons are guided to the N+ type semiconductor layer by a potential barrier to prevent avalanche amplification. The present disclosure is applicable to an image sensor including a SPAD.

Abstract: Embodiments of methods for forming a staircase structure of a three-dimensional (3D) memory device are disclosed. In an example, a first plurality of stairs of the staircase structure are formed based on a first photoresist mask. Each of the first plurality of stairs includes a number of divisions at different depths. After forming the first plurality of stairs, a second plurality of stairs of the staircase structure are formed based on a second photoresist mask. Each of the second plurality of stairs includes the number of divisions. The staircase structure tilts downward and away from a memory array structure of the 3D memory device from the first plurality of stairs to the second plurality of stairs.