Abstract: One embodiment provides a programmable logic device in which a logic switch includes: a first memory having a first terminal connected to a first wire, a second terminal connected to a second wire, and a third terminal connected to a third wire; a second memory having a fourth terminal connected to the first wire, a fifth terminal connected to a fourth wire, and a sixth terminal connected to a fifth wire; and a pass transistor having a gate connected to the first terminal, and a source and a drain respectively connected to a sixth wire and a seventh wire. A source or drain of a first select gate transistor is connected the sixth wire, and a source or drain of a second select gate transistor is connected to the seventh wire.

Abstract: A control circuit adapted to control a power converting circuit for stabilizing an output of the power converting circuit is provided. The control circuit includes a capacitor, a charging unit, a discharging unit, a feedback control unit, and a duty-cycle adjusting unit. The charging unit has a first current source coupled to the capacitor for charging the capacitor. The discharging unit is coupled to the capacitor for discharging the capacitor. The feedback control unit controls the charging unit to charge the capacitor according to a feedback signal which represents the output of the power converting circuit. The duty-cycle adjusting unit generates a control signal and adjusts a duty cycle of the control signal according to a voltage of the capacitor.

Abstract: An integrated circuit may include memory interface circuitry that is used to communicate with off-chip memory. The memory interface circuitry may include data strobe (DQS) enable circuitry that receives DQS signals from the off-chip memory and that outputs a gated version of the DQS signals. The DQS enable circuitry may include an input buffer, a comparator, a latch, a flip-flop, a counter, and a gating circuit. The input buffer may receive an incoming DQS signal. The comparator may be used to determine when the incoming DQS signal starts to toggle. The latch may be used to control when a gating signal is asserted. The flip-flop controls the counter, which limits the duration that the gating signal is asserted. The gating circuit receives the DQS signal from the buffer and the gating signal and passes the DQS signal through to its output only when the gating signal is asserted.

Abstract: A method for controlling a lighting system in an aircraft cabin is provided. The lighting system has lighting units each including a controller for controlling RGB light-emitting diodes, and a central processor connected to each controller for data exchange. Each controller has a storage unit for storing scene programs each controlling a respective scene. Control data records are transmitted to the controllers from the central processor for controlling an overall luminous behavior generated by the lighting units. The control data records have scene program identification information and synchronization information for controlling the sequence of the scene program corresponding to the scene program identification information with time.

Abstract: An ion source is disclosed including: a chamber disposed about a longitudinal axis and containing a gas, a magnetic confinement system configured to produce a magnetic field in a confinement region within the chamber, an electron cyclotron resonance driver which produces a time varying electric field which drives the cyclotron motion of electrons located within the confinement region, the driven electrons interacting with the gas to form a confined plasma. During operation, the magnetic confinement system confines the plasma in the confinement region such that a portion of atoms in the plasma experience multiple ionizing interactions with the driven electrons to form multiply ionized ions having a selected final ionization state.

Abstract: Described embodiments include a level shifter that provides a voltage level shift to applied signals, the amount of voltage shift being accurately controlled and independent of PVT. The level shifter has first transistor configured as a voltage follower with the gate coupled to an input terminal of the shifter and the source coupled to a node, a diode-connected transistor coupled between the node and an output terminal of the circuit, a first controlled current source coupled to the node, and a second controlled current source coupled to the output terminal. A controller receives a bandgap-stabilized voltage, squares the stabilized voltage to produce a control signal that controls the first and second controlled current sources. The voltage shift is proportional to a digitally-controlled scale factor (K) times the stabilized voltage. The ratio of the current from the first current source to the second current source is (K+1)/K.

Abstract: A balanced single-end impedance control system is disclosed. In a particular embodiment, the circuit includes a first transistor coupled to a first output terminal and a second transistor coupled to a second output terminal. The circuit also includes a third transistor and a fourth transistor, where device characteristics of the third transistor substantially match device characteristics of the first transistor and device characteristics of the fourth transistor substantially match device characteristics of the second transistor. The circuit further includes a first control path and a second control path. The first path is coupled to the third transistor and provides a first rail voltage to control a first gate control voltage of the first transistor. The second control path is coupled to the fourth transistor and provides a second rail voltage to control a second gate control voltage of the second transistor.

Abstract: Semiconductor modules are provided. The semiconductor module includes a first semiconductor chip configured for storing an information signal that is set in response to a command/address signal and which determines reception of an on-die termination (ODT) signal in a power down mode in response to the information signal to control activation of a first ODT circuit; and a second semiconductor chip configured for sharing and utilizing the first ODT circuit included in the first semiconductor chip.

Abstract: The circuit includes an E-mode transistor with gate-source junction, a D-mode transistor with gate-source junction, a component generating a voltage drop between the source of the D-mode transistor and the drain of the E-mode transistor, and a connection between the drain of the E-mode transistor and the gate of the D-mode transistor. The gate of the E-mode transistor is provided for an input signal, and the drain of the E-mode transistor is provided for an output signal.

Abstract: An impedance control circuit includes a first impedance unit configured to terminate an impedance node using an impedance value that is determined by an impedance control code, a second impedance unit configured to terminate the impedance node using an impedance value that is determined by an impedance control voltage, a comparison circuit configured to compare a voltage level of the impedance node and a voltage level of a reference voltage, generate an up/down signal indicating whether the voltage at the impedance node is greater than the reference voltage, and generate the impedance control voltage that has a voltage level corresponding to a difference between the voltage at the impedance node and the reference voltage, and a counter unit configured to increase or decrease a value of the impedance control code in response to the up/down signal.

Abstract: A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.

Abstract: Circuits and techniques for operating an integrated circuit (IC) with a level shifter circuit are disclosed. A level shifter circuit with input and output terminals is operable to shift an input signal that ranges from a ground voltage to a first positive voltage to an output signal that ranges from the ground voltage to a second positive voltage. The level shifter circuit further includes a first kicker transistor having a first source-drain terminal operable to receive a buffered version of the input signal and having a second source-drain terminal coupled to the output terminal. The first kicker transistor may receive gate signals that turn on the first kicker transistor when the input signal is at the ground voltage and may pull the output terminal to the first positive voltage as the input signal transitions from the ground voltage to the first positive voltage.

Abstract: An integrated circuit device comprising one or more data processing circuits, each having an input stage, a combinatorial logic stage and an output stage. The input stage is responsive to a clock signal, and receives at least a first and second set of data signals and provides the first set to an input of the logic stage during a first portion of a clock signal period, and provides the second set to the input during a second portion of the period. The output stage is responsive to the clock signal, and receives from an output of the logic stage at least a first result signal as a function of the first set during a first portion of a subsequent clock signal period and receives from the output at least a second result signal as a function of the second set during a second portion of the subsequent period.

Abstract: A system and method for calibrating bias in a data transmission system including a calibrated bias having impedance calibration for accommodating parameter variations in the data transmission system. A current mirror receives and balances bias currents between the calibrated bias and an output driver from the data transmission system. A digital compensation logic circuit is connected to the calibrated bias to adjust the calibrated bias for variations in parameters causing a current tail effect. A calibration logic circuit adjusts calibration due to variations in operational parameters, such that the tail current variations are minimized.

Abstract: Fixed Frequency, Fixed Duration power controls methods and systems are described for application of power to electrical loads. FFFD techniques according to the present disclosure utilize power train pulses with fixed-frequency fixed-duration pulses to control power applied to a load. The load can be any type of DC load. FFFD techniques allows for controlled variation of the fixed length of the ON pulse, the Fixed length of the OFF or recovery period, the total time period for one cycle, and/or the number of pulses in that time period. Applications to electric motors, electric lighting, and electric heating are described. Related circuits are also described.

Abstract: A discharge device includes a dielectric, a first electrode and a second electrode arranged with the dielectric interposed therebetween, and a circuit unit to which the first electrode and the second electrode are electrically connected for generating a high voltage to be applied to the first electrode and to the second electrode. The dielectric is formed in a tube shape or a pipe shape having therein the circuit unit.

Abstract: A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.

Abstract: An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active.

Abstract: In described embodiments, a timestamp generator includes a fixed clock domain driven by a fixed frequency clock, a core clock domain, coupled to the fixed clock domain, which is driven by a core clock whose frequency is adjustable during an operation of the timestamp generator. A timestamp logic operating in the core clock domain generates a timestamping output of the timestamp generator. A rate generator operating in both the fixed clock domain and the core clock domain generates per clock cycle increments in the fixed clock domain and transfers carry units from the fixed clock domain into the core clock domain, and a timestamp increment generation of the timestamp logic is clocked by the fixed frequency clock provided by the rate generator. A method for enabling timestamp in an ASIC to be accurate with system clock changes is also described.

Abstract: A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal.