Abstract: A three-dimensional dual-band antenna including a first radiation portion, a second radiation portion, a connection portion, an impedance matching portion and a feeding portion is provided. The second radiation portion is located under the radiation portion and parallel with the first radiation portion. The connection portion is connected to the first side of the first radiation portion and extended downward vertically, for connecting the first radiation portion and the second radiation portion. The impedance matching portion is connected to a second side of the first radiation portion and extended downward vertically. The first side and the second side are opposite. The feeding portion is connected to the second side and extended downward vertically. The feeding portion receives a feeding signal. The first and the second radiation portion are operated at the first and the second bandwidth respectively, wherein the second bandwidth is in higher frequency than the first bandwidth.

Abstract: An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor.

Abstract: A planar light-emitting module lighting circuit uses a lamp comprising an organic electroluminescence layer and electrodes sandwiching the organic electroluminescence layer as a load, and applies a current to the load so as to cause the organic electroluminescence layer to emit light. In the planer light-emitting module lighting circuit, a current at a lighting start time of the lamp is made small as compared with a current at a stationary lighting time at which a predetermined time period has passed since a lighting start.

Abstract: A constant voltage dimmable LED (Light Emitting Diode) driver is disclosed that is compatible with all types of dimmers, including conventional phase cut (TRIAC) dimmers, and behaves like a conventional constant voltage driver which can be connected to any size of LED load that has a matching voltage rating. The driver produces a continuous train of pulses for driving the LED load and obtains an averaged measure of the voltage at the AC input for controlling the duty cycle of the continuous train of pulses. Therefore, when the averaged measure of the voltage at the AC input is reduced by a dimmer, the duty cycle reduces, resulting in a dimmed LED. The driver can be created by adding a few components to a conventional wide input range AC-DC converter without or with very little modifications.

Abstract: A light source device which is used as the backlight device and does not generate sound is provided. One or more flat substrates each having a light emitting element on its surface side are supported by a chassis having a conductive flat plate surface so that back surfaces of the substrates are opposed to the flat plate surface. The substrate comprises first wiring conductive thin films on a surface side of an insulation substrate, and one or more second radiating or wiring conductive thin films on a back surface side of the insulation substrate. Two terminals of the light emitting element are connected to the two adjacent first conductive thin films. A potential of at least one of the second conductive thin films is fixed to have a constant potential difference or preferably fixed to the same potential with respect to that of the flat plate surface of the chassis.

Abstract: A driving circuit includes a first delay circuit, a rise-detection circuit, a fall-detection circuit, a first filter, a second filter, and an adder. The first delay circuit delays an input signal. The rise-detection circuit detects a rise of the input signal. The fall-detection circuit detects a fall of the input signal. The first filter gives a first gain-frequency response to an output signal of the rise-detection circuit. The second filter gives a second gain-frequency response to an output signal of the fall-detection circuit. The adder adds an output signal of the first filter and an output signal of the second filter to an output signal of the first delay circuit.

Abstract: A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

Abstract: Disclosed are methods and circuits that support different on-die termination (ODT) schemes for a plurality of signaling schemes using a relatively small number of external calibration pads. These methods and circuits develop control signals for calibrating any of multiple termination schemes that might be used by associated communication circuits. The ODT control circuits, entirely or predominantly instantiated on-die, share circuit resources employed in support of the different termination schemes to save die area.

Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.

Abstract: A mobile wireless communications device may include a portable housing, a circuit board carried by the portable housing and having a ground plane thereon, wireless communications circuitry carried by the circuit board, and an antenna assembly carried by the housing. More particularly, the antenna assembly may include a flexible substrate, an electrically conductive antenna element on the flexible substrate and connected to the wireless communications circuitry and the ground plane, and a floating, electrically conductive director element on the flexible substrate for directing a beam pattern of the antenna element.

Abstract: The Anlinx™:LVLP Hybrid Analogic Field Programmable Array of Milinx™:Mixed Signal FPSC™ Field Programmable System Chip™ is constituted of Field Programmable Hybrid Array (FPHA and Frequency Programmable Xtaless Clock (FPXC) being for high-speed and high frequency System-Design-On-Chip(SDOC) embedded in a single chip of Field Programmable System Chip(FPSC™). The FPXC adopts the Self-Adaptive Process & Temperature Compensation Bandgap Reference Generator, the Gain-Boost Amplitude Control LC VCO and inverter type flash memory. The FPHA adopts the two-way flash switch and inverter type flash memory Look-Up-Table(LUT). The FPXC adopts the inverter type flash memory as the Non-Volatile Memory(NVM) to keep the setup data in the field frequency programming. The flash technology of FPHA and FPXC are compatible that the FPHA has the FPXC capability. The PLLess CDR(PLL free Clock Data Recovery) is based on the FPXC capability for the SerDes high frequency application.

Abstract: A circuit apparatus includes an output circuit that outputs a signal to a host apparatus via a bus, and an output control circuit that controls the output circuit. The output circuit has a first conductive transistor provided between an output node and a first power source node, and a second conductive transistor provided between the output node and a second power source node. In a first output mode, the output control circuit controls one of the first conductive transistor and the second conductive transistor to go to off and controls the other transistor to go to on/off, whereas in a second output mode, the output control circuit controls the first conductive transistor to go to on and the second conductive transistor to go to off or vice versa.

Abstract: Ladder network circuits for controlling operation of a string of light emitting diodes (LEDS). The circuits include a number of sections connected in series. Each section includes one or more LED junctions, a variable resistive element coupled to the LED section, and a switch coupled to the variable resistive element and the LED section for controlling activation of the LED. The sections can include a transistor coupled between the switch and variable resistive element. The series of sections are connected to an AC power source, rectifier, and dimmer circuit. When receiving power from the power source, the sections activate the LEDs in sequence throughout the series of the sections. The dimmer circuit controls activation of a selection of one or more of the sections in order to activate in sequence the LEDs in only the selected sections, providing for both dimming and color control of the LEDs.

Abstract: A method and system are set forth for automatically adjusting keypad luminance based on display content. In one embodiment, the method comprises calculating a lighting level based on ambient light; calculating a luminance level of an image on the display; setting a maximum lighting level to the luminance level of the image on the display; and in the event the calculated lighting level exceeds the maximum lighting level then selecting the maximum lighting level, and in the event the calculated lighting level does not exceed the maximum lighting level then selecting the calculated lighting level.

Abstract: An integrated circuit includes a first ODT unit and an input buffer. The first ODT unit is configured to receive at least one pull-up code and at least one pull-down code for impedance matching of a first line through which data is transferred, and adjust a resistance value. The input buffer is configured to drive input data by buffering the data in response to a level of a reference voltage, wherein the driving of the input data is adjusted in response to the pull-up code and the pull-down code.

Abstract: A logic device includes a transmission gate block configured to receive a binary input and a control input, the transmission gate block configured to provide a multi-bit output that is correlated from the binary input and in response to the control input having a first value. A state driver block is activated to drive one of a low state bit pattern or a high state bit pattern to the multi-bit output in response to the control input having a second value, which is different from the first value.

Abstract: An LED device is provided. The LED device implements an efficient dimming operation. The LED device includes a triac dimmer for receiving an AC voltage and adjusting an angle of the AC voltage, a ballast for receiving the AC voltage from the triac dimmer and generating an AC voltage pulse, a bridge diode unit for generating a DC voltage pulse using the AC voltage pulse, an LED for receiving a DC current and emitting a light, an LED drive controller for receiving a dimming signal and controlling the DC current passing through the LED, and a dimming signal generator for receiving the AC voltage pulse from the ballast and generating a pulsating dimming signal for compensating an output of the triac dimmer and providing the dimming signal to the LED drive controller.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: An interface circuit for controlling a cross-domain signal link between a first circuit domain and a second circuit domain in a circuit may include first and second controllers, each of the first and second controllers including a first input coupled to a first voltage source of the first circuit domain and a second input coupled to a second voltage source of the second circuit domain.

Abstract: A multi-mode differential termination circuit has a pair of differential input terminals for receiving external differential signals, a pair of series-connected load elements coupled between said differential input terminals, and an analog interface terminal coupled a common junction point of said load elements. A bias circuit is coupled to the common junction point of the load elements for selectively applying a bias voltage thereto in response to a digital control signal. A control input receives the digital control signal to activate the bias circuit.