Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.

Abstract: A system provides for a serial transmitter with multiplexing and driving functionality that is combined into a single stage to increase the overall speed of the serial transmitter. The single stage includes a dynamic impedance that is configured in parallel with a multiplexing driver to reduce the input capacitance and set the correct output impedance. The single stage can be implemented as a stacked or cross-coupled XOR logic circuit or a stacked or cross-coupled multiplexer (“mux”) as the multiplexing driver. In an embodiment where a mux is used as the multiplexing driver, a clock can be injected into the mux driver to overcome inter-symbol interference.

Abstract: A dimmer adaptable to either two (H, DH) or three (H, N, DH) active wires includes a first full-wave rectifier (D1, D2, D3, D4) across an AC power hot (H) terminal and a dimmer hot (DH) terminal and a second full-wave rectifier (D1, D4, D5, D6) across the AC power hot (H) terminal and an AC power neutral (N) terminal. The dimmer operates in a two-wire configuration by drawing power through a load when a control circuit is not conducting or in a three-wire configuration, when the AC power neutral (N) terminal is connected, by drawing power from AC power hot (H) and AC power neutral (N) terminals. The dimmer operates according to a first set of preset dim levels when current is flowing through the first rectifier and according to a second set of preset dim levels when current is flowing through the second rectifier.

Abstract: A CMOS logic integrated circuit includes a level shifter and a CMOS logic circuit. The level shifter converts a signal of a first logic level to a signal of a second logic level. The signal of the first logic level changes between a first low potential and a first high potential higher than the first low potential. The signal of the second logic level changes between the first low potential and a second high potential higher than the first high potential. The CMOS logic circuit includes a first N-channel type MOSFET and a second N-channel type MOSFET. The second N-channel type MOSFET is connected in series with the first N-channel type MOSFET. A first signal of the first logic level is input into a gate of the first N-channel type MOSFET. A second signal of the second logic level has an inversion relationship with the first signal.

Abstract: A self-modulated voltage reference circuit may generate a reference voltage by receiving an internal reference voltage of a programmable device at a first input of a comparator block of the programmable device, receiving a feedback voltage at a second input of the comparator block, generating a pulse density modulated (PDM) signal based on a difference between the reference voltage and the feedback voltage, outputting the PDM signal at a digital output pin of the programmable device, and filtering the PDM signal to generate the output reference voltage.

Abstract: A constant current power supply device according to the present invention includes: an error amplifier to amplify an error signal of an error voltage between a voltage of a current detection resistor and a reference voltage, and a second control circuit to sample and hold the error signal in an ON period of the external signal, output the error signal to a first control circuit, hold the error signal just before the external signal is turned from ON to OFF, increase an amplification ratio of the error amplifier by a predetermined magnification ratio in an OFF period of the external signal, and output the increased error signal to the first control circuit.

Abstract: A domino logic circuit includes a first evaluation unit, a second evaluation unit and an output unit. The first evaluation unit precharges a first dynamic node, discharges a footer node in a first phase of a clock signal, and evaluates a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal. The second evaluation unit precharges a second dynamic node in the first phase of the clock signal, and determines a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal. The output unit provides an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node.

Abstract: A power converter having a feedback circuit for constant loads includes an input, a switch, an input voltage sense circuit, a feedback circuit, and a controller. The input is to be coupled to receive an input voltage and the switch is coupled to the input. The input voltage sense circuit is coupled to the input to generate an input voltage sense signal representative of the input voltage. The feedback circuit is coupled to an output of the power converter, where the output is electrically coupled to the input. The feedback circuit generates a feedback signal representative of an output voltage of the power converter. The controller is coupled to the feedback circuit and to the input voltage sense circuit to control switching of the switch to regulate an output current at the output of the power converter in response to the feedback signal and the input voltage sense signal.

Abstract: One embodiment relates to a programmable output buffer which includes first and second programmable variable-impedance single-ended driver circuits and first and second termination circuits. The first termination circuit is coupled to a first output pin which is driven by the first programmable variable-impedance single-ended driver circuit, and the second termination circuit is coupled to a second output pin which is driven by the second programmable variable-impedance single-ended driver circuit. The first and second termination circuits are programmable to either provide parallel termination for a differential signal or drive single-ended signals with the parallel termination turned off. Other embodiments and features are also disclosed.

Abstract: A light guide plate includes a first surface, a second surface, at least a light incident surface, and a plurality of groove sets. The second surface is opposite to the first surface. The light incident surface connects the first surface and the second surface. The groove sets are separately disposed on the second surface. Each of the groove sets includes a plurality of curved grooves. Each of the curved grooves has a curved inclined reflective surface and a curved light-back-surface. The curved inclined reflective surface is inclined with respect to the first surface. The curved grooves of each of the groove sets curve towards a same curving direction. The curved inclined reflective surface of one of two curved grooves is connected to the curved light-back-surface of the other one of the two curved grooves. A backlight module is also provided.

Abstract: A white light emitting apparatus includes a light source section in which a first white LED that emits white light whose chromaticity deviates to a blue side from a predetermined white region of a CIE chromaticity diagram and a second white LED that emits white light whose chromaticity deviates to a yellow side from the predetermined white region are adjacently disposed so as to emit light with optical axes in substantially the same direction, and a current regulator that independently drives the blue LED chip in the first and second white LEDs, respectively. A color mixture of lights emitted from the first and second white LEDs is adjusted to a chromaticity of the predetermined white region using the current regulator.

Abstract: A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W2 larger than a cell width of cell A-1, but gate length L1 of a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width W2 equal to a cell width of cell B-1, but has a MOS transistor having large gate length L2. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.

Abstract: A circuit implementing multiplexer, storage, and repeater functions is disclosed. The circuit includes first and second input stages having first and second data inputs, respectively. An output stage is configured to drive an output signal. The first input stage is configured to activate the output stage responsive to a first condition, while the second input stage is configured to activate the output stage responsive to a second condition. An intermediate stage is configured to deactivate the output stage at a first delay time subsequent to one of the first or second input stages activating the output stage. The repeater circuit also includes a storage element configured to store a state of the output signal, and further configured to cause the output node to be held at the state of the output signal subsequent to deactivation of the output stage.

Abstract: This disclosure provides a circuit and a method for driving an LED display. The driving circuit comprises a selection circuit for selecting a first light emitter from the plurality of light emitters, a pre-charging circuit for charging an equivalent capacitor of the display panel with respect to the selected first light emitter, and a power circuit for supplying power to the first light emitter after the first light emitter is selected, wherein the power circuit is configured to supply a driving current to the first light emitter in one or more stages. The driving circuit and method of this disclosure can be used to significantly increase the refresh rate and resolution of the LED display.

Abstract: Approaches for operating a programmable integrated circuit (IC) are disclosed. One configuration bitstream of two or more configuration bitstreams is selected. Each configuration bitstream implements a functionally equivalent circuit on the programmable IC and programs a respective subset of pass gates of the programmable IC. Each subset of pass gates programmed by the configuration bitstreams is disjoint from each other subset of pass gates. The programmable IC, which is defect-free, is configured with the selected configuration bitstream. The defect-free programmable IC is then operated for a period of time. The selecting, configuring and operating are repeated, and for successive selecting operations, different ones of the configuration bitstreams are selected.

Abstract: In one implementation, a memory device includes non-volatile memory and a memory controller communicatively coupled to the non-volatile memory over a first bus. The memory device can also include a host device interface through which the memory controller communicates with a host device over a second bus, wherein the host device interface includes an impedance calibration circuit that is adapted to calibrate a signal transmitted over the second bus by host device interface so that a source impedance associated with the signal matches, within a threshold value, a load impedance associated with the host device over the second bus.

Abstract: A cell-based architecture for an integrated circuit. A row of cell instances borders a first adjacent row of cell instances along a first boundary and a second adjacent row of cell instances along a second boundary. A first power rail (e.g., carrying an auxiliary voltage) extends along the first boundary. A second power rail (e.g., VSS) extends along the second boundary. The second power rail is wider than the first power rail. Additionally, a third power rail (e.g., VDD) extends across the interior of the second row of cells.

Abstract: In a power supply unit, if a dimmer rate is changed within a range of k1, k2, . . . k7 by a dimmer signal k of a dimmer signal generator, light-emitting diodes are controlled to be lighted by a constant current characteristic in an area where the dimmer rate is small according to a load characteristic corresponding to the dimmer rates k1, k2, . . . k7. As the dimmer rate becomes larger, a tendency of a constant voltage characteristic is gradually strengthened from a constant current characteristic so that the light-emitting diodes are lighted at the larger dimmer rate.

Abstract: A single-ended signaling system in which transmitted and returned signal currents are enabled to flow substantially parallel to one another and thereby maintain a substantially uniform impedance along the length of a single-ended signal conductor. A reference plane is disposed substantially parallel to a single-ended signaling conductor and coupled to the signaling conductor within a signal-receiving IC and to signaling supply voltage nodes within a signal-transmitting IC. By this arrangement, an signal current flowing to or from the receiving IC via the signaling conductor is conducted to the reference plane, thereby enabling a signal-return current to flow back to or back from the transmitting IC along a single path that is substantially parallel to the signal conductor.

Abstract: According to an embodiment, a method of preventing the alteration of a stored data value is disclosed. The method comprises coupling a first electronic fuse to an output control circuit; coupling a second electronic fuse to the output control circuit; decoding the states of the first electronic fuse and the second electronic fuse after a first processing step to generate a first decoded state; and decoding the states of the first electronic fuse and the second electronic fuse after a second processing step to generate a second decoded state different from the first decoded state; wherein the output control circuit maintains the second decoded state after an attempt to alter a state of an electronic fuse of the first electronic fuse and the second electronic fuse. A circuit for preventing the alteration of a stored data value is also described.