Abstract: A driving apparatus includes a voltage transforming unit and a detector. The driving apparatus is used for supplying a drive voltage to a load. The voltage transforming unit is used for transforming a direct current (DC) voltage to the drive voltage. The detector is connected to the load for detecting a forward voltage across the load to generate a detecting voltage; wherein the detector compares the detecting voltage with a first reference voltage. If the detecting voltage is smaller than the first reference voltage, the detector generates a first feedback signal; the voltage transforming unit increases the drive voltage according to the first feedback signal, the detecting voltage is defined by subtraction of the forward voltage from the drive voltage.

Abstract: In a power supply unit, if a dimmer rate is changed within a range of k1, k2, . . . k7 by a dimmer signal k of a dimmer signal generator, light-emitting diodes are controlled to be lighted by a constant current characteristic in an area where the dimmer rate is small according to a load characteristic corresponding to the dimmer rates k1, k2, . . . k7. As the dimmer rate becomes larger, a tendency of a constant voltage characteristic is gradually strengthened from a constant current characteristic so that the light-emitting diodes are lighted at the larger dimmer rate.

Abstract: Systems and methods for partial reconfiguration of reconfigurable application specific integrated circuit (ASIC) devices that may employ an interconnection template to allow partial reconfiguration (PR) blocks of an ASIC device to be selectively and dynamically interconnected and/or disconnected in standardized fashion from communication with a packet router within the same ASIC device.

Abstract: In one embodiment, a programmable logic device such as an FPGA includes a programmable fabric adapted to operate normally and in a sleep mode, and a general purpose input/output port (I/O). The I/O port is adapted to function in conventional fashion during normal operation of the programmable fabric and as a wakeup control port during the sleep mode.

Abstract: The invention relates to an electronic candle and an electronic night lamp. The electronic candle includes a light-emitting diode (LED), a capacitor and a control circuit. The capacitor has a first terminal coupled to a first terminal of the LED, and a second terminal coupled to a common voltage. The control circuit has a first control terminal coupled to the first terminal of the LED, and a second control terminal coupled to a second terminal of the LED. In a detecting period, the control circuit provides a preset voltage across the first and second terminals of the LED so that the LED is reversely biased for a preset time. Then, the first control terminal of the control circuit is set to high impedance. Next, the control circuit detects a variation of a voltage of the first terminal of the capacitor with respect to time to determine whether to light up the LED.

Abstract: A semiconductor device according to a first aspect of the present invention includes: a first circuit that outputs a first output value having a majority of output values received from N (N is three or more odd numbers) pieces of data hold circuits receiving a same input value; and a second circuit that outputs a second output value which is less than the majority of output values received from the N pieces of the data hold circuits.

Abstract: A communication network for a fleet of vehicles is disclosed. The communication network has a first group of the fleet of vehicles having a first level of priority on the network and a second group of the fleet of vehicles having a second level of priority on the network. A first vehicle in the first group is assigned as a supervisor of a second vehicle in the second group.

Abstract: An improved configuration for a programmable logic device and an improved method for configuration of a programmable logic device are provided. A programmable logic device such as field programmable logic device is configured to include an application logic, an embedded test logic that monitors the application logic, and an access control logic that grants access to an external device to embedded test data provided that an access control requirement is met that is based upon a key stored in a memory and information received from the external device.

Abstract: Ballasts are presented with improved end-of-life (EOL) detection of lamp DC voltage components and protection circuits to facilitate user maintenance and extend lamp life using selective dimming with preheating when EOL conditions are detected.

Abstract: A differential signal generating device includes a control circuit and a differential signal driver receiving a single-ended signal. The control circuit receives a source signal and generates a control signal corresponding to a first mode when the source signal conforms with a first pre-defined state, and corresponding to a second mode when the source signal conforms with a second pre-defined state. Variations of the source signal are related to signal content of the single-ended signal. The differential signal driver is coupled to the control unit for receiving the control signal therefrom. The differential signal driver outputs a differential signal output according to the single-ended signal when the control signal corresponds to the first mode. The differential signal driver outputs a non-differential signal output when the control signal corresponds to the second mode.

Abstract: An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.

Abstract: This disclosure is directed to a magnetic logic gate for implementing a combinational logic function. The magnetic logic gate may include a write circuit configured to apply a spin-polarized current to the magnetoresistive device such that a resulting programmed magnetization state of the magnetoresistive device corresponds to a logic input value of a combinational logic function implemented by the magnetic logic device. The magnetic logic gate may further include a read circuit configured to generate a logic output value for the combinational logic function based on the programmed magnetization state in response to the write circuit applying the spin-polarized current to the magnetoresistive device.

Abstract: An LED current control circuit including a current adjusting unit, a detecting unit, and a current control unit is provided. The current adjusting unit has a current control end coupled to an LED string for determining an amount of current flowing through the LED string according to a current control signal. The detecting unit detects the current control end and determines whether to generate a protecting signal according to a protecting voltage value. The current control unit generates the current control signal to control the amount of current flowing through the LED string of and determines whether to stop the current flowing through the LED string according to the protecting signal.

Abstract: A power gating circuit responds to a power enable signal to apply and withhold power to a MMIC. The gating circuit includes an OR gate and an AND gate, each coupled to the gate of a FET for controlling its conduction. One of the two FETs sources current to a load, and the other discharges the load. The gates are coupled so that the sourcing and discharge FETS are never turned ON simultaneously.

Abstract: A logic gate has a magnetoresistive element, a magnetization state control unit and an output unit. The magnetoresistive element has a laminated structure having N (N is an integer not smaller than 3) magnetic layers and N?1 nonmagnetic layers that are alternately laminated. A resistance value of the magnetoresistive element varies depending on magnetization states of the N magnetic layers. The magnetization state control unit sets the respective magnetization states of the N magnetic layers depending on N input data. The output unit outputs output data that varies depending on the resistance value of the magnetoresistive element.

Abstract: The present invention of a reverse polarity series type LED is formed by two sets of LED and diode assemblies in reverse polarity series connection wherein the first set is consisted of at least one or multiple homopolar series or parallel connected or series and parallel connected LED's, and the second set consisting of at least one or more homopolar parallel or series connected or series and parallel connected LED's for further connection to the drive circuit formed by current-limiting impedance and/or power storage and discharging devices and/or voltage-limit circuit devices in order to produce the required operational characteristics.

Abstract: A system and method for speed measurement of a mobile device, using an speed sensor such as a satellite navigation system or an accelerometer, does not need such speed sensor to be continually activated. The system and method make use of a monitor for monitoring at least one motion indicium for indicating that the speed of the mobile device is above an initial threshold, including but not limited to: monitoring the Doppler shift measurements of a timing signal; monitoring the timing advance of a cellular radio signal; monitoring the number of base stations visible to the mobile device; monitoring the frequency of base station handover, however determined; monitoring the level crossings and/or the autocorrelation of an RSSI signal; and/or triangulation of the position of the mobile device. When the monitor determines that the mobile device may be travelling in excess of a threshold speed, a speed sensor is activated to confirm the indication.

Abstract: An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

Abstract: A technique is provided that involves: configuring a clock generation circuit to output a first signal having a first frequency that is one of a plurality of frequencies that are different; generating in a clock section of a further circuit as a function of the first signal a second signal having a second frequency that is one of the plurality of frequencies other than the first frequency; and configuring the clock section to supply to the further circuit a clock signal that is one of the first and second signals.

Abstract: Integrated circuits and methods of permanently disabling integrated circuits are disclosed. An integrated circuit having an erasable non-volatile memory adapted to store an activation code and logic to disable the integrated circuit when the code in the erasable non-volatile memory has been altered or erased after it has been separated from a substrate, is placed into an electromagnetic field of sufficient power to erase or reprogram the erasable non-volatile memory. The entire integrated circuit is permanently disabled by erasing, altering, or reprogramming the erasable non-volatile memory. In preferred embodiments, the integrated circuit comprises a non-erasable non-volatile memory storing the activation code, and circuitry adapted to permanently disable the integrated circuit when the code in the erasable non-volatile memory does not match the activation code in the non-erasable non-volatile memory.