Patents Examined by Shawn X. Gu
  • Patent number: 11245774
    Abstract: Described herein are systems and techniques to efficiently cache data for streaming applications. A cache can be organized to include multiple cache segments, and each cache segment can include multiple cache blocks. A cache entry can be created for streaming data, and the streaming data can be streamed directly into a first cache block. When the first cache block is full, a next cache block can be identified, in a same cache segment or in a new cache segment. The streaming data can be streamed directly into the next cache block, and into any further cache blocks as needed.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: February 8, 2022
    Assignee: EMC IP Holding Company LLC
    Inventor: Andrei Paduroiu
  • Patent number: 11237958
    Abstract: A garbage collection process, wherein a system, concurrently with execution of a mutator application that modifies a heap memory computes, for each of a plurality of regions in the heap memory, an estimate indicative of a time required to evacuate the respective region. Thereafter, during a garbage collection pause having a particular pause duration, the system selects a candidate subset of memory regions for evacuation. The system merges the estimates indicative of the time required to evacuate each region of the candidate subset and determines a remaining time during the pause. The system may determine that the total estimated evacuation time to evacuate the candidate subset of regions does not exceed the determined first remaining time, and may evacuate each region in the candidate subset of memory regions for evacuation.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: February 1, 2022
    Assignee: Oracle International Corporation
    Inventors: Thomas Schatzl, Erik Duveblad
  • Patent number: 11237979
    Abstract: A method of operating a multi-core solid state drive includes: receiving an initial internal back copy command including a physical copy referencing a source Logical Page Number (LPN) and a destination LPN from a host, delaying processing of the physical copy when the physical copy requires two different flash translation layers (FTLs), and generating a modified batch internal copy command by replacing the source LPN of the physical copy with a Physical Page Number mapped to the source LPN.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: February 1, 2022
    Assignees: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Dongkun Shin, Gyuwha Han
  • Patent number: 11237742
    Abstract: A memory system includes a memory device including a plurality of memory blocks and a controller. At least one memory block among the plurality of memory blocks is allocated for one of data attributes. The controller can determine a first data attribute of first data stored in the memory device, based on a first map information item of the first data, and migrate the first data having the first data attribute to a memory block allocated for the first data attribute among the plurality of memory blocks.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Kyung-Soo Lee
  • Patent number: 11232032
    Abstract: Example storage systems, storage devices, and methods provide a write group journal for identifying incomplete writes. Related write request indicators are stored in a non-volatile journal in a solid state drive to identify a related write group and indicate whether the related write group has been stored in storage locations corresponding to physical page addresses. As the write requests for the related write group are processed, the related write request indicator is updated to allow incomplete write groups to be identified in the event of a failure.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: January 25, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kapil Sundrani, Karimulla Sheik
  • Patent number: 11231874
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks, in each of which a plurality of memory cells is arranged between bit lines and a source line, and a memory controller configured to control an operation of the nonvolatile memory. The memory controller is configured to issue a warming command to the nonvolatile memory when a temperature of the nonvolatile memory is lower than a first temperature, and the nonvolatile memory, in response to the warming command, causes current to flow through at least one bit line connected to memory cells of a first block.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: January 25, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Suguru Nishikawa, Masanobu Shirakawa, Yoshihisa Kojima, Takehiko Amaki
  • Patent number: 11226898
    Abstract: Disclosed in the present disclosure is a data caching method and apparatus, the data caching method includes the following steps: receiving a data request message sent by a user terminal; if detecting that a cache apparatus does not include the target access data requested by the data request message, then sending the target access data in a storage apparatus to the user terminal; extracting parameter information of the target access data in the storage apparatus, and determining whether the parameter information matches a preset parameter condition; and, if the parameter information matches the preset parameter condition, then transmitting the target access data to the cache apparatus.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: January 18, 2022
    Assignee: ZTE CORPORATION
    Inventors: Guangyan Zhang, Hongzhang Yang, Guiyong Wu, Shengmei Luo
  • Patent number: 11221963
    Abstract: A computer system includes a translation lookaside buffer (TLB) data cache and a processor. The TLB data cache includes a hierarchical configuration comprising a first TLB array, a second TLB array, a third TLB array, and a fourth TLB array. The processor is configured to receive a first address for translation to a second address, and determine whether translation should be performed using a hierarchical page table or a hashed page table. The processor also determines (using a first portion of the first address) whether the first array stores a mapping of the first portion of the first address in response to determining that the translation should be performed using the hashed page table, and retrieving the second address from the third TLB array or the fourth TLB array in response to determining that the first TLB array stores the mapping of the first portion of the first address.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: January 11, 2022
    Assignee: International Business Machines Corporation
    Inventors: David Campbell, Dwain A. Hicks
  • Patent number: 11221773
    Abstract: A method and apparatus for performing mapping information management regarding a RAID are provided. The method includes: writing data into a data region of the RAID in a redirect-on-write (ROW) manner, and recording mapping information between logical addresses of the data and protected-access-unit addresses (p-addresses) of protected access units in the data region into a logical-address-to-p-address (L2p) table within a table region of the RAID; when partial data of the data is updated, maintaining an updating list including a set of L2p table entries for the partial data in a RAM, and maintaining a recovery log corresponding to the updating list in a log region of the RAID, for power failure recovery; and according to the updating list, detecting whether a number of same-location L2p table entries in the set of L2p table entries reaches a predetermined threshold, to selectively update the L2p table with the same-location L2p table entries.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: January 11, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: An-Nan Chang
  • Patent number: 11216384
    Abstract: Various embodiments generally relate to a semiconductor device, and more particularly, to a controller, a memory system and an operating method thereof. In accordance with an embodiment of the present disclosure, an operating method of a controller for controlling a nonvolatile memory device may include receiving a read command from a host; determining whether changed L2P map data corresponding to L2P map data included in the read command is registered in a dirty list; and performing, when the changed L2P map data is determined as registered in the dirty list, a read operation on the nonvolatile memory device based on the changed L2P map data among L2P map data included in a plurality of L2P segments.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 11210183
    Abstract: Example systems and methods provide differentiated data recovery configurations based on memory health data. A distributed storage system, such as a cloud-based storage system, stores backup data from a remote storage device using a first data recovery configuration. Based on memory health data collected from the remote storage device, a change in a memory health state of the remote storage device may be determined. Responsive to the change in the memory health state, a different data recovery configuration may be used for storing backup data going forward and reallocating previously stored backup data in the distributed storage system.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: December 28, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Alex Bazarsky, Eran Sharon, Idan Alrod
  • Patent number: 11210220
    Abstract: A data manager may include a data opaque interface configured to provide, to an arbitrarily selected page-oriented access method, interface access to page data storage that includes latch-free access to the page data storage. In another aspect, a swap operation may be initiated, of a portion of a first page in cache layer storage to a location in secondary storage, based on initiating a prepending of a partial swap delta record to a page state associated with the first page, the partial swap delta record including a main memory address indicating a storage location of a flush delta record that indicates a location in secondary storage of a missing part of the first page. In another aspect, a page manager may initiate a flush operation of a first page in cache layer storage to a location in secondary storage, based on atomic operations with flush delta records.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 28, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: David B. Lomet, Justin Levandoski, Sudipta Sengupta
  • Patent number: 11204708
    Abstract: A method for managing data includes obtaining, by a backup agent, a migration request, wherein the migration request specifies a plurality of users, and in response to the migration request: identifying a set of source-format data sets in a backup storage system, mounting the set of source-format data sets from the backup storage system, performing data mining on the set of source-format data sets in response to the mounting to obtain a hierarchical structure, generating a cloud-based service user account for each user of the plurality of users, wherein the cloud-based service user accounts are associated with a cloud-based service, obtaining source-format data sets associated with each user of the plurality of users using the hierarchical structure, and initiating a migration of the source-format data sets to the cloud-based service.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: December 21, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Aneesh Kumar Gurindapalli, Deepthi Urs, Mahesh Reddy Appireddygari Venkataramana, Swaroop Shankar D H
  • Patent number: 11199892
    Abstract: An electro-optic module provides electro-optic signal drivers formed upon a semiconductor carrier having electrically conducting traces and passive circuit network filtering elements of electroceramic material with the electro-optic signal drivers being in electrical communication with the passive circuit elements and interface the module within a larger computing or communications system.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 14, 2021
    Inventor: L. Pierre de Rochemont
  • Patent number: 11200177
    Abstract: A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: December 14, 2021
    Assignee: ARM LIMITED
    Inventors: Alex James Waugh, Dimitrios Kaseridis, Klas Magnus Bruce, Michael Filippo, Joseph Michael Pusdesris, Jamshed Jalal
  • Patent number: 11199997
    Abstract: In one non-limiting embodiment, a method is disclosed for performing a storage device operation on a die is provide having steps of choosing a storage device operation to perform, estimating which die is related to the storage device operation chosen to be performed and performing the storage device operation at the die based on the estimating.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: December 14, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amir Shaharabany, Hadas Oshinsky
  • Patent number: 11199970
    Abstract: A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory stores a firmware that includes a plurality of mode page settings, and each mode page setting includes a plurality of mode parameters. The controller receives a data out message arranged to rewrite a first mode page setting among the plurality of mode page settings from a host. The controller determines whether the data out message will change the mode parameters which cannot be rewritten in the first mode page setting by performing bitwise logic operations on a new mode page setting in the data out message, preset values of the plurality of mode parameters of the first mode page setting, and a rewriteable setting for each bit of the first mode page setting.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: December 14, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Te-Kai Wang, Yu-Da Chen
  • Patent number: 11194709
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: December 7, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Michael Winterfeld, Steven S. Williams, Alex J. Wesenberg, Johnny A. Lam
  • Patent number: 11175850
    Abstract: Various implementations described herein relate to systems and methods for managing selective erasure in a Solid-State Drive (SSD) including receiving a selective erase command corresponding to erasing valid and invalid data mapped to a logical address and in response to receiving the selective erase command, erasing blocks in which one or more pages mapped to the logical address are located based on a mapping table that maps the logical address to the one or more pages. Both valid data and invalid data may be physically stored in one or more pages.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: November 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yaron Klein
  • Patent number: 11163678
    Abstract: A method of managing storage space for a metadata consistency checking procedure (MCCP) is provided. The method includes (a) tracking an amount of metadata and an amount of user data organized by the metadata; (b) provisioning a quantity of storage dedicated to the MCCP based, at least in part, on a ratio of the amount of metadata to the amount of user data; and (c) upon initiation of the MCCP, building tracking structures within the provisioned storage dedicated to the MCCP. An apparatus, system, and computer program product for performing a similar method are also provided.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: November 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Vamsi K. Vankamamidi, Philippe Armangau, Daniel E. Cummins