Abstract: A semiconductor device having a semiconductor element and a plurality of segments formed by dividing a conductive plate. Some of the segments are electrically coupled with electrodes of said semiconductor element and constitute lead pad portions as mounting electrodes of the semiconductor device. Other segments among the plurality of divided segments constitute die pad portions on which the semiconductor element is mounted. The plurality of divided segments and the semiconductor element are sealed and supported together by a resin material portion. The resin material portion fills the space between the divided segments as the lead pad portions. Semiconductor devices having various package sizes can be fabricated by using standardized common parts.

Abstract: A GaN based three layer buffer on a sapphire substrate provides a template for growth of a high quality I GaN layer as a substitute substrate for growth of a Nitride based LED.

Abstract: A method is described of manufacturing a semiconductor material having a zone (200) with p-conductivity type and n-conductivity type regions with dopant concentrations and dimensions such that, when the n- and p-conductivity type regions are depleted of free charge carriers the space charge per unit area of the regions balances at least to the extent that the resulting electric field is lower than that at which avalanche breakdown would occur in the area. The method starts with a semiconductor body having adjacent a first major surface (10b) a first semiconductor region (2) of one conductivity type. A mask (3, 4, 5) is provided on the first major surface, having at least one mask area masking a part (2a) of the first region. At least a part of the unmasked first region (2) is then removed to provide at least one opening (7) in the first region.

Abstract: A 60 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 60 degree bump placement structures is provided.

Abstract: A semiconductor chip, in accordance with the present invention, includes a substrate and a crack stop structure. The crack structure includes a first conductive line disposed over the substrate and at least two first contacts connected to the substrate and to the first conductive line. The at least two first contacts are spaced apart from each other and extend longitudinally along a length of the first conductive line. A second conductive line is disposed over a portion of the first conductive line, and at least two second contacts are connected to the first conductive line and the second conductive line. The at least two second contacts are spaced apart from each other and extend longitudinally along a length of the second conductive line.

Abstract: A semiconductor integrated circuit has a 3-dimmensional interconnection line structure for high-speed operation. One aspect of the present invention, there is provided a monolithic microwave integrated circuit (MMIC) having a 3-dimmensional tournament tree shaped multilayer interconnection lines, wherein a single electric feeding point on a top surface of the MMIC is divided, layer by layer, into plural electrodes on the semiconductor substrate of the MMIC via a plurality of laminated interconnection layers and vertical interconnection layers therebetween shaped like a tournament tree.

Abstract: The distance between a discrete or passive electrical component and an electrical semiconductor device and substrate or carrier is minimized by shortening the lead length connections of the passive component. One or more passive electronic components are mounted within the body of a carrier or board by creating a cavity in the substrate or carrier that is directly below a semiconductor device. The passive component is electrically connected to the substrate and device using solder bump technology resulting in much shorter lead length connections to and from the passive component.

Abstract: A low profile multi-IC chip package for high speed application comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage or, alternatively, are directly fixed to leads or pads on the host circuit board.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with An Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: A semiconductor device comprises a substrate having at least first, second and third metal layers formed over it. The metal layers comprise parallel strips. The strips of a given metal layer may be arranged such that they extend in a direction perpendicular to that of the direction in which the strips of a metal layer immediately above or below the given metal layer extend. The strips may further be arranged in parallel bands. The metal layers may comprise repeating patterns of strips. They may further provide customization. Vias may be formed to provide connections between metal layers. Such vias and/or one or more of the metal layers themselves may be used to provide customization.

Abstract: A method for forming a multilevel interconnect structure for an integrated circuit is disclosed. In an exemplary embodiment of the invention, the method includes forming a starting structure upon a substrate, the starting structure having a number of metallic conducting lines contained therein. A disk is bonded to the top of said starting structure, the disk including a plurality of mesh openings contained therein. The mesh openings are then filled with an insulative material, thereby forming a cap upon the startig structure, wherein the cap may structurally support additional interconnect layers subsequently formed thereatop.

Abstract: A semiconductor device is disclosed that includes a die having an active surface bearing integrated circuitry, the die including a plurality of bond pads thereon at least some of which are connected to the integrated circuitry and having at least one electrically conductive wire bond made between first and second bond pads of the plurality of bond pads for providing external electrical connection between the two bond pads.

Abstract: A semiconductor package includes a semiconductor chip. The semiconductor chip includes first and second electrodes disposed on a top side, and a third electrode disposed on a bottom side. A heat spreader is bonded to the third electrode. First and second conductive leads are electrically connected to the first and second electrodes through first and second conductive bonding members, respectively. The first and second leads respectively include foot portions at their lower ends, which are juxtaposed on a first side of the heat spreader. The heat spreader and the foot portions of the first and second leads have bottom faces, which are exposed on the bottom of an insulating sealing body, and are disposed on the same plane.

Abstract: A heat spreader, comprised of a plurality of carbon fibers oriented in a plurality of directions, with a carbon or metal matrix material dispersed about the fibers, is described. The carbon fibers facilitate the spreading of heat away from the smaller semiconductor device and up to a larger heat removal device, such as a heat sink.

Abstract: A power semiconductor module achieves high isolation strength from a base through selectively positioning a plurality of metal coatings on first and second surfaces and positioning edges of the plurality to beneficially reduce the field strength tangentially to a selected position, especially in a defined critical region directly adjacent a metal coating edge on a first surface opposite the base. This design results in regions which beneficially allow field lines to extend without functional detriment. The beneficial position selection is is achieved by means of an optimization process in which the tangential components of the field strength beside the first or second metallization edge reach identical values.

Abstract: The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member comprising a resin; the surface-protective film being formed of a polyimide. The present invention also provides a process for fabricating a resin-encapsulated semiconductor apparatus, comprising the steps of forming a film of a polyimide precursor composition on the surface of a semiconductor device having a ferroelectric film; heat-curing the polyimide precursor composition film to form a surface-protective film formed of a polyimide; and encapsulating, with an encapsulant resin, the semiconductor device on which the surface-protective film has been formed. The polyimide may preferably have a glass transition temperature of from 240° C. to 400° C. and a Young's modulus of from 2,600 MPa to 6 GPa. The curing may preferably be carried out at a temperature of from 230° C. to 300° C.

Abstract: A semiconductor chip assembly, comprises a first semiconductor chip having a front surface, a rear surface and contacts on the front surface and a second semiconductor chip having a front surface, a rear surface and contacts on the front surface. The rear surface of the second semiconductor chip is juxtaposed with the front surface of the first semiconductor chip. The assembly includes a first backing element having electrically conductive first terminals. The first backing element is juxtaposed with the rear surface of the first semiconductor chip so that at least some of the terminals overlie the rear surface of the first semiconductor chip. At least some of the contacts on the first and the second semiconductor chips are electrically connected to at least some of the terminals. The assembly includes a substrate having contact pads thereon. The first terminals are connected to the contact pads of the substrate. The substrate is adapted to connect the assembly with other elements of a circuit.

Abstract: An electrically conductive plug on a semiconductor workpiece. A dielectric layer is deposited on the workpiece, and a cavity is etched in the dielectric. An etchant-resistant material is deposited on the wall of the cavity adjacent the cavity mouth so as to form an inwardly-extending lateral protrusion, the etchant-resistant material being resistant to etching by at least one etchant substance which etches said electrically conductive material substantially faster than it etches the etchant resistant material. The cavity is filled by an electrically conductive material. In another aspect of the method, the etchant-resistant material can be omitted. Instead, upper and lower portions of the cavity are etched anisotropically and isotropically, respectively, so as to form a lower portion of the cavity that is wider than the upper portion.

Abstract: Thin-film microflex twisted-wire pair and other connectors are disclosed. Semiconductor packages include microflex technology that electrically connects at least one chip to another level of packaging. Microflex connectors, such as thin-film twisted-wire pair connectors according to the present invention provide superior electrical performance, which includes reduced line inductance, incorporation of integrated passive components, and attachment of discrete passive and active components to the microflex. All of these features enable operation of the chip at increased frequencies.

Abstract: A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires are used to attach the IC device to the printed board substrate and encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements.