Patents Examined by Sheila V. Clark
  • Patent number: 6621156
    Abstract: A semiconductor device in which a plurality of semiconductor chips are stacked. The semiconductor device includes a lower semiconductor chip bonded onto a surface of a wiring substrate; an upper semiconductor chip; and one or more spacers which are bonded to the surface of the wiring substrate and which support the upper chip over the lower chip and at a location separated from the lower chip. Conductors electrically connect the lower chip to the wiring substrate and extend through the spacers.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: September 16, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Naoto Kimura
  • Patent number: 6617680
    Abstract: A chip carrier, a semiconductor package and a fabricating method thereof are proposed, in which on one side of the chip carrier finally removed from an engaged surface of a mold in a de-molding process there is formed at least one grounding means corresponding in position to an eject pin of the mold, so as to allow a gear amount of electrical static generated on a surface of the semiconductor package during molding and de-molding to be discharged to the outside, instead of being retained on a semiconductor chip, conductive elements and conductive traces of the semiconductor package. This therefore can prevent electrical leakage and damage to the semiconductor chip from occurrence, and improve the quality and production efficiency for the semiconductor package.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: September 9, 2003
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chen Chien-Chih, Yu-Ting Lai, Chin-Wen Lai
  • Patent number: 6617697
    Abstract: The invention describes an assembly provided with a component and a substrate (7). The component and the substrate (7) are electrically interconnected by means of connecting structures (6, 8). The first connecting structure (6) of the component comprises aluminum, which simplifies the manufacture of the assembly.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: September 9, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Jose Solo De Zaldivar, Peter Baumgartner
  • Patent number: 6617630
    Abstract: The present invention provides a resin-encapsulated semiconductor apparatus comprising a semiconductor device having a ferroelectric film and a surface-protective film, and an encapsulant member comprising a resin; the surface-protective film being formed of a polyimide. The present invention also provides a process for fabricating a resin-encapsulated semiconductor apparatus, comprising the steps of forming a film of a polyimide precursor composition on the surface of a semiconductor device having a ferroelectric film; heat-curing the polyimide precursor composition film to form a surface-protective film formed of a polyimide; and encapsulating, with an encapsulant resin, the semiconductor device on which the surface-protective film has been formed. The polyimide may preferably have a glass transition temperature of from 240° C. to 400° C. and a Young's modulus of from 2,600 MPa to 6 GPa. The curing may preferably be carried out at a temperature of from 230° C. to 300° C.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: September 9, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Jun Tanaka, Keiko Isoda, Kiyoshi Ogata
  • Patent number: 6617679
    Abstract: There is provided by this invention a novel and unique configuration for combining multiple die such as metal oxide field effect transistors (MOSFETS) in high power high frequency applications to prevent internal oscillation. A first embodiment of this invention comprises a split gate design wherein the gate distribution network for multiple semiconductor devices is split to provide individual gate feeds to each device. A second embodiment provides a plurality of semiconductors devices arranged in a configuration such that the reference terminals are connected together at a common point at the approximate center of the configuration that allows external connections to the semiconductor devices' input and output terminals positioned on the outer periphery of the configuration design.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: September 9, 2003
    Assignee: Advanced Energy Industries, Inc.
    Inventor: Gideon van Zyl
  • Patent number: 6618404
    Abstract: A method and apparatus for accurately and precisely controlling the frequency (wavelength) and periodic frequency modulation of a laser are provided. An ADC (Analog to Digital Converter) is used to sample the output of a modified interferometer used as a delay line discriminator, and quadrature components of the sampled output are generated. An arctangent function (e.g., atan2) is applied to convert the quadrature components to a phase measure that is proportional to the laser frequency. Correlator circuits (e.g., cost-efficient correlator circuits) are provided to extract average frequency, modulation peak deviation, and modulation phase error signals. Control-loop feedback using the extracted signals is used to adjust the average frequency, modulation deviation, and modulation phase to respective set points.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: September 9, 2003
    Assignee: Lockheed Martin Corporation
    Inventor: Barry G. Mattox
  • Patent number: 6617685
    Abstract: A heat sink assembly includes a retainer having a body, a finger extending from the body and legs extending from the body. The assembly further includes a heat sink having a base and fins extending from the base, where slits in the fins define a trench. A package which includes an electronic device is located between a circuit board and the heat sink and the retainer holds the heat sink in place. To secure the heat sink with the retainer, the retainer is positioned so that the finger of the retainer is aligned with the trench of the heat sink and the legs of the retainer are aligned to slide around the circuit board. The retainer is then moved to slide the finger into the trench and the legs around the circuit board.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: September 9, 2003
    Assignee: Sun Microsystems, Inc.
    Inventor: Vernon P. Bollesen
  • Patent number: 6614122
    Abstract: An apparatus, comprising: a substrate having a surface; a die attached to the substrate surface; an underfill material positioned between the substrate surface and the die; and one or more barriers on the substrate surface adjoining the die, wherein the barriers controls flow of the underfill material.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: September 2, 2003
    Assignee: Intel Corporation
    Inventors: Thomas S. Dory, HengGee Lee, David W. Young, Leigh E. Wojewoda
  • Patent number: 6614096
    Abstract: Disclosed is a method for manufacturing a semiconductor device, which comprises the steps of forming a first insulating film made of a low dielectric constant material and containing carbon, subjecting the first insulating film to a surface treatment to reduce the carbon concentration of surface layer of the first insulating film, thus turning the surface layer into a low carbon concentration layer, forming a second insulating film on the low carbon concentration layer, forming a groove in the first and second insulating films for burying a metal therein, burying the metal in the groove formed in the first and second insulating films, and polishing a surface of the metal buried in the groove to thereby form a metal wiring.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: September 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Hideshi Miyajima
  • Patent number: 6614121
    Abstract: A semiconductor stack is provided. The semiconductor stack is comprised of a first semiconductor device, a second semiconductor device, and a socket. The first semiconductor device has a plurality of pins extending therefrom and arranged in a first preselected pattern. The socket is adapted to receive the plurality of pins. The second semiconductor device is disposed between the socket and the first semiconductor device and includes a die, a casing, and a plurality of electrical connections. The casing extends about the die and defines a plurality of openings extending therethrough. The openings are arranged in a first preselected pattern to receive the pins of the first semiconductor device. The plurality of electrical connections are disposed in at least a portion of the plurality of openings. The electrical connections are adapted to electrically communicate with the pins of the first semiconductor device inserted therein and the die.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: September 2, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Bryan Timothy Heenan
  • Patent number: 6611010
    Abstract: In a bit line contact section, a contact hole is formed through a silicon oxide film, and a contact plug made of a polysilicon film doped with impurities is buried in the contact hole. The silicon oxide film is formed with a wiring groove overlapping the contact hole. A bit line made of a metal film is buried in the wiring groove. The contact plug extends through the bit line, and has its upper surface substantially coplanar with an upper surface of the bit line. The contact plug is in contact with the bit line only on its side surfaces.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: August 26, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Goda, Kazuhiro Shimizu, Yuji Takeuchi, Riichiro Shirota, Seiichi Aritome
  • Patent number: 6611056
    Abstract: Provided are a composite material excellent in plastic workability, a method of producing the composite material, a heat-radiating board of a semiconductor equipment, and a semiconductor equipment to which this heat-radiating board is applied. This composite material comprises a metal and an inorganic compound formed to have a dendritic shape or a bar shape. In particular, this composite material is a copper composite material, which comprises 10 to 55 vol. % cuprous oxide (Cu2O) and the balance of copper (Cu) and incidental impurities and has a coefficient of thermal expansion in a temperature range from a room temperature to 300° C. of from 5×10−6 to 17×10−6/° C. and a thermal conductivity of 100 to 380 W/m·k. This composite material can be produced by a process comprising the steps of melting, casting and working and is applied to a heat-radiating board of a semiconductor article.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: August 26, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kazutaka Okamoto, Yasuo Kondo, Teruyoshi Abe, Yasuhisa Aono, Junya Kaneda, Ryuichi Saito, Yoshihiko Koike
  • Patent number: 6611063
    Abstract: A method for forming a mold-encapsulated semiconductor device includes the steps of mounting a semiconductor chip on a metallic plate having a metallic interconnect pattern thereon, encapsulating the semiconductor chip on the metallic interconnect pattern, removing the bottom of the metallic plate by etching to expose the metallic interconnect pattern, and forming external terminals on the bottom of the metallic interconnect pattern. The method reduces the thickness as well as the planar dimensions of the semiconductor device.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: August 26, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Michihiko Ichinose, Tomoko Takizawa, Hirokazu Honda, Keiichirou Kata
  • Patent number: 6608390
    Abstract: A wirebonded semiconductor package structure that provides for high frequency operation, a large number of I/O terminals, controlled low impedance, compensated inductance, electromagnetic shielding against cross-talk and prevention of false signals from ground bounce includes a semiconductor device, a semiconductor package substrate and a wirebond(s) electrically connecting the semiconductor device to the semiconductor package substrate. The wirebonded semiconductor package structure also includes a first insulating encapsulant layer at least partially encapsulating the wirebond(s) and a conductor layer (e.g., a patterned gold conductor layer) disposed on the first insulating encapsulant layer and electrically connected to the semiconductor package substrate. A method for manufacturing such a wirebonded semiconductor package includes wirebonding a semiconductor device (i.e.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: August 19, 2003
    Assignee: Kulicke & Soffa Investments, Inc.
    Inventors: David T. Beatson, Andrew F. Hmiel
  • Patent number: 6608387
    Abstract: A semiconductor device includes a support member having first and second major surfaces and an elongate hole extending between the first and second major surfaces. The hole has first and second elongate edges extending along a side of the support member and opposed to each other. A plurality of first and second external connection terminals is provided along each of the first and second edges. The first and second external connection terminals each have one end located above the second major surface of the support member. A semiconductor chip is provided on the first major surface of the support member. The semiconductor chip includes connection pads arranged along the hole. The connection pads are electrically connected to the other ends of the first and second external connection terminals by first and second connection wires, respectively. The hole is filled with an insulation material.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: August 19, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Kozono
  • Patent number: 6600219
    Abstract: A non-contact data carrier device has an upper layer pattern and a lower layer pattern having an antenna coil part made of wire pattern laid spirally and capacitor patterns. The upper and lower layer patterns are disposed on a surface and a back of a dielectric layer, respectively, in such a manner that the external forms of the respective antenna coil parts accord with each other so that a resonance circuit is formed. The non-contact data carrier device is provided with a portion of wire pattern of the antenna coil part which has the shape according to the external form of coil of data carrier chip. Data carrier chip is mounted on one of the portions of densely formed wire pattern in such a manner that a part of the shape of coil of data carrier chip conforms to the portion of densely formed wire pattern.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: July 29, 2003
    Assignee: Dainippon Printing Co., LTD
    Inventor: Takuya Higuchi
  • Patent number: 6593664
    Abstract: In a data carrier (1) with a chip module (3), the chip (5) of the chip module (3) is provided, in the region of its chip connecting layers (8), with a respective wire connecting means which is formed by a flat metal layer (10) and whereto an end (13), bonded in a wedge-shape fashion, of a bond wire (11) is connected.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: July 15, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Joachim Schober, Marcus Toth
  • Patent number: 6593652
    Abstract: A semiconductor device having: a wiring substrate; a semiconductor chip disposed thereon; and a heat radiating plate for radiating the heat generated from the semiconductor chip. A highly elastic member made of a synthetic resin is so disposed as to surround the semiconductor chip between the wiring substrate and the heat radiating plate.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: July 15, 2003
    Assignee: Rohm Co., Ltd.
    Inventor: Kazutaka Shibata
  • Patent number: 6590295
    Abstract: A microelectronic device including a substrate having a top metal layer, a first passivation layer overlying the substrate and wherein the passivation layer includes a via defined at least in part by a side wall of the passivation layer, and wherein the via overlies the top metal layer, a dielectric spacer positioned the via and the spacer having and inner wall with arcuate shape, an the electrically conductive redistribution layer having a portion positioned overlying the inner wall of the spacer and wherein the redistribution layer includes a portion in electrical contact with the top metal layer.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: July 8, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Che Liao, Chin-Kang Lee, Tao-Sheng Chang, Feng-Ru Chang
  • Patent number: 6590294
    Abstract: A device for bump probing and a method for fabricating the device are described. The device utilizes a bimorph-structured fingers for holding onto a solder bump, or a solder ball, without causing damages to the ball. The device further utilizes a direct current to cause an electrostatic force to flatten the probe fingers prior to attaching the fingers to a solder ball and for positioning the finger over a solder ball. After the electrostatic force is removed by disconnecting the direct current from the electrodes, the fingers grip onto the solder ball making electrical connection and performing testing. The invention further provides a micro-electro-mechanical-system technique for fabricating the probing device on a semiconducting substrate.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: July 8, 2003
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Hong Lee, Hsin-Li Lee