Abstract: A semiconductor device which includes: a semiconductor chip bonded to a surface of a solid device; and a stiffener surrounding the periphery of the semiconductor chip. A surface of the stiffener opposite from the solid device is generally flush with a surface of the semiconductor chip opposite from the solid device.

Abstract: An improved barrier stack for reducing plug oxidation in capacitor-over-plug structures is disclosed. The barrier stack is formed on a non-conductive adhesion layer of titanium oxide. The barrier stack includes first and second barrier layers wherein the second barrier layer covers the top surface and sidewalls of the first barrier layer. In one embodiment, the first barrier layer comprises Ir and the second barrier layer comprises IrOx. Above the barrier stack is formed a capacitor.

Abstract: A lead-frame for connecting and supporting an integrated circuit chip with a chip accommodating zone with inwardly extending ears for supporting the chip including minimum shoulder area, and having open crack and delamination stopping regions.

Abstract: A method and structure to electrically and mechanically join a first a first electrically conductive pad on a first substrate to a second electrically conductive pad on a second substrate using a solder joint that includes a low-melt solder alloy composition. The second electrically conductive pad has a geometry that compels a gap size of a gap between the first substrate and the second substrate to exceed a distance between the first substrate and a surface of the second pad.

Abstract: A silicon nitride read only memory and associated method of data programming and erasing. The read only memory includes a first type ion-doped semiconductor substrate, an oxide-nitride-oxide (ONO) composite layer over the semiconductor substrate, a first type ion-doped gate conductive layer over the ONO layer and a second type ion doped source/drain region in the substrate on each side of the ONO layer, wherein the second type ions have an electrical polarity opposite to the first type ions. Data is programmed into the silicon nitride read only memory by channel hot electron injection and data is erased from the silicon nitride read only memory by negative gate channel erase method. Since the gate conductive layer and the channel layer are identically doped, the energy gap between the two layers reduced. Hence, operating voltage of the gate terminal is lowered and damage to the tunnel oxide layer by hot holes is reduced.

Abstract: A high frequency semiconductor device includes semiconductor elements provided on a semiconductor substrate, a surface insulating layer for covering the semiconductor elements, at least one wiring layer which is provided above the surface insulating layer, with at least one insulating interlayer provided therebetween, and which combines with the ground potential to form transmission line, and at least one heat-radiating stud which is provided in at least one throughhole so as to penetrate said insulating interlayers and so as not to penetrate said surface insulating layer.

Abstract: A semiconductor device includes a plurality of conductors 2A each of which includes a first surface 20a, a second surface 20b opposite to the first surface, a thickness defined between these surfaces, and a thin-walled end portion 22a retreating from the first surface 20a toward the second surface 20b and having a side surface 24 connected to the second surface 20b. The device also includes a semiconductor chip 1 having a plurality of electrodes 10a, 10b electrically connected to the plurality of conductors 2A, respectively, and a resin package 3 for sealing the conductors 2A and the semiconductor chip 1 while exposing, for each conductor 2A, the side surface 24 of the thin-walled end portion 22a and at least apart of the second surface 20b connected to the side surface 24.

Abstract: A semiconductor device is formed from a die and a lead frame having one or more bus bars. Portions of the bus bars are overlain with an electrically insulative material while leaving bonding areas unobstructed, whereby bond wires which span the bus bar(s) may be bonded with a shorter wire and a lower loop, without the danger of shorting to the bus bar(s). The incidence of harmful wire sweep in the encapsulation step is also reduced.

Abstract: A semiconductor device includes a semiconductor chip having a bump electrode over its main surface. The bump electrode has at least one protrusion on the top surface thereof. A lead is electrically connected to the top surface of the bump electrode, and is positioned adjacent to the protrusion.

Abstract: The present invention provides a ball grid array semiconductor package having a resin coated metal core substrate. The semiconductor device comprises a resin coated metal core substrate, solder balls, chip adhesive material, at least one semiconductor chip, bonding wires, and encapsulant. The metal core is made from a conductive material, for example, a metal lead frame and coated with a resin to form a resin covered metal core substrate structure. The resin coating covers both sides of the metal core except for selected areas of the metal core, such as where it is desired to attach the bonding wires or the solder balls. A liquid encapsulant is formed to cover desired areas of the resin coated substrate, bonding wires, adhesive material, and the semiconductor chip. Since the outer surface of the substrate is substantially of resin material, the adhesion between the substrate and the encapsulant is much stronger than if a standard conventional substrate was used.

Abstract: A BGA semiconductor device using an insulating film and having air purge holes situated between metal through-holes in a base film serving as a substrate Stagnant air can be purged from voids formed between the insulating film arranged on the upper face of a wiring pattern on the base film and the wiring pattern via the air purge holes before electronic elements formed with chip bonding are packaged with asealing resin.

Abstract: A compliant interconnect assembly to electrically connect a first electronic device to a second electronic device comprises a contact set including an electrically insulating flexible film having at least one conductive contact suspended therein. The interconnect assembly also includes a compressible interposer as an electrically insulating elastomer sheet matrix for at least one electrically conducting elastic column to provide a localized conductive path through the thickness of the elastomer sheet. The electrically conducting elastic column comprises a central pillar of conductive spheroidal particles having a first average particle size. The central pillar has a first end opposite a second end. At least the first end has a particulate cap bonded to it including particles having a second average particle size that is less than the first average particle size.

Abstract: A semiconductor package structure for Flip Chip package includes at least an insulative core layer and a plurality of patterned circuit layers alternately stacking up each other. The patterned circuit layers are electrically connected each other wherein one of the patterned circuit layers is positioned on the surface of the substrate. The patterned circuit layer includes a plurality of bump pads, and each of the bump pads has an etching hole. The solder mask layer covers the surface of the patterned circuit layer and a portion of the surface of the outer edge of the bump pads, and exposes the etching holes. The solder mask layer may also expose the whole surface of the bump pads.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: A lead frame for a semiconductor device. The lead frame has a layer defining a first unit lead frame including a first support for a semiconductor chip and a plurality of leads spaced around the first support. The first support has a peripheral edge. The layer further defines a guide rail extending along at least a portion of the peripheral edge and connected to at least one of the leads. At least one notch is formed in the layer between the at least one lead and a part of the guide rail so as to define a first tie bar.

Abstract: A semiconductor package and its production method in which the semiconductor package is produced by having via holes for electrically connecting top and bottom surface of a double-sided copper clad substrate and cutting the substrate at a line separating the via holes into half. The semiconductor package includes a plurality of wiring patterns on the double-sided copper clad substrate, via holes for interconnecting the top and bottom sides of the substrate and having a long hole shape so that the via hole is shared by adjacent semiconductor packages when the substrate is cut and separated, semiconductor chips mounted on predetermined positions on the substrate, and resin for sealing an entire body of the substrate.

Abstract: The present invention provides a semiconductor device bonded to a wiring board in a flip-chip bonding manner, wherein bumps for the flip-chip bonding are formed on a front surface of the semiconductor element, and a wiring pattern to which bumps and bonding wires for another semiconductor element are connected is formed on a back surface of the semiconductor element. The present invention also provides a semiconductor device structure including a first semiconductor element and a second semiconductor element sequentially stacked in multi-stages on a wiring board by flip-chip bonding, wherein a wiring pattern of the first semiconductor element is bonded to segments of wiring formed on the wiring board by means of bonding wires. With this configuration, it is possible to realize a thin semiconductor device of a stacked structure including a plurality of semiconductor elements mounted at a higher density and hence to miniaturize an electronic device using the semiconductor device.

Abstract: A plurality of wiring layers are laminated on an LSI chip. Each wiring layer includes an electrode to which is applied a mechanical pressure, a first insulating film formed in a region where it is necessary to have a high mechanical strength and having the electrode formed therein, a second insulating film formed in the same layer as the layer of the first insulating film and formed in a region where a mechanical strength higher than that of the first insulating layer is not required, and a wiring layer formed on the surface of the second insulating film.

Abstract: An offset die stacking arrangement is disclosed having at least one upper level die having a width which is less than the distance separating the opposing bonding sites of the underlying die. The lowest die is affixed to the substrate within a recess in the substrate. The upper die is fixed above the lower die and rotated within a plane parallel to the lower die through an angle which insures that none of the bonding sites of the lower die are obstructed by the upper die. Once the dice are fixed in this manner, the entire assembly is subjected to the wire bonding process with all of the bonds being made in the same step.

Abstract: A semiconductor package having a plurality of conductors arrayed in two (or more) parallel planes, and an available ground conductor. Conductors in the auxiliary or second plane substantially overlay the primary signal conductors in the first plane, and the impedance of any lead or lead pair is arbitrarily set at the assembly process by connecting the auxiliary conductors to ground or by leaving them floating. Differential pairs of signal conductors, either odd or even mode are set by connecting the auxiliary conductors to a ground contact.