Abstract: An apparatus for avoiding a collision between data. The apparatus includes a plurality of integrated circuits (ICs) configured to mutually perform insulation communication, an amplitude detection module configured to detect amplitudes of transmission data and reception data that are input and output through pins of the IC during the insulation communication between the plurality of ICs, and a signal pattern error detection module configured to determine a collision situation between the transmission data and the reception data by comparing an amplitude of transmission data, which is generated by a processor in a TX mode of the IC, and the amplitude of the transmission data, which is detected through the pins of the IC by the amplitude detection module.

Abstract: A storage device syndrome-weight-based error correction system includes a syndrome-weight-based error correction subsystem coupled to a storage subsystem in a chassis. The syndrome-weight-based error correction subsystem performs a plurality of respective first error correction hard decoding operations on the storage subsystem that each utilize respective read voltage thresholds and that each generate a respective final codeword candidate having a respective syndrome weight.

Abstract: A block processing method, node and medium are provided. The method includes: determining, in a metro transport network, Ethernet or flexible Ethernet, 64B/66B blocks of a forward error correction (FEC) codeword with errors that cannot been corrected; replacing all of the 64B/66B blocks in the FEC codeword with error control blocks, or replacing each invalid 64B/66B block in the FEC codeword with an error control block.

Abstract: The invention relates to systems, methods, network devices, and machine-readable media for encoding an input message with robustness against noise by executing a compressing hash function on the input message, encoding an output of the hash function and the input message to generate a single combined message, executing a permutation function on the combined message, and encoding the result of the permutation function with a list-decodable code.

Abstract: Message faults are caused by network crowding and signal fading at high frequencies of 5G and 6G. Current error-detection and correction algorithms are computationally demanding, especially for new low-cost reduced-capability IoT devices. Disclosed are methods for (a) determining whether a message is faulted using a compact error-detection code, (b) localizing the most likely faulted message element(s) according to the waveform signal, and (c) determining the likely corrected version by back-calculating from the error-detection code. Other versions include testing various modulation substitutions for the most suspicious message elements, having the worst signal quality. The waveform parameters may include a deviation from an average amplitude, phase, frequency, or polarization, as well as an amount of amplitude variation and phase variation within the message element. Identification of the most likely faulted message elements may enable recovery of the message without a costly retransmission.

Abstract: A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.

Abstract: An apparatus comprising circuitry configured to: receive a plurality of signal samples, wherein at least two of the signal samples are received on different carrier frequencies or over different durations; convert the plurality of signal samples to a common data format that stores as entries the samples, a stored entry corresponding to a sample measured with a carrier frequency, a time, and a receive antenna; generate entries of the common data format that are missing due to a sample not being measured with a carrier frequency, time, and receive antenna; wherein the entries of the common data format are ranked, wherein a higher ranking entry is considered more relevant than a relatively lower ranking entry; and generate at least one positioning measurement with a machine learning model, based on the entries of the common data format and the ranking of the entries of the common data format.

Abstract: A HARQ-ACK feedback method and apparatus are provided, so as to solve a problem that a terminal cannot perform HARQ-ACK feedback in a case that the terminal is configured with a DL SPS. The method may be applied to a terminal. The method includes determining, based on first information, a HARQ-ACK codebook corresponding to M DL SPS configurations; where the first information includes at least one of the following: first HARQ-ACK feedback indication information, first TDD configuration information, or first dynamic slot format information; and M?1, and M is an integer.

Abstract: Systems and methods are disclosed herein that provide low latency data communication with improved physical link layer reliability through repeated physical layer retransmission of data over a data connection whenever the connection is idle (i.e., no new data to send). In some embodiments, the transmission of administrative control symbols (e.g. “idles,” “commas”, etc.) can be suppressed or otherwise reduced to allow some of the available connection bandwidth to be used for data redundancy and fault tolerance through the repeated retransmission of data as described in more detail below. Accordingly, instead of executing time-consuming error correcting routines, a receive node can discard the erroneous data frame and process at least one repeat frame that carries the same data payload. Sequence numbers and/or other repeat indicators can be used to distinguish original frames from repeat frames and/or for identifying which frames carry the same data payload.

Abstract: A method is provided for decompressing wide word data compressed in parallel. The method includes creating an instance of memory structure for a wide word in the wide word data, where the instance of memory structure is an inverse of a compression dictionary for the wide word; retrieving multiple compressed codes iteratively from a gap-free compressed output stream of the wide word data using the instance of memory structure, where each compressed code includes at least one character code and a reverse-pointer, and where at least one compressed code includes a multi-symbol string having a multiple character codes; forming an intermediate decompressed output stream by iteratively following the reverse-pointers for the multiple compressed codes, respectively; and forming decompressed output stream by reversing an order of the character codes in the multi-symbol string of the at least one compressed code.

Abstract: Methods, systems, and devices for enhanced negative acknowledgment control (NAC) frame are described. A device may generate and communicate an enhanced NAC frame that includes additional error information to indicate to the device a cause for the error. The device may receive a data frame and determine an error condition associated with a set of layers of a protocol stack. The device may generate feedback indicating a cause for the determined error condition and transmit the feedback indicating the error cause. The feedback may be a NAC that includes a first quantity of bits configured for indicating an existence of an error and a second quantity of bits configured for indicating the error cause. A format of the NAC frame may include bits configured to identify multiple types of error causes associated with the different layers of the protocol stack.

Abstract: Disclosed are systems and methods for transmission and reception of data bits. A plurality of data bits are received. FEC-based encoded data bits are generated in accordance with a zipper code framework incorporating component non-binary codes. The zipper code framework includes a buffer having a virtual buffer and a real buffer. Codewords associated with the FEC-based encoded data bits are stored in rows of the real buffer. A given codeword in a given row of the real buffer is mapped to different rows of the virtual buffer in a quasi-diagonal interleaving manner.

Abstract: A method is provided for reducing data stored in a capture buffer of an interposer circuit during communication of the data over a data link according to a high-speed, layered packet-based protocol for analysis. The method includes performing data integrity checks of the data in real time, and omitting data integrity bits corresponding to the data integrity checks from transaction layer packets (TLPs) and data link layer packets (DLLPs) of the data when the data integrity checks indicate the data is correct; performing acknowledge and negative acknowledge (ACK/NACK) matching in real time to confirm successful delivery of the TLPs of the data using ACK/NACK packets, where the ACK/NACK packets are omitted from being stored in the capture buffer; removing and/or reducing fields in real time from the TLPs and/or the DLLPs of the data; and compressing data payloads of the TLPs and/or the DLLPs of the data in parallel.

Abstract: A new approach is proposed to support device under test (DUT) validation reuse across a plurality of platforms, e.g., hardware simulation, hardware emulation, and post-silicon validation. First, an inference profile used for an inference operation of an application, e.g., a machine learning (ML) application, is generated based on a set of profile configurations, a set of test parameters, and a set of randomized constraints. A plurality of math functions specified by, e.g., an architecture team, for the ML application are also statically and/or dynamically verified via block simulation and/or formal verification. An inference model for the DUT is then built based on the inference profile and the plurality of verified math functions. Finally, an inference database including one or more of stimulus, DUT configurations, input data and predicted output results is generated based on the inference model, wherein the inference database for the DUT is reusable across the plurality of platforms.

Abstract: A universal asynchronous receiver/transmitter includes a transmission register to include information to be transmitted, a receive register to include information received, a frame error checking circuit to evaluate contents of the receive register for a frame error, and control logic. The control logic is to route the contents of the transmission register to the receive register. The control logic is to, during transmission of the contents of the transmission register through the reprogrammable pin to the receive register, modify a bit inversion register to yield modified contents to be provided to the receive register. The modified contents are to cause a frame error. The control logic is to determine whether the frame error checking circuit detected the frame error.

Abstract: A radio communication link is established between first and second nodes in a cellular network, which comprise at least channel coding and decoding of first and second Physical (PHY) layers and first and second Medium Access Control (MAC) sublayers. User data is transmitted from the first node to the second node while applying a PHY Forward Error Correction (FEC) algorithm in transmission for coding and in reception for decoding by the first and second PHY layers. A value of a PHY-FEC error metric is computed with respect to errors in the user data received by the second node that are uncorrected by the PHY FEC algorithm. The received user data including the uncorrected errors is transferred from the second PHY layer to the second MAC sublayer, subject to the value of the PHY-FEC error metric being less than a threshold used by an error tolerance procedure.

Abstract: The technology disclosed herein comprises a processor; a memory to store data and a plurality of error correcting code (ECC) bits associated with the data; and a memory controller coupled to the memory, the memory controller to receive a write request from the processor and, when an access control field is selected in the write request, perform an exclusive OR (XOR) operation on the plurality of ECC bits and a fixed encoding pattern to generate a plurality of encoded ECC bits and store the data and the plurality of encoded ECC bits in the memory.

Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

Abstract: A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.

Abstract: A receiver may use a trained AI model to recover a faulted 5G/6G message by interpreting the meaning or intent of the message by correlating the message content with one of the “expected” message types. For example, the AI model may consider changes to the message, for consistency with an associated error-detection code, thereby producing a series of candidate messages. The AI model can then determine a likelihood that each of the candidate messages is correct, in the context of the receiver (such as an action or condition of the receiver, or a planned activity of the receiver) or is commonly received in that context. For example, the AI model can be trained to recognize the expected messages or message types, and thereby indicate which candidate message has the highest likelihood of being correct. The AI model may also consider waveform parameters to identify likely faults.