Patents Examined by Shelly A Chase
  • Patent number: 12379840
    Abstract: A storage network operates by: issuing read slice requests to storage units of a set of storage units, where the read slice requests identify at least a read threshold number of encoded slices of a set of encoded slices corresponding to a data segment; when less than the read threshold number of encoded slices are received within a time threshold, facilitating receiving a decode threshold number of encoded slices of the set of encoded slices; decoding the decode threshold number of encoded slices to produce recovered encoded data slices, wherein a number of the recovered encoded data slices corresponds to the read threshold number minus a number of the encoded slices received within the time threshold; and outputting the recovered encoded data slices and the encoded slices of the read threshold number of encoded slices received within the time threshold.
    Type: Grant
    Filed: March 1, 2024
    Date of Patent: August 5, 2025
    Assignee: Pure Storage, Inc.
    Inventors: Bruno H. Cabral, Wesley B. Leggette
  • Patent number: 12373318
    Abstract: A disclosed method may include (i) initiating a cellular field testing tool that tests a condition of cellular network connectivity of a device under test, (ii) checking, prior to starting a specific test of the cellular field testing tool, whether each precondition in a set of preconditions is satisfied, and (iii) preventing the cellular field testing tool from starting the specific test until each precondition in the set of preconditions is satisfied. Related systems and computer-readable mediums are further disclosed.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: July 29, 2025
    Assignee: DISH Wireless L.L.C.
    Inventors: Nikhil Rangaraajan Vijayakumar, Andrew Allan, In-Kyung Kim
  • Patent number: 12368531
    Abstract: In an example, a method for delivering a multimedia data stream includes determining a frequency for generating one or more repair packets and a placement for positioning the one or more repair packets in the multimedia data stream based on a configuration parameter related to the multimedia data stream. The frequency and the placement may be determined based on a priority derived from a multimedia delivery use-case. Further, the method includes generating the one or more repair packets by network coding source packets of the multimedia data stream based on the determined frequency and the placement and transmitting the network coded multimedia data stream with the repair packets to a receiving device.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: July 22, 2025
    Inventors: Shailesh Ramamurthy, Swapan Kumar Kundu, Murali Babu Muthukrishnan, Arunkumar Mohananchettiar
  • Patent number: 12360845
    Abstract: Disclosed are methods, systems, devices, circuits. and other implementations, including a method for error identification and correction that includes obtaining from a memory device coded input data, the coded input data previously encoded by multiplying a source data element by a pre-determined multiplier, and stored in the memory device, and performing a decoding operation on the coded input data obtained from the memory device, with the decoding operation including at least a modulo operation, to derive a resultant decoded data element and a remainder portion. The method further includes determining whether the coded input data includes a corrupted portion based on a value of the remainder portion.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: July 15, 2025
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Lakshminarasimhan Sethumadhavan, Evgeny Manzhosov
  • Patent number: 12348312
    Abstract: Methods for transmitting and receiving an audio stream are provided. For transmission, the method involves obtaining a frame of an audio signal, determining a number of source blocks to divide the frame of the audio signal into and a number of parity blocks to generate for forward error correction, wherein the number of source blocks and the number of parity blocks are determined based on characteristics of a wireless communication protocol to be used. The wireless communication protocol may be BLUETOOTH. The parity blocks are usable by a decoder to reconstruct one or more corrupted or missing source blocks and may be obtained by means of Reed-Solomon encoding.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: July 1, 2025
    Assignee: Dolby International AB
    Inventor: Gael Lassure
  • Patent number: 12348311
    Abstract: A system and method for 5G new radio (NR) low-density low density parity check (LDPC) decoding comprising performing a Fast Fourier Transform using a Fast Fourier Transform algorithm. The system and method determines if a reference sequence is present and performing a channel estimate and a channel interpolate for the channel estimate if the reference sequence is present. The system and method demodulates at least one orthogonal frequency division multiplexing (OFDM) symbol according to rbin*conj(Hbin)/(norm(Hbin)2+Noise_Power). The system and method decodes the demodulated at least one orthogonal frequency division multiplexing symbol, and determines if the decoded at least one orthogonal frequency division multiplexing symbol is correct.
    Type: Grant
    Filed: February 19, 2024
    Date of Patent: July 1, 2025
    Assignee: PCTEL, INC.
    Inventors: Wei Zha, Kamran Ghavami, Amir Soltanian
  • Patent number: 12341608
    Abstract: A method for link transition in a USB device includes transmitting a plurality of first RS-FEC blocks by a first transmitter, receiving an UNBOND set by a receiver, waking up a second transmitter by a LASM when the receiver receives the UNBOND set, transmitting a training sequence by the second transmitter, transmitting a specific pattern sequence by the second transmitter after finishing transmitting the training sequence, determining whether a current RS-FEC block to be transmitted by the first transmitter is a DESKEW block, stopping transmitting the specific pattern sequence if the current RS-FEC block is determined to be the DESKEW block, and transmitting a plurality of second RS-FEC blocks by the first transmitter and the second transmitter.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: June 24, 2025
    Assignee: MEDIATEK INC.
    Inventors: Yu-Cheng Chen, Chih-Chieh Wang
  • Patent number: 12335036
    Abstract: A method for link transitions in a Universal Serial Bus system includes transmitting a plurality of first RS-FEC blocks by a first transmitter of the USB system, transmitting a training sequence by a second transmitter of the USB system, determining number of sets in a first RS-FEC block which have been transmitted by the first transmitter when the second transmitter completes transmitting the training sequence, generating a specific pattern sequence according to the number of sets in the first RS-FEC block which have been transmitted by the first transmitter and a total number of sets in the first RS-FEC block, and transmitting the specific pattern sequence by the second transmitter.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: June 17, 2025
    Assignee: MEDIATEK INC.
    Inventors: Yu-Cheng Chen, Chih-Chieh Wang
  • Patent number: 12334956
    Abstract: A data processing method for a DNN model includes: reading weights of transmission data; quantizing each weight into bits sequentially including first, second, third, and fourth-type bits; sequentially interleaving the first-type bit into a first bit set; sequentially interleaving each second-type bit into second bit sets and reading a second compression rate of each second bit set in response to the compressible second bit sets; interleaving the third-type bit into a third bit set and reading a third compression rate of the third bit set in response to the compressible third bit set; compressing each second bit set with the second compression rate, and compressing the third bit set with the third compression rate; sequentially coding the first bit set, each compressed second bit set, and the compressed third bit set to generate first encoded data corresponding to the transmission data; transmitting the first encoded data to an external device.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: June 17, 2025
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Chih Huang, Li-Yang Tseng
  • Patent number: 12327588
    Abstract: A process is provided to trim PCRAM cells to have consistent programming curves. Initial programming curves of PCRAM cells are measured. A target programming curve is set up for the PCRAM cells. Each PCRAM cell is then modulated individually to meet the target programming curve.
    Type: Grant
    Filed: November 21, 2023
    Date of Patent: June 10, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jau-Yi Wu
  • Patent number: 12316446
    Abstract: A first flit is generated according to a first flit format, where a first number of error detection codes are to be provided for an amount of data to be sent in the first flit, and the first flit is to be sent on a link by the transmitter while the link operates with a first link width. The link transitions from a first link width to a second link width, where the second link width is narrower than the first link width. A second flit is generated according to a second flit format based on the transition to the second link width, where the second flit is to be sent while the link operates at the second link width, and the second flit format defines that a second, higher number of error detection codes are to be provided for the same amount of data.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: May 27, 2025
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • Patent number: 12301255
    Abstract: A low density parity check (LDPC) channel encoding method is used in a wireless communications system. A communication device encodes an input bit sequence by using an LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The base matrix may be one of eight exemplary designs. The encoding method can be used in various communications systems including fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.
    Type: Grant
    Filed: May 24, 2024
    Date of Patent: May 13, 2025
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jie Jin, Wen Tong, Jun Wang, Aleksandr Aleksandrovich Petiushko, Ivan Leonidovich Mazurenko, Chaolong Zhang
  • Patent number: 12301260
    Abstract: A non-transitory computer-readable medium, method and system, the system including processing circuitry. The processing circuitry is to generate a first matrix, perform an incident cycle optimization process using the first matrix to generate a modified first matrix, and perform an encoder gate optimization process using the modified first matrix to generate a further modified first matrix. Processing circuitry is then to generate a second matrix including the further modified first matrix as a submatrix of the second matrix, perform the incident cycle optimization process using the second matrix to generate a modified second matrix, and perform the encoder gate optimization process using the further modified first matrix and the modified second matrix to generate a further modified second matrix.
    Type: Grant
    Filed: November 13, 2023
    Date of Patent: May 13, 2025
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Young Hoon Ji, Nathan Poon
  • Patent number: 12273195
    Abstract: Message faulting is expected to be a major challenge in 5G-Advanced and especially 6G, due to increased pathloss and phase noise at FR2 frequencies, and exponential crowding of networks. Legacy methods for forward-correction or automatic retransmissions are unsuitable to the fast-paced demands of next-generation users. Therefore, disclosed herein is an AI-based receiver that interprets a corrupted message to determine the most likely meaning or intent, and thereby provides one or more candidate corrected messages along with a likelihood that each of the candidate corrected messages is indeed correct. The AI model may also be provided with data on the context or current activity of the receiver, data on the waveform of each message element, and other data available to the receiver, so that the AI model can further refine the likelihood values. By recovering corrupted messages in the receiver, a costly retransmission may be avoided, saving time and resource usage.
    Type: Grant
    Filed: June 29, 2024
    Date of Patent: April 8, 2025
    Inventors: David E. Newman, R. Kemp Massengill
  • Patent number: 12267162
    Abstract: Embodiments of this application provide a method for coding in a wireless communication network. A communication device interleave a first bit sequence to obtain a first interleaved sequence having sequence number starting with a sequence number of 0, wherein the first bit sequence comprises bits for indicating timing, wherein the bits for indicating timing comprises a set of bits for indicating synchronization signal block index (SSBI); wherein the set of bits for indicating SSBI are placed in positions indicated by sequence numbers of 2, 3 and 5 in the first interleaved sequence. The devices add d first CRC bits on the first interleaved sequence to obtain a second bit sequence, interleave on the second bit sequence according to an interleave pattern to obtain a second interleaved sequence, and polar encode the second interleaved sequence to obtain the encoded sequence.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: April 1, 2025
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hejia Luo, Yinggang Du, Rong Li, Lingchen Huang, Ying Chen
  • Patent number: 12265124
    Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N?1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N?1 number of redundant flip-flops is observed through the functional path to determine faults.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: April 1, 2025
    Assignee: STMicroelectronics International N.V.
    Inventors: Sandeep Jain, Akshay Kumar Jain, Jeena Mary George
  • Patent number: 12260129
    Abstract: Disclosed herein are related to a system and a method for adjusting a read voltage threshold to read data from a plurality of memory dies of a nonvolatile memory device. Each of the plurality of memory dies comprises a plurality of blocks. A controller in communication with the plurality of memory dies may read, from a first block of the plurality of blocks, data corresponding to a read command received from a host. The controller may determine a bit error rate for the first block based on the data. The controller may update the read voltage threshold for the first block when the bit error rate for the first block exceeds a first error threshold. The read voltage threshold may be stored in the controller.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: March 25, 2025
    Assignee: KIOXIA CORPORATION
    Inventors: Ofir Kanter, Avi Steiner
  • Patent number: 12253561
    Abstract: According to one embodiment, a semiconductor device includes a first chip and a second chip arranged on a substrate, the first chip outputs first time stamp data and first trace data in which a time stamp value is associated with a first execution result obtained by executing software, the second chip outputs second trace data in which a difference value with a marker is associated with a second execution result obtained by executing the software, the second execution result obtained by the second chip executing the software is associated with a third time stamp value calculated based on a second time stamp value and the difference value in a debugger.
    Type: Grant
    Filed: October 10, 2023
    Date of Patent: March 18, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masahide Matsumoto, Kazunori Ochiai, Tomoyoshi Ujii
  • Patent number: 12250004
    Abstract: Disclosed is a storage device which includes a nonvolatile memory device, and a memory controller that performs a read operation on the nonvolatile memory device and performs an error correction operation on data read in the read operation. In the error correction operation, the memory controller estimates an error rate of the read data, and determines whether to perform a read retry operation based on the estimated error rate.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: March 11, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: YongSung Kil, Soonyoung Kang, Hong Rak Son, Kangseok Lee
  • Patent number: 12242336
    Abstract: Systems and devices can include a physical layer (PHY) that includes a logical PHY to support multiple interconnect protocols. The logical PHY can include a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol, and a second set of CRC encoders corresponding to a second interconnect protocol. A multiplexer can direct data to the first set or the second set of CRC encoders based on a selected interconnect protocol. The logical PHY can include a first set of error correcting code (ECC) encoders corresponding to the first interconnect protocol and a second set of ECC encoders corresponding to the second interconnect protocol. The multiplexer can direct data to the first set or the second set of ECC encoders based on the selected interconnect protocol. In embodiments, different CRC/ECC combinations can be used based on the interconnect protocol and the link operational conditions.
    Type: Grant
    Filed: August 25, 2023
    Date of Patent: March 4, 2025
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma