Abstract: Message faulting is expected to be a major challenge in 5G-Advanced and especially 6G, due to increased pathloss and phase noise at FR2 frequencies, and exponential crowding of networks. Legacy methods for forward-correction or automatic retransmissions are unsuitable to the fast-paced demands of next-generation users. Therefore, disclosed herein is an AI-based receiver that interprets a corrupted message to determine the most likely meaning or intent, and thereby provides one or more candidate corrected messages along with a likelihood that each of the candidate corrected messages is indeed correct. The AI model may also be provided with data on the context or current activity of the receiver, data on the waveform of each message element, and other data available to the receiver, so that the AI model can further refine the likelihood values. By recovering corrupted messages in the receiver, a costly retransmission may be avoided, saving time and resource usage.

Abstract: Embodiments of this application provide a method for coding in a wireless communication network. A communication device interleave a first bit sequence to obtain a first interleaved sequence having sequence number starting with a sequence number of 0, wherein the first bit sequence comprises bits for indicating timing, wherein the bits for indicating timing comprises a set of bits for indicating synchronization signal block index (SSBI); wherein the set of bits for indicating SSBI are placed in positions indicated by sequence numbers of 2, 3 and 5 in the first interleaved sequence. The devices add d first CRC bits on the first interleaved sequence to obtain a second bit sequence, interleave on the second bit sequence according to an interleave pattern to obtain a second interleaved sequence, and polar encode the second interleaved sequence to obtain the encoded sequence.

Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N?1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N?1 number of redundant flip-flops is observed through the functional path to determine faults.

Abstract: Disclosed herein are related to a system and a method for adjusting a read voltage threshold to read data from a plurality of memory dies of a nonvolatile memory device. Each of the plurality of memory dies comprises a plurality of blocks. A controller in communication with the plurality of memory dies may read, from a first block of the plurality of blocks, data corresponding to a read command received from a host. The controller may determine a bit error rate for the first block based on the data. The controller may update the read voltage threshold for the first block when the bit error rate for the first block exceeds a first error threshold. The read voltage threshold may be stored in the controller.

Abstract: According to one embodiment, a semiconductor device includes a first chip and a second chip arranged on a substrate, the first chip outputs first time stamp data and first trace data in which a time stamp value is associated with a first execution result obtained by executing software, the second chip outputs second trace data in which a difference value with a marker is associated with a second execution result obtained by executing the software, the second execution result obtained by the second chip executing the software is associated with a third time stamp value calculated based on a second time stamp value and the difference value in a debugger.

Abstract: Disclosed is a storage device which includes a nonvolatile memory device, and a memory controller that performs a read operation on the nonvolatile memory device and performs an error correction operation on data read in the read operation. In the error correction operation, the memory controller estimates an error rate of the read data, and determines whether to perform a read retry operation based on the estimated error rate.

Abstract: Systems and devices can include a physical layer (PHY) that includes a logical PHY to support multiple interconnect protocols. The logical PHY can include a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol, and a second set of CRC encoders corresponding to a second interconnect protocol. A multiplexer can direct data to the first set or the second set of CRC encoders based on a selected interconnect protocol. The logical PHY can include a first set of error correcting code (ECC) encoders corresponding to the first interconnect protocol and a second set of ECC encoders corresponding to the second interconnect protocol. The multiplexer can direct data to the first set or the second set of ECC encoders based on the selected interconnect protocol. In embodiments, different CRC/ECC combinations can be used based on the interconnect protocol and the link operational conditions.

Abstract: Provided are an information processing device, an encoding method, and a decoding method that implement low latency communication. An information processing device of the present disclosure includes a first processing unit that performs processing of a first protocol layer including processing of generating first coded data by encoding first data with an erasure correction code that is a first code, and provides the first coded data to a second protocol layer lower than the first protocol layer.

Abstract: A data storage device includes at least one signal processing circuit to perform an error recovery procedure when an error has occurred in the data storage device. When performing the error recovery procedure, the signal processing circuit determines which type of line reset is to be performed according to a device identifier. When the device identifier satisfies a predetermined condition, the signal processing circuit performs an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device in a predetermined period until the predetermined period expires or another line reset signal representing an acknowledgment of the line reset signal is received from the peer device; and when the device identifier does not satisfy the predetermined condition, the signal processing circuit performs an operation of one-shot line reset to transmit the line reset signal to the peer device for only one time.

Abstract: A linearity test system for a chip, a linearity signal providing device, and a linearity test method for the chip are provided. The linearity test method for the chip includes steps as follows: providing a reference clock signal and a receiver input signal to a chip under test, wherein the reference clock signal and the receiver input signal have a phase difference in time domain; and determining a linearity of a phase interpolator of the chip under test based on a plurality of phase signals of the chip under test corresponding to the reference clock signal and the receiver input signal.

Abstract: Techniques for forward error correction are disclosed. These techniques include receiving a forward error correction codeword transmitted over a communication network, the codeword including a parity portion and a payload portion. The techniques further include determining, based on the parity portion, to disable forward error correction for the codeword. The techniques further include disabling forward error correction for the codeword.

Abstract: An on-die controller can provide an error correction capability for data stored in an array of memory cells located on the same die as the on-die controller. The error correction capability provided by the on-die controller eliminates a need to transfer error correction code (ECC) data to an external controller that may have provided the error correction capability in lieu of the on-die controller, which can provide more channel bandwidth for other types of non-user data for further strengthening data reliability, security, integrity of the memory system.

Abstract: An embodiment of the present disclosure contemplates a data sending and receiving method and apparatus. A first FEC unit of a sending device sends, by using a first channel, a first data stream on which first FEC encoding has been performed; a second FEC unit of the sending device sends, by using a second channel, a second data stream on which second FEC encoding has been performed; and the sending device performs interleaving on the first data stream and the second data stream, to obtain an output data stream, and sends the output data stream to a receiving device.

Abstract: This application relates to communicating information between communication devices. A channel coding method is disclosed. A communication device obtains an input sequence of K bits. The communication device encodes the input sequence using a low density parity check (LDPC) matrix H, to obtain an encoded sequence. The LDPC matrix H is determined according to a base matrix and a lifting factor Z. The base matrix includes m rows and n columns, m is greater than or equal to 5, and n is greater than or equal to 27. The lifting factor Z satisfies a relationship of 22*Z?K. According to the encoding method provided in the embodiments, information bit sequences of a plurality of lengths can be encoded for transmission between the communication devices.

Abstract: Provided is an apparatus including an acquisition unit that acquires an information block generated from transmission data for a user and subjected to error correction coding, and an interleaving unit that interleaves a bit sequence of the information block using an interleaver unique to the user. The interleaving unit interleaves the bit sequence by interleaving each of two or more partial sequences obtained from the bit sequence.

Abstract: Techniques are described for deploying a fault tolerant data center by determining that the physical infrastructure deployment of the data center meets the fault tolerance levels and the fault domains specified for the data center. Techniques are described for obtaining configuration information related to various infrastructure resources deployed in a data center. A resource graph for the data center is generated based on the configuration information. The resource graph represents a logical representation of a set of vertices representing the physical and logical resources used to power a data center and a set of edges that connect the set of vertices. The resource graph is used to determine if a set of infrastructure nodes deployed in the data center meet the fault tolerance levels and fault domains specified for the data center. Results indicative of whether a deployed data center is fault tolerant are then transmitted to a user.

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

Abstract: For example, an apparatus may include an encoder configured to encode data into a plurality of codewords according to a parity function for a transmission modulated according to a Differential Modulation (DM) scheme, and/or a decoder to decode received codewords of the transmission.

Abstract: A method is provided for decompressing wide word data compressed in parallel. The method includes creating an instance of memory structure for a wide word in the wide word data, where the instance of memory structure is an inverse of a compression dictionary for the wide word; retrieving multiple compressed codes iteratively from a gap-free compressed output stream of the wide word data using the instance of memory structure, where each compressed code includes at least one character code and a reverse-pointer, and where at least one compressed code includes a multi-symbol string having a multiple character codes; forming an intermediate decompressed output stream by iteratively following the reverse-pointers for the multiple compressed codes, respectively; and forming decompressed output stream by reversing an order of the character codes in the multi-symbol string of the at least one compressed code.

Abstract: The present disclosure relates generally to the field of data encoding and decoding, and particularly to automorphism-based polar encoding and decoding apparatuses and methods, as well as computer program products embodying the method steps in the form of computer codes. More specifically, polar codes are designed such that their frozen bits support automorphisms described by a binary upper triangular matrix having a diagonal including at least one of zeros and units. Codewords generated using these polar codes may be subsequently subjected to automorphism-based polar decoding in an efficient manner and with a lower decoding latency compared to the conventional Successive Cancellation List decoding algorithms. Furthermore, the efficiency of the automorphism-based polar decoding may be increased even more if the automorphisms are based on matrix elements arranged above the diagonal in a vicinity of a bottom right corner of the binary upper triangular matrix.