Patents Examined by Shelly A Chase
  • Patent number: 11611356
    Abstract: A low density parity check (LDPC) channel encoding method is used in a wireless communications system. A communication device encodes an input bit sequence by using an LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The base matrix may be one of eight exemplary designs. The encoding method can be used in various communications systems including fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: March 21, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jie Jin, Wen Tong, Jun Wang, Aleksandr Aleksandrovich Petiushko, Ivan Leonidovich Mazurenko, Chaolong Zhang
  • Patent number: 11599412
    Abstract: Systems, methods, and computer-readable media are provided for utilizing distributed erasure encoding in a redundant array of independent disks (RAID) system. An example method can include generating a plurality of virtual redundant array of independent disk (vRAID) stripes, each of the plurality of vRAID stripes including a segment having a plurality of data, each of the plurality of data including metadata, the metadata including a checksum of a corresponding data of the plurality of data, distributing the segment of each of the plurality of vRAID stripes over a plurality of virtual nodes, mapping at least one of logical files, volumes, or objects to the plurality of data chunks and the at least one parity chunk of the plurality of vRAID stripes to avoid write-hole issues, and verifying data integrity of the corresponding data of the plurality of data using the checksum of the corresponding data.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 7, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Sandip Agarwala, Shravan Gaonkar
  • Patent number: 11595152
    Abstract: Embodiments of the present disclosure relate to a binary clustered forward error correction encoding scheme. Systems and methods are disclosed that define binary clustered encodings of the media packets from which forward error correction (FEC) packets are computed. The different encodings specify which media packets in a frame are used to compute each FEC packet (a frame includes M media packets). The different encodings may be defined based on the quantity of media packets in a frame, M?floor(2N), where each bit of the binary representation of N is associated with a different cluster pair encoding of the media packets. Each cluster pair includes a cluster for which the bit=0 and a cluster for which the bit=1. Computing FEC packets using at least two cluster pair encodings provides redundancy for each media packet, thereby improving media packet recovery rates.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: February 28, 2023
    Assignee: NVIDIA Corporation
    Inventors: Shridhar Majali, Harsh Chandresh Maniar, Reza Marandian Hagh
  • Patent number: 11593201
    Abstract: Apparatuses and methods for memory repair for a memory device are described. An example apparatus includes: a data input/output circuit that provides data via a plurality of data signal lines; memory cell arrays; an ECC/Parity redundancy array; and a redundancy circuit coupled to the plurality of data signal lines. The redundancy circuit includes an error correction block that generates error correction information based on the data and provides the error correction information to the ECC/Parity redundancy array. If during test it is determined that a failure is not repairable by standard redundancy including error correction code, the error correction parity array is not needed and can be redirected by a block repair circuit. The error correction circuit can now have its functionality changed to allow the error correction array to become a block repair.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: February 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Seth Eichmeyer, James Rehmeyer, Benjamin Johnson, Jason Johnson
  • Patent number: 11595059
    Abstract: A method for compressing pre-compressed data used in a reconfigurable processor, where the pre-compressed data includes a number of data blocks, obtains a current data block, calculates a current checking code of the current data block, and compares the current checking code with an immediately-previous checking code. A tag of the current data block is marked as a first tag if the current checking code and the immediately-previous checking code are different, and is marked as a second tag if the current checking code and the immediately-previous checking code are the same. Only data blocks whose tags are the first tags are saved. A related device for compressing data, and a method and a device for decompressing data are also provided.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: February 28, 2023
    Inventor: Jen-Hao Liao
  • Patent number: 11593190
    Abstract: Systems and methods are disclosed for detecting shingled overwrite errors. When a read error is encountered when reading from shingled recording tracks, a processor may determine whether the read error is an error caused by shingled overwriting. The processor may determine whether the read error is caused by shingled overwriting by determining read signal quality of one or more sectors preceding the read error, such as based on a bit error count or bit error ratio (BER), and comparing the read signal quality to a threshold value. The processor may determine that the read error is caused by shingled overwriting when the read signal quality value is lower than the threshold.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: February 28, 2023
    Assignee: Seagate Technology LLC
    Inventors: Xiong Liu, WeiQing Zhou, Quan Li, WenXiang Xie
  • Patent number: 11588590
    Abstract: Provided are systems and methods for adaptive payload extraction and retransmission in wireless data communications. An example method commences with transmitting a network packet to a receiver via a communication channel. The method further includes receiving a further network packet including a further payload. The method continues with determining, based on the payload and the further payload, an error vector. The method includes generating, based on the error vector, a plurality of indices. An index of the plurality of indices corresponds to a portion of a plurality of non-overlapping portions of the payload. The method further continues with selecting, based on the error vector, at least one index from the plurality of indices. The method includes sending, to the receiver via the communication channel, a further network packet. The further network packet includes the selected index and a portion of the payload corresponding to the selected index.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: February 21, 2023
    Assignee: Aira Technologies, Inc.
    Inventors: Anand Chandrasekher, RaviKiran Gopalan, Yihan Jiang, Arman Rahimzamani
  • Patent number: 11579964
    Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Sai Krishna Mylavarapu, Todd A. Marquart
  • Patent number: 11573855
    Abstract: Techniques are provided for remote object store error handling. A storage system may store data within one or more tiers of storage, such as a local storage tier (e.g., solid state storage and disks maintained by the storage system), a remote object store (e.g., storage provided by a third party storage provider), and/or other storage tiers. Because the remote object store may not provide the same data consistency and guarantees that the storage system provides for clients such as through the local storage tier, additional validation is provided by the storage system for the remote object store. For example, when data is put into an object of the remote object store, a verification get operation is performed to read and validate information within a header of the object. Other verifications and checks are performed such as using a locally stored metafile to detect corrupt or lost metadata and/or objects.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: February 7, 2023
    Assignee: NetApp, Inc.
    Inventors: Ananthan Subramanian, Ganga Bhavani Kondapalli, Cheryl Marie Thompson, Kevin Daniel Varghese, Anil Paul Thoppil, Qinghua Zheng
  • Patent number: 11575466
    Abstract: The invention discloses an error reconciliation method for a Learning With Errors (LWE) public key cryptography. The method includes an encoding algorithm and a decoding algorithm. The input of the encoding algorithm is a binary message vector u?{0,1}k with a length of k, the output is a q-ary vector z?Zqm with a length of m, where Zq={?q/2, . . . , q/2?1}; the input of the decoding algorithm is a q-ary vector w=z+e?Zqm containing errors with a length of m, and the output is a binary vector u?{0,1}k corresponding to z; the error reconciliation method for the LWE public key cryptography provided by the present invention combines a binary linear code with a Gray code to realize the error reconciliation scheme in LWE public key cryptography. The error reconciliation method can be used to solve the problem of error reconciliation in LWE public key cryptography. The scheme of the invention has good fault tolerance and can significantly improve the transmission rate of encrypted information.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: February 7, 2023
    Inventors: Xiaoyun Wang, Anyu Wang, Yue Sun
  • Patent number: 11569939
    Abstract: A system includes a first device and a second device coupled to a link. The first device is to transmit one or more request frames for synchronization of a data layer, each request frame including a quantity of bits and an error code. The second device is to receive a first set of bits corresponding to the quantity of bits in each request frame. The second device is to perform an error decode operation on the first set of bits using a first portion of the first set of bits and determine the first set of bits correspond to a frame boundary of the one more request frames responsive to a success of the error decode operation. The second device is to transmit an acknowledgement of the synchronization of the data layer based on determining the first set of bits corresponds to the frame boundary.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: January 31, 2023
    Assignee: NVIDIA Corporation
    Inventors: Adithya Hrudhayan Krishnamurthy, Ish Chadha
  • Patent number: 11563518
    Abstract: A method and a device of cyclic redundancy check are provided. The method includes determining a payload portion, the payload portion including at least one information field for carrying information bits; determining input bits for generating CRC bits, the input bits including information bits carried in a part or all of at least one information field; generating target CRC bits according to the input bits; generating control information including the payload portion and the target CRC bits.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: January 24, 2023
    Inventors: Xiaodong Shen, Xueming Pan, Zichao Ji, Peng Sun
  • Patent number: 11544141
    Abstract: Provided is a method for detecting stored data and device, a storage medium and an electronic device. The method includes: the first check information of first data stored in a memory in the current period is determined; the first check information is compared with second check information to obtain a check result, wherein the second check information is check information of second data stored in the memory in a period prior to the current period; and the correctness of storage of the second data is detected according to the check result.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: January 3, 2023
    Assignee: Suzhou Centec Communications Co., Ltd.
    Inventors: Zicang Zhao, Xianghong Gu, Lei Li, Zhichuan He, Fushan Jia
  • Patent number: 11537466
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller comprises an XOR module, an ECC module, a scrambler, an encoder, and comparison logic. The controller is configured to retrieve data from the memory device, decode the retrieved data, execute XOR protection logic on the decoded data, encode the decoded data, and compare the encoded data to the retrieved data stored in the memory device.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Michael Ionin, Alexander Bazarsky
  • Patent number: 11528092
    Abstract: Methods, systems, and devices for wireless communications employing multi-level coding with set partitioning on transmitting side and multi-level sequential decoding on the receiving side for latency minimization are described. In some systems, a transmitting device may transmit a code block group (CBG) to a receiving device including a first set of code blocks associated with a first decoding level and a second set of code blocks associated with a second decoding level. The receiving device may unsuccessfully decode one or more code blocks of the first set or the second set of code blocks and transmit a feedback message to the transmitting device. The transmitting device may determine that the data to be communicated via the CBG is latency-sensitive data and, as such, determine to retransmit both the first set and the second set of code blocks to the receiving device in response to receiving the feedback message.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: December 13, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Michael Levitsky, Assaf Touboul, Daniel Paz
  • Patent number: 11528126
    Abstract: This document includes techniques, apparatuses, and systems related to an interface for revision-limited memory, which can improve various computing aspects and performance. In aspects, confidentiality, integrity, and availability may be ensured while increasing the performance of revision-limited memory. In this example, the techniques also enable the digital computing device to interact with information related to the revision-limited memory.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: December 13, 2022
    Assignee: Google LLC
    Inventors: Eunchan Kim, Michael Stefano Fritz Schaffner, Timothy Jay Chen, Christopher Gori, Ziv Hershman, Miguel Angel Osorio
  • Patent number: 11520660
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding zone. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding zones. As the parity data is updated, the corresponding command is simultaneously written to the corresponding zone.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: December 6, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel L. Helmick, Peter Grayson, Sergey Anatolievich Gorobets
  • Patent number: 11520661
    Abstract: An apparatus includes a memory and one or more processors. The memory includes multiple memory blocks. The one or more processors are configured to read at least part of data stored in a group of one or more memory blocks, the data including multiple code words of an Error Correction Code (ECC) that is decodable using one or more processing elements selected from among multiple predefined processing elements. The one or more processor are further configured to decode one or more of the code words, and identify one or more of the predefined processing elements that actually participated in decoding the respective code words, and, based on cost-values associated with the identified processing elements, the cost-values are indicative of processing latencies respectively incurred by the identified processing elements, to make a decision of whether or not to refresh the one or more memory blocks in the group.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: December 6, 2022
    Assignee: APPLE INC.
    Inventors: Michael Jeffet, Itay Sagron, Nir Tishbi
  • Patent number: 11522635
    Abstract: A communication device includes a modulator, a first encoder and a second encoder, and generates a modulated signal with quadrature amplitude modulation. The modulator generates a modulated signal by mapping each symbol in a data frame that includes data, a first code, and a second code to a signal point among signal points of the quadrature amplitude modulation. The first encoder encodes the data by using a first coding scheme to generate the first code. The second encoder encodes, by using a second coding scheme, a bit string formed from a specified bit in a plurality of bits allocated to each symbol in the data frame to generate the second code. The modulator performs mapping such that each pair of adjacent signal points are different from each other in terms of a value of the specified bit in the plurality of bits.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: December 6, 2022
    Inventors: Junichi Sugiyama, Toshihiro Konno
  • Patent number: 11520656
    Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a plurality of memory devices of the set, wherein the failure causes data of the plurality of memory devices to be inaccessible; determining the capacity of the set of memory devices has changed to a reduced capacity; notifying a host system of the reduced capacity, wherein the notifying indicates a set of storage units comprising the data that is inaccessible; recovering the data of the set of storage units from the host system after the failure; and updating the set of memory devices to store the recovered data and to change the capacity to the reduced capacity.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: December 6, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert