Patents Examined by Shelly A Chase
  • Patent number: 12040030
    Abstract: The embodiments of the disclosure provide a method and device for generating a command sequence, a method and device for testing, and a storage medium. The method for generating a command sequence includes that: at least one executable CMD is determined based on a state machine module according to a current state; a command weight corresponding to the at least one executable CMD is acquired, and a random command is generated from the at least one executable CMD by taking the command weight as a constraint condition; and a next state is determined based on the state machine module according to the random command, and the next state is taken as the current state to continuously execute the step of determining at least one executable CMD based on the state machine module according to the current state, to generate a random command sequence.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: July 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yu Li, Changqing Wu
  • Patent number: 12040039
    Abstract: An apparatus that includes a memory cell array, an I/O terminal supplied with an original write data in a normal operation, a compression logic circuit configured to generate a compressed test data in a test operation based on a test read data read from the memory cell array, and a syndrome generator configured to generate a first syndrome based on the original write data in the normal operation and generate a second syndrome based on the compressed test data in the test operation.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: July 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kenya Adachi, Takuya Nakanishi
  • Patent number: 12034454
    Abstract: A method for verifying data integrity in a receiver in a wireless communication network is disclosed. The method includes receiving a data message, wherein the data message includes a group of data elements and a checksum, computing a complete syndrome vector based on partial syndrome vectors, wherein the partial syndrome vectors are computed, in parallel, by multiplying part of a parity-check matrix with corresponding part of the received data message, determining that all vector elements of the complete syndrome vector are zero, and verifying that the received data message is correct when all the vector elements of the complete syndrome vector are zero, and incorrect otherwise. Corresponding computer program product, apparatus, and receiver are also disclosed.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: July 9, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Niclas Wiberg, Martin Hessler
  • Patent number: 12034535
    Abstract: One coding method of a plurality of coding methods including at least a first coding method and a second coding method is selected, an information sequence is encoded by using the selected coding method, and an encoded sequence obtained by performing predetermined processing on the information sequence is modulated and transmitted. The first coding method is a coding method having a first coding rate, for generating a first encoded sequence by performing puncturing processing on a generated first codeword by using a first parity check matrix. The second coding method is a coding method having a second coding rate, for generating a second encoded sequence by performing puncturing processing on a generated second codeword by using a second parity check matrix that is different from the first parity check matrix, the second coding rate after the puncturing process being different from the first coding rate.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: July 9, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yutaka Murakami, Tomohiro Kimura, Mikihiro Ouchi
  • Patent number: 12034536
    Abstract: A method of communicating between nodes in a network where a node receives a sequence of symbols that will form a packet on a first communications channel and has a planned packet that it would send on a second communications channel. A destination is encoded into an arbitration portion of a header sequence of the packet, the header sequence comprising a sequence of symbols. The transmission on the second communications channel is as per the planned packet, for as long as the symbols of the planned packet match the symbols being received on the first channel. An arbitration decision is made when the symbols do not match, with the node either continuing to send the rest of the planned packet, or the rest of the packet being received on the first communications channel.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: July 9, 2024
    Inventors: Alexander Phillip Davies, Kevin Stephen Davis
  • Patent number: 12026052
    Abstract: A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: July 2, 2024
    Inventors: Kishore K. Muchherla, Niccolo' Righetti, Jeffrey S. McNeil, Jr., Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
  • Patent number: 12021548
    Abstract: A method of encoding input data. The method includes receiving a plurality of data bits of a bit stream. The method further includes forming words using the plurality of data bits to create a plurality of data packets including a first data packet. The method further includes encoding the words of the first data packet into coded words, partitioning the coded words into a plurality of blocks of M words each and integrating the coded words in each block in an interleaved order to generate a coded data packet for transmission through a communication channel.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: June 25, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventor: Aliazam Abbasfar
  • Patent number: 12021547
    Abstract: Methods, systems, and devices for associative computing for error correction are described. A device may receive first data representative of a first codeword of a size for error correction. The device may identify a set of content-addressable memory cells that stores data representative of a set of codewords each of which is the size of the first codeword. The device may identify second data representative of the first codeword in the set of content-addressable memory cells. Based on identifying the second data, the device may transmit an indication of a valid codeword that is mapped to the second data.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: June 25, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Ameen D. Akel, Helena Caminal, Sean S. Eilert
  • Patent number: 12015422
    Abstract: An apparatus has a communication bus, a first circuit, and a second circuit. The first circuit is operational to generate a package, calculate a check value of payload data in the package with a particular cyclic redundance check variant and an obfuscation type, store an encrypted check value in a footer of the package, store an encrypted obfuscation code in a header of the package, and transmit the package on the communication bus. The second circuit is operational to receive the package from the communication bus, decrypt the encrypted check value to determine the check value calculated by the first circuit, determine an obfuscation type from the encrypted obfuscation code, perform a payload verification of the payload data with the particular cyclic redundancy check variant with the obfuscation type applied and the check value, and signal that the payload data is valid in response to passage of the payload verification.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: June 18, 2024
    Assignee: GM Global Technology Operations LLC
    Inventors: Brian Farrell, Thomas M. Forest, Karl B. Leboeuf, Kenneth William Junk
  • Patent number: 12008244
    Abstract: The present description concerns a method comprising: the loading, from a non-volatile memory of a circuit to a computation circuit, of a first security parameter of the circuit and of a first error-correcting code stored in association with the first security parameter; the verification, by the computation circuit, of the first security parameter and of the first error-correcting code to determine whether one or a plurality of the bits of the security parameter are erroneous; and if it is determined that two bits of the security parameter are erroneous, the loading of a default value of the first parameter into a register.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: June 11, 2024
    Assignee: STMicroelectronics (Alps) SAS
    Inventor: Jawad Benhammadi
  • Patent number: 12009919
    Abstract: Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: June 11, 2024
    Assignee: KANDOU LABS SA
    Inventors: Filippo Borlenghi, David Stauffer
  • Patent number: 12009922
    Abstract: A method of processing wireless signals, including: receiving a wireless signal carrying a transmission frame having a physical layer header including a data rate index; decoding the physical layer header including the data rate index; filtering out the transmission frame for no further processing if a measured physical layer header energy is below an energy threshold corresponding to the decoded data rate index; decode a sample portion of data codewords of the transmission frame if the transmission frame is not filtered out, wherein the sample portion of data codewords is less than all of the data codewords of the transmission frame; and filtering out the transmission frame for no further processing if the decoding of the sample portion of data codewords fails, and otherwise decode a remainder of the transmission frame.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 11, 2024
    Assignee: Intel Corporation
    Inventors: Dor Chay, Itamar Borochov, Ofir Klein, Chen Kojokaro, Nadav Szanto
  • Patent number: 12002530
    Abstract: A memory transparent in-system built-in self-test may include performing in-system testing on subsets of memory cells over one or more test intervals of one or more test sessions. A test interval may include copying contents of a subset of memory cells to a register(s), writing test data (e.g., a segment of a pattern) to the subset of memory cells, reading back contents of the subset of memory cells, and restoring the content from the register(s) to the subset of memory cells. In-system testing may be performed on overlapping sets of memory cells. In-system testing may be performed on successive subsets of memory cells within a row (i.e., fast column addressing) and/or within a column (fast column addressing). In-system testing may be performed on sets of m blocks of memory cells during respective test intervals. The number of m blocks tested per interval may be configurable/selectable.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: June 4, 2024
    Assignee: Synopsys, Inc.
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Patent number: 12003323
    Abstract: Message faulting is a critical unsolved problem for 5G and 6G. Disclosed herein is a method for combining an AI-based analysis of the waveform data of each message element, plus the constraint of an associated error-detection code (such as a CRC or parity construct of the correct message) to localize and, in many cases, correct a limited number of faults per message, without a retransmission. For example, the waveform data may include a deviation of the amplitude or phase of a particular message element, relative to an average of the amplitudes or phases of the other message elements that have the same demodulation value. The outliers are thereby exposed as the most likely faulted message elements. In addition, using the error-detection code, the AI model can determine the most likely corrected message, thereby avoiding retransmission delays and power usage and other costs.
    Type: Grant
    Filed: November 5, 2023
    Date of Patent: June 4, 2024
    Inventors: David E. Newman, R. Kemp Massengill
  • Patent number: 11996938
    Abstract: Apparatus, methods, and computer program products for selecting an encoder for network coding are provided. An example method may include transmitting a report request for reporting one or more conditions to one or more network coding devices, the one or more conditions being associated with the one or more network coding devices. The example method may further include receiving a condition report reporting the one or more conditions from the one or more network coding devices based on the report request. The example method may further include transmitting a selection indication to a selected network coding device of the one or more network coding devices, the selection indication indicating a selection of the selected network coding device as an encoder for encoding a transport block (TB).
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: May 28, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Guangyi Liu, Gabi Sarkis, Shuanshuan Wu
  • Patent number: 11996157
    Abstract: A processing-in-memory (PIM) device includes an ECC logic circuit configured to generate first write data, first write parity, second write data, and second write parity from first write input data and second write input data when a write operation in an operation mode is performed, and generate first converted data and second converted data from first read data, first read parity, second read data, and second read parity when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the first converted data and the second converted data to generate MAC operation result data.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: May 28, 2024
    Assignee: SK hynix Inc.
    Inventor: Choung Ki Song
  • Patent number: 11996863
    Abstract: A low density parity check (LDPC) channel encoding method is used in a wireless communications system. A communication device encodes an input bit sequence by using an LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The base matrix may be one of eight exemplary designs. The encoding method can be used in various communications systems including fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: May 28, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jie Jin, Wen Tong, Jun Wang, Aleksandr Aleksandrovich Petiushko, Ivan Leonidovich Mazurenko, Chaolong Zhang
  • Patent number: 11991280
    Abstract: A method for execution by one or more modules of one or more processors of a storage network includes receiving a data object for storage, segmenting the data object into a plurality of data segments and determining a level of security and a level of performance for the plurality of data segments. The method continues by determining whether one or more data segments of the plurality of data segments is to be transformed using an all-or-nothing transformation and in response to a determination to transform one or more data segments of the plurality of data segments, transforming a data segment of the plurality of data segments to produce a transformed data segment. The method continues by dispersed error encoding the transformed data segment to produce a set of encoded data slices and transmitting the set of encoded data slices to a set of storage units of the storage network.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: May 21, 2024
    Assignee: Pure Storage, Inc.
    Inventors: Wesley B. Leggette, Jason K. Resch
  • Patent number: 11983431
    Abstract: A read-disturb-based read temperature time-based attenuation system includes a storage device that is coupled to a global read temperature identification subsystem. The storage device determines current read disturb information for data stored in a block in the storage device during a current time period, processes the current read disturb information and previous read disturb information that was determined during at least one previous time period that was prior to the current time period in order to generate a read temperature for the data stored in the block, generates a local logical storage element read temperature map that includes the read temperature, and provides the local logical storage element map to the global read temperature identification subsystem.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: May 14, 2024
    Assignee: Dell Products L.P.
    Inventors: Ali Aiouaz, Walter A. O'Brien, III, Leland W. Thompson, James Ulery
  • Patent number: 11979232
    Abstract: A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC) value is determined for the data frame by nullifying the checksum value in the data frame and considering the timestamp value. A final CRC value is determined by combining the CRC value for the data frame and a CRC correction value based on the checksum. The modified data frame is sent for processing using an emulator.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: May 7, 2024
    Assignee: Synopsys, Inc.
    Inventors: Jishnu De, Jaspreet Singh Gambhir