Patents Examined by Shelly A Chase
  • Patent number: 12015422
    Abstract: An apparatus has a communication bus, a first circuit, and a second circuit. The first circuit is operational to generate a package, calculate a check value of payload data in the package with a particular cyclic redundance check variant and an obfuscation type, store an encrypted check value in a footer of the package, store an encrypted obfuscation code in a header of the package, and transmit the package on the communication bus. The second circuit is operational to receive the package from the communication bus, decrypt the encrypted check value to determine the check value calculated by the first circuit, determine an obfuscation type from the encrypted obfuscation code, perform a payload verification of the payload data with the particular cyclic redundancy check variant with the obfuscation type applied and the check value, and signal that the payload data is valid in response to passage of the payload verification.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: June 18, 2024
    Assignee: GM Global Technology Operations LLC
    Inventors: Brian Farrell, Thomas M. Forest, Karl B. Leboeuf, Kenneth William Junk
  • Patent number: 12009922
    Abstract: A method of processing wireless signals, including: receiving a wireless signal carrying a transmission frame having a physical layer header including a data rate index; decoding the physical layer header including the data rate index; filtering out the transmission frame for no further processing if a measured physical layer header energy is below an energy threshold corresponding to the decoded data rate index; decode a sample portion of data codewords of the transmission frame if the transmission frame is not filtered out, wherein the sample portion of data codewords is less than all of the data codewords of the transmission frame; and filtering out the transmission frame for no further processing if the decoding of the sample portion of data codewords fails, and otherwise decode a remainder of the transmission frame.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 11, 2024
    Assignee: Intel Corporation
    Inventors: Dor Chay, Itamar Borochov, Ofir Klein, Chen Kojokaro, Nadav Szanto
  • Patent number: 12008244
    Abstract: The present description concerns a method comprising: the loading, from a non-volatile memory of a circuit to a computation circuit, of a first security parameter of the circuit and of a first error-correcting code stored in association with the first security parameter; the verification, by the computation circuit, of the first security parameter and of the first error-correcting code to determine whether one or a plurality of the bits of the security parameter are erroneous; and if it is determined that two bits of the security parameter are erroneous, the loading of a default value of the first parameter into a register.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: June 11, 2024
    Assignee: STMicroelectronics (Alps) SAS
    Inventor: Jawad Benhammadi
  • Patent number: 12009919
    Abstract: Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: June 11, 2024
    Assignee: KANDOU LABS SA
    Inventors: Filippo Borlenghi, David Stauffer
  • Patent number: 12002530
    Abstract: A memory transparent in-system built-in self-test may include performing in-system testing on subsets of memory cells over one or more test intervals of one or more test sessions. A test interval may include copying contents of a subset of memory cells to a register(s), writing test data (e.g., a segment of a pattern) to the subset of memory cells, reading back contents of the subset of memory cells, and restoring the content from the register(s) to the subset of memory cells. In-system testing may be performed on overlapping sets of memory cells. In-system testing may be performed on successive subsets of memory cells within a row (i.e., fast column addressing) and/or within a column (fast column addressing). In-system testing may be performed on sets of m blocks of memory cells during respective test intervals. The number of m blocks tested per interval may be configurable/selectable.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: June 4, 2024
    Assignee: Synopsys, Inc.
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Patent number: 12003323
    Abstract: Message faulting is a critical unsolved problem for 5G and 6G. Disclosed herein is a method for combining an AI-based analysis of the waveform data of each message element, plus the constraint of an associated error-detection code (such as a CRC or parity construct of the correct message) to localize and, in many cases, correct a limited number of faults per message, without a retransmission. For example, the waveform data may include a deviation of the amplitude or phase of a particular message element, relative to an average of the amplitudes or phases of the other message elements that have the same demodulation value. The outliers are thereby exposed as the most likely faulted message elements. In addition, using the error-detection code, the AI model can determine the most likely corrected message, thereby avoiding retransmission delays and power usage and other costs.
    Type: Grant
    Filed: November 5, 2023
    Date of Patent: June 4, 2024
    Inventors: David E. Newman, R. Kemp Massengill
  • Patent number: 11996938
    Abstract: Apparatus, methods, and computer program products for selecting an encoder for network coding are provided. An example method may include transmitting a report request for reporting one or more conditions to one or more network coding devices, the one or more conditions being associated with the one or more network coding devices. The example method may further include receiving a condition report reporting the one or more conditions from the one or more network coding devices based on the report request. The example method may further include transmitting a selection indication to a selected network coding device of the one or more network coding devices, the selection indication indicating a selection of the selected network coding device as an encoder for encoding a transport block (TB).
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: May 28, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Guangyi Liu, Gabi Sarkis, Shuanshuan Wu
  • Patent number: 11996157
    Abstract: A processing-in-memory (PIM) device includes an ECC logic circuit configured to generate first write data, first write parity, second write data, and second write parity from first write input data and second write input data when a write operation in an operation mode is performed, and generate first converted data and second converted data from first read data, first read parity, second read data, and second read parity when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the first converted data and the second converted data to generate MAC operation result data.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: May 28, 2024
    Assignee: SK hynix Inc.
    Inventor: Choung Ki Song
  • Patent number: 11996863
    Abstract: A low density parity check (LDPC) channel encoding method is used in a wireless communications system. A communication device encodes an input bit sequence by using an LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The base matrix may be one of eight exemplary designs. The encoding method can be used in various communications systems including fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: May 28, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jie Jin, Wen Tong, Jun Wang, Aleksandr Aleksandrovich Petiushko, Ivan Leonidovich Mazurenko, Chaolong Zhang
  • Patent number: 11991280
    Abstract: A method for execution by one or more modules of one or more processors of a storage network includes receiving a data object for storage, segmenting the data object into a plurality of data segments and determining a level of security and a level of performance for the plurality of data segments. The method continues by determining whether one or more data segments of the plurality of data segments is to be transformed using an all-or-nothing transformation and in response to a determination to transform one or more data segments of the plurality of data segments, transforming a data segment of the plurality of data segments to produce a transformed data segment. The method continues by dispersed error encoding the transformed data segment to produce a set of encoded data slices and transmitting the set of encoded data slices to a set of storage units of the storage network.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: May 21, 2024
    Assignee: Pure Storage, Inc.
    Inventors: Wesley B. Leggette, Jason K. Resch
  • Patent number: 11983431
    Abstract: A read-disturb-based read temperature time-based attenuation system includes a storage device that is coupled to a global read temperature identification subsystem. The storage device determines current read disturb information for data stored in a block in the storage device during a current time period, processes the current read disturb information and previous read disturb information that was determined during at least one previous time period that was prior to the current time period in order to generate a read temperature for the data stored in the block, generates a local logical storage element read temperature map that includes the read temperature, and provides the local logical storage element map to the global read temperature identification subsystem.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: May 14, 2024
    Assignee: Dell Products L.P.
    Inventors: Ali Aiouaz, Walter A. O'Brien, III, Leland W. Thompson, James Ulery
  • Patent number: 11979232
    Abstract: A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC) value is determined for the data frame by nullifying the checksum value in the data frame and considering the timestamp value. A final CRC value is determined by combining the CRC value for the data frame and a CRC correction value based on the checksum. The modified data frame is sent for processing using an emulator.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: May 7, 2024
    Assignee: Synopsys, Inc.
    Inventors: Jishnu De, Jaspreet Singh Gambhir
  • Patent number: 11971818
    Abstract: A memory view generator evaluates a Liberty file characterizing an NVM module to generate a memory view file for the NVM module. The memory view file includes a port alias identifying ports of the NVM module. The port alias for a set of ports of the NVM module characterizes a type of port in the set of ports. The memory view file includes a port action identifying ports of the NVM module that have a static value and a port access identifying ports of the NVM module that have a dynamic value. The memory view file has an address limit characterizing a number of words in the NVM module and an address partition characterizing address bits and data bits. The memory view file includes a read delay that defines a number of clock cycles needed to hold an address bus stable after a strobe port transitions to an inactive state.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: April 30, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven L. Gregor, Puneet Arora
  • Patent number: 11973514
    Abstract: A low-complexity selective mapping method using cyclic redundancy check is provided. In performing coding, a transmitter adds a check bit to information bits to be transmitted to obtain modulated data. Demodulation is performed on an M-order modulation symbol received by a receiver to obtain a decoding result of a coding polynomial of the modulation symbol and bit information received by the receiver. A modulo-2 division result of the decoding result of the coding polynomial and a generation polynomial is calculated. In a case that a remainder of the modulo-2 division result is equal to zero, if the modulated data corresponding to the same index value of the receiver and the transmitter are identical, a current iteration is stopped, and a current value is outputted as a phase rotation sequence index recovery value. Finally, the receiver obtains a decoded signal.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: April 30, 2024
    Assignee: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Guojun Li, Junbing Li, Congji Yin, Changrong Ye
  • Patent number: 11966277
    Abstract: A storage error identification/reduction system includes a storage error identification/reduction subsystem coupled to a storage subsystem including a block. The storage error identification/reduction subsystem receives first data, and writes the first data to first storage locations in the block while writing storage error identification data to second storage location(s) in the block that each are located adjacent at least one of the first storage locations, with the storage error identification data including predetermined values that are written to predetermined locations included in the second storage location(s) in the block. The storage error identification/reduction subsystem then reads the storage error identification data from the second storage location(s) and, based on the predetermined values and predetermined locations of the storage error identification data, identifies errors resulting from the reading of the storage error identification data.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: April 23, 2024
    Assignee: Dell Products L.P.
    Inventors: Leland W. Thompson, Ali Aiouaz
  • Patent number: 11967342
    Abstract: Mechanisms are provided to receive encoded header information stored on a tape of a tape drive, wherein the encoded header information has been generated by: generating, for a plurality of tracks of the tape of the tape drive, a header information in a plurality of symbols, wherein the plurality of symbols is comprised of a first set of symbols and a second set of symbols, wherein the first set of symbols include identical information across all tracks of the plurality of tracks, and wherein the second set of symbols are configurable to include different information across all tracks of the plurality of tracks; and modifying, for writing to the tape of the tape drive, the first set of symbols of the plurality of tracks to include parity information corresponding to information included in the second set of symbols of the plurality of tracks. The received encoded header information is decoded.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: April 23, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin Dale Butt, Roy Cideciyan, Simeon Furrer, Masayuki Iwanaga, Keisuke Tanaka
  • Patent number: 11962410
    Abstract: A user station for a serial bus system. The user station includes a communication control device for controlling a communication of the user station with at least one other user station, and a transceiver device to serially transmit a transmission signal generated by the communication control device onto a bus and to serially receive signals from the bus. The communication control device generates the transmission signal according to a frame, and inserts a header check sum into the frame, only bits of a frame header that is situated in front of a data field provided for useful data in the frame being included in the computation. For computing the header check sum, the communication control device uses a predetermined starting value and a predetermined check sum polynomial.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: April 16, 2024
    Assignee: ROBERT BOSCH GMBH
    Inventors: Christian Senger, Arthur Mutter, Christian Horst, Florian Hartwich
  • Patent number: 11956081
    Abstract: Disclosed are two methods, the first method comprising receiving a plurality of data packets, producing a coded data packet by coding together at least two data packets, wherein at least one of the at least two data packets is comprised in the received plurality of data packets or in a coding buffer, transmitting the at least two data packets to a first subset of legs, transmitting the coded data packets to a second subset of legs, and determining if the at least two data packets are to be duplicated based on, at least partly, one or more of the following: a notification, a condition, or a first indication.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: April 9, 2024
    Assignee: Nokia Technologies Oy
    Inventors: Stefano Paris, Qiyang Zhao, Daniela Laselva, Kalle Petteri Kela
  • Patent number: 11948652
    Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: April 2, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Ashish Darbari, Iain Singleton
  • Patent number: 11949434
    Abstract: Methods, systems, and devices for wireless communications are described. An encoding device (e.g., a user equipment (UE) or a base station) may divide one or more data units (e.g., packet data convergence protocol (PDCP) protocol data units (PDU)) into a set of data blocks. The encoding device may encode the set of data blocks using a fountain code and may generate a set of data units (e.g., radio link control (RLC) PDUs) based on encoding the set of data blocks using the fountain code. The UE may allocate a first subset of the set of data units to a first carrier and a second subset of the set of data units to a second carrier and may transmit the first subset over the first carrier and the second subset over the second carrier.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 2, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Changlong Xu, Tao Luo, Hao Xu