Patents Examined by Shelly A Chase
  • Patent number: 11144204
    Abstract: A method for execution by a dispersed storage and task (DST) client module includes issuing a read threshold number of read slice requests are issued to storage units of the set of storage units. One or more encoded slices of a selected read threshold number of encoded slices are received. When a next encoded data slice of a decode threshold number of encoded data slices is received within a response timeframe, outputting of the next encoded data slice is initiated. When the next encoded data slice is not received within the response timeframe, receiving of another decode threshold number of encoded slices of the set of encoded slices is facilitated. The other decode threshold number of encoded slices are decoded to produce recovered encoded data slices, where the recovered encoded data slices includes at least a recovered next encoded data. Outputting of the recovered next encoded data slice is initiated.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: October 12, 2021
    Assignee: PURE STORAGE, INC.
    Inventors: Bruno H. Cabral, Wesley B. Leggette
  • Patent number: 11139836
    Abstract: In a wireless communication system, a transmission device generates (K+J) bits by adding J cyclic redundancy check (CRC) bits to K information bits, and interleaves the (K+J) bits according to a seed value-based interleaving pattern. The transmission device encodes the bits interleaved according to the interleaving pattern, using a polar code. The seed value permutates the CRC bits, and a value previously determined according to K is used as the seed value.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: October 5, 2021
    Assignees: LG Electronics Inc., Ajou University Industry-Academic Cooperation Foundation
    Inventors: Kwangseok Noh, Bonghoe Kim, Song Nam Hong
  • Patent number: 11121817
    Abstract: Provided is a transmission method executed by a transmitting apparatus to transmit a content to a plurality of terminals. The content having transmission count information indicating a number of times the content is to be transmitted by the transmitting apparatus. The transmission method including a first transmission step of generating and transmitting a first transmission signal which transfers at least a first portion of a plurality of data packets including a plurality of content packets, storing data of the content therein, and a plurality of parity packets, generated from the content packets, and a second transmission step of, when the transmission count information of the content indicates a plurality of times, generating a second transmission signal including at least a second portion of the plurality of data packets, and transmitting the second transmission signal during a period which differs from a period during which the first transmission signal is transmitted.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: September 14, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventor: Yutaka Murakami
  • Patent number: 11119987
    Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for communicating and sharing blockchain data. One of the methods includes determining historic state data associated with one or more blocks created prior to a current block on a blockchain; performing error correction coding of the historic state data to generate encoded historic state data; dividing, based on one or more predetermined rules, the encoded historic state data into a plurality of data sets; selecting one or more data sets from the plurality of data sets based on the one or more predetermined rules; hashing the one or more data sets to generate one or more hash values corresponding to the one or more data sets; storing the one or more hash values; and deleting, by the blockchain node, the one or more data sets.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: September 14, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventor: Haizhen Zhuo
  • Patent number: 11106533
    Abstract: A memory system includes a host error correction code (ECC) encoder and a memory module. The host ECC encoder performs a host ECC encoding operation of write data to output host ECC encoded data, and the memory module includes a memory medium receiving the host ECC encoded data and a module controller controlling the memory medium. The module controller includes a parity remover and a module ECC decoder. The parity remover removes parity data from the host ECC encoded data to generate parity-removed data and performs a first write operation for writing the parity-removed data into the memory medium. The module ECC decoder performs a module ECC decoding operation of the host ECC encoded data to generate module ECC decoded data and performs a second write operation for writing the module ECC decoded data into the memory medium.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: August 31, 2021
    Assignee: SK hynix Inc.
    Inventor: Du Hyun Kim
  • Patent number: 11108506
    Abstract: Various embodiments disclosed herein provide for a retransmission system that uses a hybrid system to signal to a receiver the retransmission of codeblock groups to reduce network overhead and bandwidth. The amount of bandwidth needed to signal to a receiver which codeblock groups are being retransmitted is directly proportional to the number of codeblock groups. Therefore, during retransmission, if the number of a codeblock groups is below a predetermined threshold, then explicit signaling can be performed, where the transmitter sends a bit map identifying the codeblock groups being retransmitted. If the number of codeblock groups is above the threshold however, can use a codeblock group confirmation bit in the control information sent to the receiver, where the values of the bit can inform the receiver how the retransmission will be performed.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: August 31, 2021
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: SaiRamesh Nammi, Arunabha Ghosh
  • Patent number: 11101923
    Abstract: Circuitry and methods for receiving data that may be compliant with a specific protocol is discussed. The described systems may be employed to implement a physical media access (PMA) sublayer and/or physical coding sublayer (PCS) for high-speed Ethernet protocols. Embodiments described herein may have reduced circuitry footprint that may be achieved by the use of a single recovered clock to drive the operations of PCS circuitry. Efficient use of components may also be achieved by the use of smaller-sized words for processing by the PCS circuitry. The circuitry may process the smaller-sized words by implementing pipelined circuitry. Implementations that employ programmable circuitry, hardened circuitry, or hybrid implementations are also discussed.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventor: Faisal Khan
  • Patent number: 11093145
    Abstract: Protecting in-memory configuration state registers. A request to access an in-memory configuration state register, such as a read or write request, is obtained. The in-memory configuration state register is mapped to memory. Error correction code of the memory is used to protect the access to the in-memory configuration state register.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 11095310
    Abstract: An error correction apparatus may include: an input component configured to receive data; an error information generation component having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the received data and the positions of the errors, based on the first error detection ability, and generate the error information based on the second error detection ability, when the error information is not generated on the basis of the first error detection ability; an error correction component configured to correct the errors of the received data based on the generated error information; and an output component configured to output the corrected data.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Kim, Won Gyu Shin
  • Patent number: 11086713
    Abstract: A method of optimized end-to-end integrity comprises receiving a request to write application data stored in a first kernel buffer to a storage device. The method further comprises determining, by a processing device, that a first cyclic redundancy check (CRC) of the application data failed. The method further comprises copying the application data to a second kernel buffer. The method further comprises performing, by the processing device, a second CRC on the application data stored in the second kernel buffer.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: August 10, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Constantine P. Sapuntzakis, Krishna Kant
  • Patent number: 11082060
    Abstract: A method for encoding a quasi-cyclic low-density parity-check (LDPC) code according to an embodiment of the present invention comprises: a step of generating a multi-edge LDPC code matrix which comprises a high rate code matrix and a single parity check code matrix; and a step of encoding a signal using the multi-edge LDPC code matrix, wherein the single parity check code matrix may be configured by connecting a first matrix which is configured as a quasi row-orthogonal structure matrix and a second matrix which is configured as a pure row-orthogonal structure.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: August 3, 2021
    Assignee: LG Electronics Inc.
    Inventors: Jongwoong Shin, Bonghoe Kim, Jinwoo Kim, Ilmu Byun
  • Patent number: 11082915
    Abstract: Systems and methods for optimizing data communication in a network of moving things. As non-limiting examples, various aspects of this disclosure provide systems and methods for communicating delay tolerant information in a network of moving things, for example comprising any of a variety of types of vehicles (e.g., autonomous vehicles, vehicles controlled by local operators, vehicles controlled by remote operators, etc.).
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 3, 2021
    Assignee: Veniam, Inc.
    Inventors: Tiago Condeixa, Joao Azevedo, Carlos Ameixieira, Ricardo Matos, Roy Russell, Joao Barros
  • Patent number: 11074124
    Abstract: One embodiment facilitates data access in a storage device. During operation, the system obtains, by the storage device, a file from an original physical media separate from the storage device, wherein the file comprises compressed data which has been previously encoded based on an error correction code (ECC). The system stores, on a physical media of the storage device, the obtained file as a read-only replica. In response to receiving a request to read the file, the system decodes, by the storage device based on the ECC, the replica to obtain ECC-decoded data, wherein the ECC-decoded data is subsequently decompressed by a computing device associated with the storage device and returned as the requested file.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: July 27, 2021
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11073552
    Abstract: Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo Li
  • Patent number: 11070312
    Abstract: A transmitter generates determiners from data vectors representing payload information, each determiner representing parity information dependent on the payload information. The transmitter encodes the determiners to generate a nub vector representing compressed parity information dependent on the parity information, wherein the encoding is mathematically equivalent to calculating three or more forward error correction (FEC) codewords from the determiners and then calculating the nub vector from the codewords, at least one of the codewords being calculated from at least one recursion of a mathematical operation, and at least one of the codewords comprising more than 6 terms. The transmitter transmits signals representing the data vectors and the nub vector to a receiver, where recovery of the data vectors at the receiver involves sequential decoding of the FEC codewords, wherein at least one codeword decoded earlier in the decoding enhances an estimate of at least one codeword decoded later in the decoding.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 20, 2021
    Assignee: CIENA CORPORATION
    Inventors: Shahab Oveis Gharan, Mohammad Ehsan Seifi, Kim B. Roberts
  • Patent number: 11061763
    Abstract: According to an aspect of inventive concepts, there is provided a memory controller configured to control a memory device including a plurality of memory pages, the memory controller including an error correction code (ECC) region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions, and an ECC engine configured to perform an ECC operation on data included in the ECC enable regions.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: July 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-hun Kim, Yong-sang Yu, Man-hwee Jo, Min-young Joe, Ji-woong Kim, Nak-hee Seong
  • Patent number: 11055176
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding zone. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding zones. As the parity data is updated, the corresponding command is simultaneously written to the corresponding zone.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: July 6, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel L. Helmick, Peter Grayson, Sergey Anatolievich Gorobets
  • Patent number: 11057049
    Abstract: Provided is an encoder, a decoder, a computer-readable medium and methods of forward error correction channel encoding/decoding within a HARQ scheme, based on a generalized quasi-cyclic low-density parity-check code comprising a Cordaro-Wagner component code.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: July 6, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Vasily Stanislavovich Usatyuk, Nikita Andreevich Polianskii, Ilya Viktorovich Vorobyev, Vladimir Anatolyevich Gaev, German Viktorovich Svistunov, Mikhail Sergeevich Kamenev, Yulia Borisovna Kameneva
  • Patent number: 11057054
    Abstract: Embodiments of this application provide a method for transmitting encoded information. A communication device obtains K bits of information, and generates a to-be-encoded sequence u1N, wherein N is a length of the sequence. The device encodes the sequence u1N in an encoding process, to obtain an output sequence, and transmits the output sequence. In the sequence u1N, each of the N bits corresponds to a subchannel, and each subchannel has a reliability. The K information bits, a quantity J of first-type auxiliary bits, and a quantity J? of second-type auxiliary bits are placed in K?=K+J+J? bit positions of the sequence u1N according to reliabilities of the subchannels. Since the positions of the information bits and the auxiliary bits are pre-determined and not affected by subsequent encoding and rate-matching, overheads of real-time reliability calculation are effectively reduced, time is saved, and delay is reduced.
    Type: Grant
    Filed: February 23, 2020
    Date of Patent: July 6, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Huazi Zhang, Rong Li, Yue Zhou, Hejia Luo, Gongzheng Zhang, Yunfei Qiao
  • Patent number: 11057152
    Abstract: Embodiments of this application provides a communication method in a wireless communication network. A communication device obtains an information bit sequence and obtain a first sequence, wherein the first sequence comprises sequence numbers of N channels ordered in ascending order of channel reliability, wherein N is 1024 and wherein a channel whose sequence number is 0, a channel whose sequence number is 1, and a channel whose sequence number is 2 are ordered in ascending order of channel reliability; then polar encode the information bits based on the first sequence to obtain an encoded bit sequence and output the encoded bit sequence.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: July 6, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Ying Chen, Gongzheng Zhang, Lingchen Huang, Rong Li, Huazi Zhang, Hejia Luo