Abstract: Apparatuses, systems, and techniques to select fifth-generation (5G) new radio data. In at least one embodiment, a processor includes one or more circuits to select 5G new radio signal information in parallel.

Abstract: This disclosure relates to encoding and decoding methods and apparatuses. The method may include encoding an ith signal frame, to obtain an encoded result of the ith signal frame. The method may further include performing forward error correction encoding on first n signal frames, to obtain forward error correction encoded results corresponding to the first n signal frames. The first n signal frames may be signal frames located before the ith signal frame. The method may further include synthesizing the encoded result of the ith signal frame and the forward error correction encoded results corresponding to the first n signal frames, to obtain an ith encoded frame corresponding to the ith signal frame. The ith encoded frame may comprise a flag bit, the flag bit may be for indicating a number n, and n may be a positive integer greater than or equal to 2.

Abstract: A three-dimensional stacked memory device includes a buffer die having a plurality of core die memories stacked thereon. The buffer die is configured as a buffer to occupy a first space in the buffer die. The first memory module, disposed in a second space unoccupied by the buffer, is configured to operate as a cache of the core die memories. The controller is configured to detect a fault in a memory area corresponding to a cache line in the core die memories based on a result of a comparison between data stored in the cache line and data stored in the memory area corresponding to the cache line in the core die memories. The second memory module, disposed in a third space unoccupied by the buffer and the first memory module, is configured to replace the memory area when the fault is detected in the memory area.

Abstract: A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.

Abstract: Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The mechanisms address ANN system level safety in situ, as a system level strategy tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts that function to detect and promptly flag and report an error with some mechanisms capable of correction as well.

Abstract: Certain aspects of the present disclosure provide techniques for wireless communication. The techniques include a method wireless communication by a user equipment including receiving a configuration message, wherein the configuration message in part configures the UE to communicate coordinated transmissions with a plurality of transmission reception points using a coordinated transmission mode. The method further includes, receiving one or more physical downlink shared channel transmissions from a plurality of transmission reception points in accordance with the coordinated transmission mode. The method further includes, selecting a HARQ-ACK feedback mode based in part on the coordinated transmission mode. The method further includes, transmitting HARQ-ACK feedback to at least one of the plurality of transmission reception points using the selected HARQ-ACK feedback mode.

Abstract: Artificial Intelligence (AI) is well-suited to mitigate message faults by combining analog and digital information in 5G and 6G communications. The analog information includes everything measureable about the waveform signal as-received, and the digital information includes the error-detection code accompanying the message. For example, the AI model can localize the most likely faulted message elements according to amplitude fluctuations or phase deviations or other signaling irregularity, and can then use the error-detection code to calculate the corrected values of the faulted message elements. The AI model can also check the error-detection code itself for faults and consistency, as well as a demodulation reference that was used to demodulate the message, thereby avoiding a defective mitigation if either of those is faulted. The AI model can provide output including the most likely corrected version of the message, as well as a comparison with other possible versions, if any.

Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

Abstract: The present disclosure provides a method for controlling a data storage device. The method includes: storing a first data in a first area of a memory of the data storage device; storing a second data in a second area of the memory, wherein the second data is associated with the first; reading the first data and the second data via a first communication interface; and in response to the read first data and second data, generating a first output signal.

Abstract: This application relates to communicating information between communication devices. A channel coding method is disclosed. A communication device obtains an input sequence of K bits. The communication device encodes the input sequence using a low density parity check (LDPC) matrix H, to obtain an encoded sequence. The LDPC matrix H is determined according to a base matrix and a lifting factor Z. The base matrix includes m rows and n columns, m is greater than or equal to 5, and n is greater than or equal to 27. The lifting factor Z satisfies a relationship of 22*Z?K. According to the encoding method provided in the embodiments, information bit sequences of a plurality of lengths can be encoded for transmission between the communication devices.

Abstract: A data processing system comprises a memory, a processing unit, a MMU operable to process memory transactions for the processing unit; and an error-detecting circuit located between the MMU and the memory. The MMU is configured to determine from respective memory address mappings corresponding memory addresses to which memory transaction applies. The determined memory addresses comprise a first part representing a memory location and a second part representing an error-detecting code generated using the first part of the memory address. The error-detecting circuit can then check using the error-detecting code for the memory address whether the memory address received by the error-detecting circuit is valid.

Abstract: An operation method of a terminal may include: receiving, from a base station, an addition value KN, information on linear combination coefficient matrices for respective numbers of transport blocks, and configuration information on each linear combination coefficient matrix; dividing a source block into M transport blocks; selecting one linear combination coefficient matrix among the linear combination coefficient matrices based on M; generating (M+KN) network coding blocks by performing network coding on the M transport blocks with the selected one linear combination coefficient matrix; and transmitting, to the base station, messages each including one network coding block among the network coding blocks, a control index of the one linear combination coefficient matrix, and a preamble.

Abstract: A data transmission method, includes: receiving N data packets sent by a communication opposite-end device, wherein each data packet includes a piece of target data, and N is a positive integer greater than 1; according to a receiving sequence of the N data packets from a first data packet to an Nth data packet, sequentially determining whether a transmission error occurs in each data packet; if it is determined that a data packet is transmitted incorrectly, storing, in a first queue, a piece of first indication information which indicates the data packet is transmitted incorrectly; and after it is determined that the reception of the N data packets ends, generating a first retransmission instruction, and sending the first retransmission instruction to the communication opposite-end device, wherein the first retransmission instruction includes information in the first queue.

Abstract: Certain aspects of the present disclosure generally relate to techniques for encoding and decoding bits of information using cyclic redundancy check (CRC) concatenated polar encoding and decoding. A method generally includes obtaining the bits of information to be transmitted. The method includes performing CRC outer encoding of the bits of information using an even-weighted generator polynomial to produce CRC encoded bits. The method includes performing polar inner encoding of the CRC encoded bits to generate a codeword. The method includes discarding a first code bit at a beginning of the codeword. The shortened codeword is transmitted over a wireless medium. In another method, bit-level scrambling is performed on the CRC encoded bits before the polar encoding to. In another method, only odd-weighted generator polynomials are selected.

Abstract: Wireless messages in 5G and 6G include error-detection codes appended or embedded in the message, such as Polar, LDPC, Turbo, and CRC codes. Analog fault tests based on the waveform signal of each message element can enhance the fault localization and mitigation, in many cases. Unexpected amplitude or phase variations, ambiguous modulation values, and polarization irregularities in or between message elements can localize the likely faulted message element(s). Turbo, Polar, and certain LDPC versions employ soft-decision decoding natively, and therefore can include the waveform results as extrinsic information. Other codes, such as basic parity, CRC, and basic LDPC, use hard-decision processes, but when combined with waveform diagnostics, can localize and mitigate faults. In life-threatening situations, rapid mitigation of a faulted message may save lives.

Abstract: An IC is provided and includes a memory array, an address register holding at least one address of a securely stored file and configured to output three or more addresses of the securely stored filed and computation-in-memory (CIM) logic coupled with the memory array. The CIM logic is configured to perform a majority function on three or more bits of the securely stored file, wherein the three or more bits are redundantly stored in three or more different locations in the memory array and wherein the three locations are associated with the three or more addresses in the memory array.

Abstract: A memory controller coupled to a memory device and configured to control access operations of the memory device includes a host interface and a microprocessor. The microprocessor is coupled to the host interface and configured to set a value of a predetermined parameter to a specific value after the memory controller powers up and start to perform a link flow to try to establish a transmission link via the host interface. The predetermined parameter is one of a plurality of capability parameters of the host interface and the predetermined parameter is related to reception of the host interface. After the link flow is completed, the microprocessor is further configured to identify an object device with which the host interface establishes the transmission link according to the specific value and at least one of a plurality of attribute parameters associated with the transmission link.

Abstract: One coding method of a plurality of coding methods including at least a first coding method and a second coding method is selected, an information sequence is encoded by using the selected coding method, and an encoded sequence obtained by performing predetermined processing on the information sequence is modulated and transmitted. The first coding method is a coding method having a first coding rate, for generating a first encoded sequence by performing puncturing processing on a generated first codeword by using a first parity check matrix. The second coding method is a coding method having a second coding rate, for generating a second encoded sequence by performing puncturing processing on a generated second codeword by using a second parity check matrix that is different from the first parity check matrix, the second coding rate after the puncturing process being different from the first coding rate.

Abstract: Provided is a device and method for encoding and decoding to implement maximum transition avoidance coding with minimum overhead. An exemplary device performs encoding and/or decoding, by using sub-block lookup tables representing correlations between some bit values in a data burst and symbols, a combining lookup table selectively interconnecting the sub-block lookup tables based on remaining bit values of the data burst, and a codeword decoding lookup table designating the sub-block lookup tables corresponding to the symbols of each of received codewords.

Abstract: A method of transmitting data determines a measure of consecutive packet loss in a network; a ratio of a number of data packets and a number of error correction packets is selected in dependence on the measure. A stream of data packets is generated, and a stream of error correction packets is generated in dependence on the stream of data packets such that the proportion of error correction packets generated to the data packets generated is commensurate with the selected ratio.