Abstract: A data transmission circuit, a data transmission method, and a storage apparatus are provided. The data transmission circuit includes a check circuit, a comparison circuit, and a data conversion circuit. The check circuit is configured to generate check code data according to first data on a first data line, and combine the first data and the check code data into second data. The comparison circuit is configured to receive the second data and third data on the second data line, and compare the second data with the third data to output a comparison result indicating whether number of different bits between the second data and the third data exceeds a preset threshold. The data conversion circuit is configured to invert the second data and transmit the inverted second data to the second data line when the comparison result is indicative of exceeding the preset threshold.

Abstract: A technique for performing lattice surgery without using twists is disclosed. Also, an error correcting code and decoder is provided that allows for error decoding of Pauli measurements performed in association with a lattice surgery operation. This allows for overall run-times of lattice surgery to be reduced. For example, some level of errors are tolerable, because they can be corrected, thus fewer measurement rounds (dm) may be performed for a given round of Pauli measurements. Additionally, a temporal encoding of lattice surgery technique is provided, which may additionally or alternatively be used to shorten run times. Also, a quantum computer layout is provided, wherein the layout includes a core computing region and a cache region. Also, protocols for swapping logical qubits between the core and cache are provided.

Abstract: A master is provided which is connected to at least one slave via an interface, wherein the at least one master is designed, in a transmission mode to transfer a valid combination of output data and associated error detection data via the interface, and wherein the at least one master is furthermore designed, in a non-transmission mode, to output an invalid combination of output data and associated error detection data in case of an erroneous output request.

Abstract: This document includes techniques, apparatuses, and systems related to an interface for revision-limited memory, which can improve various computing aspects and performance. In aspects, confidentiality, integrity, and availability may be ensured while increasing the performance of revision-limited memory. In this example, the techniques also enable the digital computing device to interact with information related to the revision-limited memory.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

Abstract: According to one embodiment, an electronic communication device includes a controller that changes an upper limit value capable of correcting an error of bit data in which an error occurs in packet data transferred by serial communication.

Abstract: Preventing quantum errors using a Quantum Error Correction Algorithm Trainer (QECAT) table is disclosed herein. In one example, a processor device of a computing device is to identify a subset of a plurality of QECAT table entries of a QECAT table, wherein each QECAT table entry of the subset corresponds to an occurrence of a quantum error. The processor device is further to obtain metadata from each QECAT table entry of the subset. The processor device identifies, based on the metadata from each QECAT table entry of the subset, a common characteristic of each occurrence of the quantum error. The processor device then determines, based on the common characteristic, a preventative action to prevent a future occurrence of the quantum error.

Abstract: A process is provided to trim PCRAM cells to have consistent programming curves. Initial programming curves of PCRAM cells are measured. A target programming curve is set up for the PCRAM cells. Each PCRAM cell is then modulated individually to meet the target programming curve.

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

Abstract: Embodiments of this application disclose a signal transcoding method performed by an electronic device. The method includes: acquiring an encoding result of an ith signal frame and encoding results respectively corresponding to first n signal frames of the ith signal frame; generating forward error correction (FEC) encoding results respectively corresponding to the first n signal frames according to the encoding results respectively corresponding to the first n signal frames; and synthesizing the encoding result corresponding to the ith signal frame and the FEC encoding results respectively corresponding to the first n signal frames to generate an encoded frame corresponding to the ith signal frame, the encoded frame comprising a flag bit for indicating a value of n. According to this application, a quantity of FEC encoded frames included in an encoded frame can be flexibly adjusted to improve the reliability of data transmission in a poor network state.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data, determine an entropy value of the received KV pair data, select an error correction code (ECC) code rate based on the determined entropy value, and program the KV pair data to a codeword (CW). The KV pair data includes a key and a value. The programming includes encoding the KV pair data using the selected ECC code rate. The controller is further configured to aggregate a portion of another KV pair data and the KV pair data and program the aggregated KV pair data to the CW using a selected ECC code rate.

Abstract: A polar code may be initially divided into multiple polar component codes where the features of these component codes, such as the number of component codes and the size of the component codes, are determined based on parameters such as the number of available timing units within a transmission interval, interleaving depth, and decoder capability. For each selected component code, the order of code bit generation and their indexes may be determined. The determined indexes may be assigned into different, unique groups according to the order of code bit generation. An interleaving operation may be configured and then executed according to the determined index grouping. In the transmission phase, the code bits may be transmitted based on the identified order of the bit generation in the component polar codes, such as the determined index grouping.

Abstract: Message faults are expected to be an increasing problem in 5G and 6G, due to signal fading at high frequencies, heavy background interference, and high user densities. Retransmissions are expensive in time, power, and the additional background they generate. Prior art includes “soft-combining” among multiple copies, an especially ineffective fault mitigation procedure when SNR is low. Nevertheless, the waveform signals of even badly faulted message elements are rich with information about the correct value. Therefore, procedures are disclosed herein for determining which message elements of a corrupted message, or its associated error-detection code, are faulted, by measuring characteristic parameters of the signal waveform of each message element, and correlating those parameters with the associated error-detection code. In many cases, the corrupted message may be corrected without a retransmission, according to some embodiments.

Abstract: As transmitters proliferate, and the transmission frequency steadily increases in 5G and especially 6G, the rate of message faults will likely increase unacceptably. Disclosed are methods for wireless receivers to detect, localize, and correct message faults using a combination of signal quality, modulation quality, and an embedded error-detection code. The error-detection code can indicate when the message is corrupted, while the signal quality and modulation quality can indicate which message elements are faulted, or can provide a likelihood that each message element is faulted. The message can then be corrected, using a combination of the error-correction code, the signal quality, and the modulation quality. In embodiments, the correction can be calculated directly from the error-detection code, or determined by altering each likely faulted message element to each of the other modulation states and testing with the error-detection code.

Abstract: A method of extremely high coding rates for next-generation wireless local area network (WLAN) systems involves coding an input data at a first coding rate using codes designed for coding up to a second coding rate lower than the first coding rate to provide a coded data. The method also involves wirelessly transmitting the coded data.

Abstract: The present disclosure provides an encoding and decoding device implementing an improved forward error correction (FEC) coding/decoding method. In particular, the encoding device is configured to encode a stream of data symbols using a spatially coupled code (e.g. staircase codes, braided block codes or continuously interleaved block codes), wherein at least one generalized error location (GEL) code is used as a component code of the spatially coupled code. Accordingly, the decoding device is configured to decode a sequence of encoded symbol blocks using a spatially coupled code, wherein at least one GEL code is used as a component code of the spatially coupled code. Thereby, a suitable spatially coupled FEC code that allows for very low-latency, high-throughput, high-rate applications with a low-complexity decoding procedure, and allows for mitigation of the error-floor, is designed.

Abstract: Embodiments of this application provide a method for coding in a wireless communication network. A communication device interleave a first bit sequence to obtain a first interleaved sequence having sequence number starting with a sequence number of 0, wherein the first bit sequence comprises bits for indicating timing, wherein the bits for indicating timing comprises a set of bits for indicating synchronization signal block index (SSBI); wherein the set of bits for indicating SSBI are placed in positions indicated by sequence numbers of 2, 3 and 5 in the first interleaved sequence. The devices add d first CRC bits on the first interleaved sequence to obtain a second bit sequence, interleave on the second bit sequence according to an interleave pattern to obtain a second interleaved sequence, and polar encode the second interleaved sequence to obtain the encoded sequence.

Abstract: A quantum error correction (QEC) decoding system includes an error correction chip. The error correction chip is configured to: obtain error syndrome information of a quantum circuit; and decode the error syndrome information by running neural network decoders, to obtain error result information, a core operation of the neural network decoders being a multiply accumulate (MA) operation of unsigned fixed-point numbers obtained through numerical quantization. According to the present disclosure, for the system that uses the neural network decoders for QEC decoding, the core operation of the neural network decoders is the MA operation of unsigned fixed-point numbers obtained through numerical quantization, thereby minimizing the data volume and the calculation amount desirable by the neural network decoders, so as to better meet the requirement of real-time error correction.

Abstract: A polar encoder comprises an input, an output and a processor operatively connected to the input and to the output. The input either receives first, second and third codewords, or receives information bits used by the processor for generating first, second and third probabilistic constellation shaping codewords. The processor combines the first and second codewords, to produce a first modulation symbol bit, combines the first and third codewords to produce a second modulation symbol bit, and combines the first, second and third codewords to produce a third modulation symbol bit. The output forwards the modulation symbol bits to a bit to symbol mapper. The polar encoder may be included in a transmitter that further comprises the bit to symbol mapper receiving the modulation symbol bits and generating modulation symbols, and a modulator modulating a carrier using the modulation symbols.

Abstract: A method for performing code block segmentation for wireless transmission using concatenated forward error correction encoding includes receiving a transport block of data for transmission having a transport block size, along with one or more parameters that define a target code rate. A number N of inner code blocks needed to transmit the transport block is determined. A number M—outer code blocks may be calculated based on the number of inner code blocks and on encoding parameters for the outer code blocks. The transport block may then be segmented and encoded according to the calculated encoding parameters.