Abstract: A transistor having an emitter, a base, and a collector, the transistor includes a substrate, a collector contact, a metallic sub-collector coupled to the collector contact, and the metallic sub-collector electrically and thermally coupled to the collector, and an adhesive layer between the substrate and the metallic sub-collector, the adhesive layer bonded to the substrate and in direct contact with the substrate and bonded to the metallic sub-collector and in direct contact with the metallic sub-collector, wherein the adhesive layer comprises an electrically conductive material.

Abstract: A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.

Abstract: The present invention provides an array substrate comprising a substrate, a metal conductive film layer, and an anti-reflective film layer located between the substrate and the metal conductive film layer, and a method for manufacturing the same, as well as a display device. The method comprises step S1: forming an anti-reflective film layer on a substrate by adjusting the reaction power and/or reactive gas flow during the formation of film by the chemical vapor deposition process; and step S2: forming a metal conductive film layer on the substrate finished in step S1. Through the preparation method of the array substrate, the anti-reflective film layer can have a sand-like granulation structure, such that light reflected from the metal conductive film layer can be blocked, thereby weakening or avoiding the light reflected from the surface of the metal conductive film layer, further improving the display effect of the array substrate.

Abstract: A light-emitting device includes: a substrate; a first light-emitting element row disposed on the substrate; a first wire disposed on the substrate and passing between two light-emitting elements adjacent in the first light-emitting element row; and a first bonding wire which has one end connected to one of the two light-emitting elements and another end connected to the other of the two light-emitting elements, and crosses over the first wire.

Abstract: An array substrate, a manufacturing method therefor, and a display device are provided. The array substrate comprises multiple pixel units, where at least one of the pixel units comprises a first subpixel electrode and a second subpixel electrode, the first subpixel electrode is electrically connected to a first charging thin-film transistor, and the second subpixel electrode is electrically connected to a second charging thin-film transistor. In same one pixel unit, the charging capacity of the second charging thin-film transistor is greater than the charging capacity of the first charging thin-film transistor.

Abstract: A method of manufacturing a division mask includes pulling opposite end portions of a mask member in a first direction to fasten the mask member to a fastening portion, forming a first pattern portion having a plurality of first openings on the fastened mask member, such that the first pattern portion has a longer length in the first direction toward a central portion of the first pattern portion, and cutting the opposite end portions of the mask member to detach the mask member from the fastening portion.

Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.

Abstract: A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.

Abstract: An apparatus and method are provided to: determine a unique profile to etch each wafer, execute that etch, and determine and deliver the proper chemical addition in order to maintain etch rate within tight tolerances.

Abstract: A semiconductor device includes a substrate including a first fin element, a second fin element, and a third fin element. A first source/drain epitaxial feature is disposed over the first and second fin elements. A first portion of the first source/drain epitaxial feature disposed on the first fin element and a second portion of the first source/drain epitaxial feature disposed on the second fin element merge at a merge point. A second source/drain epitaxial feature is disposed over the third fin element. A first sidewall of the second source/drain epitaxial feature interfaces a first third-fin spacer disposed along a first sidewall of the third fin element. A second sidewall of the second source/drain epitaxial feature interfaces a second third-fin spacer disposed along a second sidewall of the third fin element. The merge point has a first height less than a second height of the first third-fin spacer.

Abstract: A semiconductor device includes a first source wiring substructure connected to a plurality of source doping region portions of a transistor structure, and a second source wiring substructure connected to a plurality of source field electrodes located in a plurality of source field trenches extending into a semiconductor substrate. A contact wiring portion of the first source wiring substructure and a contact wiring portion of the second source wiring substructure are located in a wiring layer of a layer stack located on the semiconductor substrate. The contact wiring portion of the first source wiring substructure and the contact wiring portion of the second source wiring substructure each have a lateral size sufficient for a contact for at least a temporary test measurement. The wiring layer including the contact wiring portions is located closer to the substrate than any ohmic electrical connection between the first and the second source wiring substructures.

Abstract: A semiconductor device is formed to include a fin structure, a first trench at a first lateral end of the fin, a second trench at a second lateral end of the fin, and a filler filled on a first traverse side of the fin and a second traverse side of the fin. The filler is contained between the first trench and the second trench, and oxidized in-place to cause a stress to be exerted on the first and second traverse sides of the fin, the stress causing the fin to exhibit a tensile strain in a lateral running direction of the fin.

Abstract: A first dielectric layer on a substrate is provided. The first dielectric layer has a first level metal line embedded in the dielectric. An opposite gouging feature is created in a top surface of the first level metal line. The opposite gouging feature has a protuberant shape relative to the first level metal line. A second dielectric layer is formed over the first dielectric layer. A compound recess is formed in the second dielectric layer. A first portion of the recess is for a via connector positioned over the opposite gouging feature. A second portion of the recess for a second level metal line. In another aspect of the invention, a device is produced using the method.

Abstract: A microfluidic system includes a liquid drop accommodation space, an array of photosensitivity detection circuits and an array of driving circuits between an upper substrate and a lower substrate. Each photosensitivity detection circuit includes a photosensitive transistor and a first gating transistor. The photosensitive transistor has a gate electrode coupled to a first scan signal line, a source electrode coupled to a first power supply voltage signal line, and a drain electrode coupled to a source electrode of the first gating transistor. The first gating transistor has a gate electrode coupled to a second scan signal line, and a drain electrode coupled to a read signal line. Each driving circuit includes a driving transistor and a driving electrode. The driving transistor has a gate electrode coupled to a third scan signal line, a source electrode coupled to a data signal line, and a drain electrode coupled to the driving electrode.

Abstract: A capacitor structure and a method for constructing the structure are described. A metal insulator metal capacitor in an integrated circuit device includes a first dielectric layer on a substrate. The first dielectric layer has a linear trench feature in which the capacitor is disposed. A bottom capacitor plate is in a lower portion of the trench. The bottom capacitor plate has an extended top face so that the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions. A high-k dielectric layer is disposed over the extended top face of the bottom capacitor plate. A top capacitor plate is disposed in a top, remainder portion of the trench on top of the high-k dielectric layer.

Abstract: A method of fabricating a composite integrated optical device includes providing a substrate comprising a silicon layer, forming a waveguide in the silicon layer, and forming a layer comprising a metal material coupled to the silicon layer. The method also includes providing an optical detector, forming a metal-assisted bond between the metal material and a first portion of the optical detector, forming a direct semiconductor-semiconductor bond between the waveguide, and a second portion of the optical detector.

Abstract: After forming an epitaxial semiconductor layer on portions of a semiconductor located on opposite sides of a sacrificial gate structure, dopants from the epitaxial semiconductor layer are diffused into the semiconductor fin to form a dopant-containing semiconductor fin. A sacrificial gate stack is removed to provide a gate cavity that exposes a portion of the dopant-containing semiconductor fin. The exposed portion of the dopant-containing semiconductor fin is removed to provide an opening underneath the gate cavity. A channel which is undoped or less doped than remaining portions of the dopant-containing semiconductor fin is epitaxially grown at least from the sidewalls of the remaining portions of the dopant-containing semiconductor fin. Abrupt junctions are thus formed between the channel region and the remaining portions of the dopant-containing semiconductor fin.

Abstract: A display device includes: a resin layer on the circuit layer including a groove surrounding and separating a display area; light-emitting elements on an upper surface of the resin layer so as to emit light with luminances controlled by the currents; a sealing layer covering the light-emitting elements; a second substrate above the sealing layer; a sealing material provided between the sealing layer and the second substrate so as to surround the display area and the groove; and a filling layer surrounded by the sealing material between the sealing layer and the second substrate. The groove is formed along a line describing a shape that is inscribed in a rectangle and not in contact with corners of the rectangle as viewed in a direction vertical to the upper surface of the resin layer.

Abstract: An organic electroluminescence (EL) display panel includes a multi-layered wiring laminate including: a first part on which an organic EL element array is disposed and in which a first portion of a resin insulating layer is present, the resin insulating layer being a highest layer among insulating layers; a second part surrounding the first part in plan view and in which a second portion of the resin insulating layer having a bank-shape is present; and a third part disposed between the first part and the second part in plan view and having a shape of a circumferential groove in which the resin insulating layer is not present. In the third part, wiring is on an inorganic insulating layer that is lower by a layer than the resin insulating layer. The wiring on the inorganic insulating layer is spaced away from the second portion of the resin insulating layer.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers and the connection pads to each other; and a guide pattern disposed adjacent to a wall of the recess portion and disposed in the frame. An edge of the bottom surface of the recess portion has a groove portion.