Abstract: A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.

Abstract: A semiconductor stacked body includes: a first semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a first conductivity type; a quantum-well light-receiving layer containing a group III-V compound semiconductor; a second semiconductor layer containing a group III-V compound semiconductor; and a third semiconductor layer containing a group III-V compound semiconductor and being a layer whose conductivity type is a second conductivity type. The first semiconductor layer, the quantum-well light-receiving layer, the second semiconductor layer, and the third semiconductor layer are stacked in this order. The concentration of an impurity that generates a carrier of the second conductivity type is 1×1014 cm?3 or more and 1×1017 cm?3 or less in the second semiconductor layer.

Abstract: A micro LED display panel able to display images from opposite surfaces includes a substrate, a pixel circuit layer on the substrate, an insulating layer on the pixel circuit layer, at least two micro LEDs on the insulating layer and embedded in the insulating layer, at least two first electrodes, and at least one second electrode. The pixel circuit layer includes at least two TFTs. Each micro LED includes a first end adjacent to the pixel circuit layer and a second end opposite to the first end and exposed from the insulating layer. Each first electrode is between the first end of each micro LED and the pixel circuit layer. The second electrode covers the second end of each micro LED and is transparent. Each first electrode defines a light transmitting region to allow light emitted from the micro LED to pass through.

Abstract: A semiconductor device includes: one or more semiconductor dice, a die pad supporting the semiconductor die or dice, a package molded onto the semiconductor die or dice supported by said die pad, wherein the die pad is exposed at the surface of the package, and the exposed die pad with an etched pattern therein to form at least one electrical contact land in the die pad.

Abstract: In fabricating a radio frequency (RF) switch, a phase-change material (PCM) and a heating element, underlying an active segment of the PCM and extending outward and transverse to the PCM, are provided. Lower portions of PCM contacts for connection to passive segments of the PCM are formed, wherein the passive segments extend outward and are transverse to the heating element. Upper portions of the PCM contacts are formed from a lower interconnect metal. Heating element contacts are formed cross-wise to the PCM contacts. The heating element contacts can comprise a top interconnect metal directly connecting with terminal segments of the heating element. The heating element contacts can comprise a top interconnect metal and intermediate metal segments for connecting with the terminal segments of the heating element.

Abstract: A method of manufacturing a display apparatus includes preparing a substrate including a display area and a pad area outside of the display area, forming a sacrificial layer in the pad area, forming an encapsulation layer over the display area and the pad area, forming cracks in at least a portion of the encapsulation layer by increasing a volume of the sacrificial layer or by gasifying or evaporating at least a portion of the sacrificial layer, and removing at least a portion of the encapsulation layer in the pad area. A display apparatus is manufactured according to the manufacturing method.

Abstract: An OLED panel and a manufacturing method thereof are provided. The panel includes a substrate, a plurality of OLED devices disposed on the substrate and an auxiliary cathode. The OLED devices include a cathode and have light emitting areas respectively. The auxiliary cathode is disposed on the cathode of the OLED devices in electrical contact with the cathode and the auxiliary cathode is at least partially located in the light emitting areas of the OLED devices. A material of the auxiliary cathode is a transparent conductive material.

Abstract: The present application provides a touch sensor and a fabricating method thereof and a touch display panel, comprising: a substrate, where the substrate includes a plurality of grooves which are strip-shaped and intersected with each other to define a grid shape; a first infiltrating adjustment layer, disposed on an inside wall of the grooves; and a touch electrodes filled in the groove. The first infiltrating adjustment layer is positioned between the groove and the touch electrodes. An infiltration angle between the touch electrodes in solution state and the first infiltrating adjustment layer is ?, an infiltration angle between the touch electrodes in solution state and the substrate is ?, wherein ? is not equal to ?.

Abstract: A flexible semiconductor device includes a first tape having bonding pads and conductive traces formed. A semiconductor die having a bottom surface is attached to the first tape and electrically connected to the bond pads by way of electrical contacts. A second tape is attached to a top surface of the semiconductor die. The first and second tapes encapsulate the semiconductor die, the electrical contacts, and at least a part of the conductive traces.

Abstract: A first dielectric layer on a substrate is provided. The first dielectric layer has a first level metal line embedded in the dielectric. An opposite gouging feature is in a top surface of the first level metal line. The opposite gouging feature has a protuberant shape relative to the first level metal line. A second dielectric layer is over the first dielectric layer. A compound recess is in the second dielectric layer. A first portion of the recess is for a via connector positioned over the opposite gouging feature.

Abstract: A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.

Abstract: Bulk semiconductor substrates configured to exhibit semiconductor-on-insulator (SOI) behavior, and corresponding methods of fabrication, are disclosed herein. An exemplary bulk substrate configured to exhibit SOI behavior includes a first isolation trench that defines a channel region of the bulk substrate and a second isolation trench that defines an active region that includes the channel region. The first isolation trench includes a first isolation trench portion and a second isolation trench portion disposed over the first isolation trench portion. A first isolation material fills the first isolation trench portion, and an epitaxial material fills the second isolation trench portion. The epitaxial material is disposed on the first isolation material. A second isolation material fills the second isolation trench. A portion of the bulk substrate underlying the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region.

Abstract: A method of manufacturing a display apparatus includes preparing a substrate including a display area and a pad area outside of the display area, forming a sacrificial layer in the pad area, forming an encapsulation layer over the display area and the pad area, forming cracks in at least a portion of the encapsulation layer by increasing a volume of the sacrificial layer or by gasifying or evaporating at least a portion of the sacrificial layer, and removing at least a portion of the encapsulation layer in the pad area. A display apparatus is manufactured according to the manufacturing method.

Abstract: High-voltage, gallium-nitride Schottky diodes are described that are capable of withstanding reverse-bias voltages of up to and in excess of 2000 V with reverse current leakage as low as 0.4 microamp/millimeter. A Schottky diode may comprise a lateral geometry having an anode located between two cathodes, where the anode-to-cathode spacing can be less than about 20 microns. A diode may include at least one field plate connected to the anode that extends above and beyond the anode towards the cathodes.

Abstract: A power semiconductor device having an IGBT-configuration includes at least one power cell. Each power cell includes at least three trenches arranged laterally adjacent to each other. Each trench extends into a semiconductor body along a vertical direction and includes an insulator that insulates a respective electrode from the semiconductor body. The at least three trenches include at least one control trench whose electrode is electrically coupled to a control terminal, and a source trench whose electrode is electrically coupled to a first load terminal. An active mesa for conduction of at least a part of the load current is laterally confined at least by one of the at least one control trench and includes at least a respective section of each of a source region and a channel region. An auxiliary mesa is laterally confined by the source trench and one of the at least one control trench.

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

Abstract: Various embodiments include monitoring structures for integrated circuits (ICs) and related monitoring methods. In some cases, a monitoring structure includes: a set of serpentine-comb structures configured to connect with a back-end-of-line (BEOL) portion of the IC, each of the serpentine-comb structures including: a chain of interconnected laterally extending wires spanning a set of metal levels in the IC; and a set of vias connecting the chain of interconnected laterally extending wires across the set of metal levels, wherein the set of vias includes at least one via spanning between each successive level of the chain of interconnected laterally extending wires, wherein the chain of interconnected laterally extending wires and the set of vias are configured to detect a chip package interface (CPI) failure in the IC.

Abstract: A wiring substrate include a pad, an insulation layer having an opening arranged on the pad, a metal post including a seed layer and a metal plated layer, the seed layer arranged on the pad and an upper surface of the insulation layer, the metal plated layer arranged on the seed layer, and a connection metal layer formed on the metal plated layer. A side surface of the metal plated layer has a concave surface recessed inward from a lower end of the connection metal layer. A side surface of the seed layer is recessed inward from a lower end of the metal plated layer.

Abstract: A semiconductor structure includes a first dielectric layer disposed over a substrate; a first metal feature and a second metal feature embedded in the first dielectric layer and spaced from each other; an etch stop layer disposed between the first and second metal features and on sidewalls of the first dielectric layer; a second dielectric layer disposed over the etch stop layer and between the first and second metal features; and an air gap surrounded by the second dielectric layer and disposed between the first and second metal features.