Abstract: Embodiments of a charge pump converter are disclosed. In some embodiments, the charge pump converter includes a first switch, a second switch, a third switch, a first charge storage device, and a second charge storage device. The first charge storage device is connected between the first switch and the second switch. The second charge storage device is connected between the second switch and the third switch. In a charging state, the charge pump converter charges the first charge storage device and the second charge storage device. In a multiplying state, the charge pump converter discharges the first charge storage device and the second charge storage device. The multiplying state allows for the charge pump converter to generate voltage higher than an input voltage.

Abstract: A signal transmission device according to one aspect of the present invention is a signal transmission device that performs differential transmission, and includes an information processing circuit that performs processing of various types of information, and a power supply circuit that includes a voltage output circuit outputting a first applied voltage to a first signal wiring and outputting a second applied voltage to a second signal wiring. The information processing circuit includes an output voltage determination unit that determines an instruction value of at least one of the first applied voltage or the second applied voltage applied by the power supply circuit and that sends the determined instruction value to the power supply circuit.

Abstract: A quantum device including a ferromagnetic link having a ferromagnetic material, a first superconducting layer, and a second superconducting layer configured to be coupled with the first superconducting layer by the ferromagnetic link, the quantum device being configured to have a resonant frequency that is tunable based on a position of a domain wall of the ferromagnetic link, and, to reproduce a predetermined resonant frequency of the quantum device, the ferromagnetic link includes a marking point corresponding to the predetermined resonant frequency.

Abstract: An open-loop modulator (OLM) in a fractional frequency divider. A high-pass filter is applied to residual error output of a delta-sigma modulator of the OLM. The filtering is obtained as a part of matching the signal transfer function of the combination of a portion of the DSM generating the residual error and a matching block with that of the combination of a calibration PLL and a phase detector of a gain calibration circuit contained in the OLM. The gain calibration circuit cancels a gain error of digital-to-time converter (DTC) contained in the OLM.

Abstract: A system for enhancing digital signal event counting is provided. The system includes a pulse filter coupled between a plurality of comparators and a plurality of counters. The pulse filter is configured to generate a refined signal associated with a rising edge and a falling edge of each comparator output corresponding to a threshold level. The pulse filter identifies the timing characterization of at least two refined signals respectively corresponding to a lower threshold level and a next higher threshold level and generates a trigger signal corresponding to an event counting based on the timing characterization associated with both the rising edge and the falling edge. Corresponding counters increment a count at the lower threshold level or both the lower threshold level and the next higher threshold level for each event counting based on the trigger signal.

Abstract: An integrated circuit comprises a charge pump connected to a power source terminal and to a ground terminal, the charge pump having a charge pump output terminal; and a switch matrix having a plurality of switch matrix inputs and a plurality of switch matrix outputs, wherein pairs of the plurality of switch matrix outputs are connected to respective ones of a respective plurality of output terminals, and wherein the charge pump output terminal is connected to a first subset comprising at least three of the plurality of switch matrix inputs.

Abstract: A device comprising a plurality of switches and a plurality of driver units. Each driver unit is coupled to drive a respective switch of the plurality of switches. A system controller is coupled to each of the driver units by a bus, wherein the system controller is configured to coordinate driving of the respective switches by the driver units. The device further comprises at least one communication channel coupled to each of the driver units, wherein the driver units are configured to communicate with each other over the communication channel without mediation by the system controller.

Abstract: A computing system including a quantum computing device. The quantum computing device includes a Majorana island at which Majorana zero modes (MZMs) are instantiated. The quantum computing device further includes a quantum dot electrically connectable to an MZM, a capacitance sensor capacitively coupled to the quantum dot, and a controller. The controller is configured to set a Majorana island gate voltage of the Majorana island and a quantum dot gate voltage of the quantum dot to a candidate resonance Majorana island voltage and a candidate resonance quantum dot voltage. The controller is further configured to receive a capacitance measurement of the quantum dot and the Majorana island and determine whether resonance occurs based on the capacitance measurement. The controller is further configured to reset the gate voltages. The controller is further configured to output a quasiparticle poisoning value indicated by the one or more determinations of whether resonance occurs.

Abstract: An auto-redundant high voltage generating circuitry and a method to generate a high voltage to a low DC current load is provided. The circuitry incudes a digital controller and two charge pump modules each comprising a charge pump. The high voltage is generated by having either one of the two charge pump modules active at a time. Each charge pump module is configured to have its output in a high impedance state whenever the respective charge pump module is inactive, and to provide a status information signal that indicates whether the active charge pump module is functional. The digital controller monitors the active charge pump module's status information signal, and automatically switches to the other charge pump module to produce the high voltage if the status information signal indicates that the currently active charge pump module is not functional.

Abstract: Embodiments disclosed herein relate to synchronizing signals across multiple independent clock domains. In an example, a synchronizer flip-flop circuit is provided. The synchronizer flip-flop circuit includes a first latch sub-circuit coupled to receive an input and a second latch sub-circuit coupled to the first latch sub-circuit. The first latch sub-circuit includes a first group of inverters, a first diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a first bias voltage to each inverter of the first group of inverters, and a second diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a second bias voltage to each inverter of the first group of inverters.

Abstract: Presented are systems and methods for generating quadrature clock signals for high-speed signal processing and similar applications. In various embodiments, a first input signal is rotated by a first phase angle to obtain a first rotated signal that represents a first quadrature clock signal. A second input signal that is 180 degrees out-of-phase with the first signal is rotated by a second phase angle such as to produce a second rotated signal. The unaltered first input signal and the phase-shifted second signal are then combined to derive an interpolated signal. This interpolated signal may be used to generate a second quadrature clock signal. As a result, the presented systems and methods effectively addresses the challenges of low-jitter, high-accuracy clock signal generation in applications such as SERDES and other systems that require precise timing signals, thereby ensuring enhanced system performance, while reducing complexity and power consumption.

Abstract: An apparatus includes first and second capacitors, first and second switches, a current source, a first circuit, and a second circuit. The first switch is coupled between a first terminal of the first capacitor and a reference terminal. The current source has an input coupled to a power terminal. The second switch is coupled between the first terminal of the first capacitor and an output of the current source. The second capacitor has a first terminal coupled to the reference terminal. The first circuit has a first terminal coupled to a second terminal of the second capacitor, and a second terminal coupled to a second terminal of the first capacitor. The second circuit has a first input coupled to a third terminal of the first circuit, a second input coupled to the power terminal, and an output coupled to the output of the current source.

Abstract: The present application provides a clock detection method, a clock detection circuit, and an image sensor, wherein an first AND gate is receiving a first clock signal and an enable signal, a first capacitor is connected to a first switch element, and a second capacitor is connected between the first switch element and ground, the second switch element receives a preset voltage, and the second switch element is connected to the first switch element; a comparator is connected to the second switch element, and a preset voltage end, and an output end of the comparator is connected to a trigger; a trigger end of the trigger is receiving the first clock signal, and the reset end of the trigger is receiving the enable signal, to output a clock detection result signal. The present application enhances the user experience.

Abstract: Circuits and methods that can rapidly detect voltage degradation in a positive charge pump output and discharge control node accumulated charge (CNAC), thereby forcing the positive charge pump into a high-power mode. Embodiments include circuitry configured to provide a load current to a positive charge pump, including a low-dropout regulator (LDO) having a pass device that includes a control input, and a rapid charge transfer circuit coupled to the control input of the pass device and configured to be coupled to a source of a trigger voltage, the rapid charge transfer circuit configured to transfer a charge to or from the control input of the pass device when the trigger voltage falls sufficiently below a specified level so as to rapidly place the pass device in a higher conduction state, and to automatically cease to provide the transfer the charge after a settable amount of time.

Abstract: A charge pump circuit includes first and second capacitors, first, second, third and fourth switches, and a transistor. The first switch is coupled between a top plate of the first capacitor and a first voltage input terminal. The second switch is coupled between a bottom plate of the first capacitor and a reference voltage terminal. The third switch is coupled between the top plate of the first capacitor and a top plate of the second capacitor. The transistor and the fourth switch are coupled in series between the bottom plate of the first capacitor and a second voltage input terminal.

Abstract: Phase-locked loop circuitry is provided that includes a time-to-digital converter, a first frequency divider circuit coupled to an output of the time-to-digital converter, and a second frequency divider circuit coupled between the first frequency divider circuit and an input of the time-to-digital converter and having a phase interpolator with a plurality of delay circuits forming a first digital-to-analog converter (DAC) circuit and a second digital-to-analog converter (DAC) circuit separate from the first DAC circuit. The phase interpolator can be calibrated using the time-to-digital converter.

Abstract: A non-linear superconducting quantum circuit comprising at least one resonant portion and an asymmetrical threaded superconducting quantum interference device connected to said at least one resonant portion galvanically, said non-linear superconducting circuit having a first mode with a first resonant frequency and a second mode with a second resonant frequency, the ratio between said first resonant frequency and said second resonant frequency being different from ½, said at least one resonant portion being configured with inductance and capacitance values of its symbolic representation which induce with said asymmetrical threaded superconducting quantum interference device said first mode and said second mode such that, said non-linear superconducting quantum circuit has zero-point fluctuations of the superconducting phase across the asymmetrical threaded superconducting quantum interference device for the first mode and the second mode which are superior or equal to 0.05 rad.

Abstract: A circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) having a gate, a source, and a drain. The circuit further includes a first inductor and a second inductor. The first inductor has a small inductance value that is less than a larger inductance value of the second inductor. The circuit further includes a switch configured to include the first inductor in a current path shared by a gate loop and a source loop of the MOSFET when the MOSFET is turning on, and to include the second inductor in the current path shared by the gate loop and the source loop when the MOSFET is turning off.

Abstract: A gate driver includes: a gate driving circuit configured to generate a gate driving signal for a power device according to a gate control signal; and a driving capacity switch circuit configured to raise the gate driving capacity of the gate driving circuit when a time-variation signal obtained by passing the gate driving signal in the on-transition period of the power device through a high-pass filter becomes lower than a threshold value.

Abstract: A semiconductor device includes a first and a second output transistor on a high and a low side respectively, a first terminal connected to the connection node between the first and second output transistors, and a second terminal configured to be connected via a bootstrap capacitor to the first terminal. The first output transistor is driven based on a voltage between the first and second terminals. A switching circuit is provided between a terminal fed with a predetermined control supply voltage and the second terminal. The switching circuit includes a first and a second switching element, which are N-channel MOSFETs connected in series. According to the voltage at the first terminal, the first and second switching elements are turned on or off.