Patents Examined by Sibin Chen
  • Patent number: 10419007
    Abstract: A digital frequency-division phase-locked loop, including a time-to-digital converter (TDC), a digital loop filter (DLF), a digital-controlled oscillator (DCO), a feedback frequency divider (DIV), a sigma-delta modulator (SDM), and a calibration apparatus, where the calibration apparatus compensates for, based on a frequency control word and a frequency-division control word generated by the SDM, a digital signal output by the TDC to obtain a calibration signal. The DLF performs digital filtering on the calibration signal to obtain an oscillator frequency control signal and set the oscillator frequency control signal as an output signal of the DCO.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 17, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Peng Gao
  • Patent number: 10414358
    Abstract: An embodiment of the present disclosure provides a method and apparatus for supplying an electrical current. The method comprises sending the electrical current into a device from a panel comprising a dielectric core. Further, the method comprises a first sheet with a first conductive adhesive attaching the first sheet to a first side of the dielectric core, wherein the first conductive adhesive is a first electrode for a battery. Yet further, the method comprises a second sheet with a second conductive adhesive attaching the second sheet to a second side of the dielectric core, wherein the second conductive adhesive is a second electrode for the battery. Still further, the method comprises operating the device using the electrical current from the battery in the panel.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: September 17, 2019
    Assignee: The Boeing Company
    Inventor: Sesinando Prado Macaraeg
  • Patent number: 10404238
    Abstract: A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventor: Young Hoon Kim
  • Patent number: 10403330
    Abstract: Memory devices may have internal circuitry that employs voltages higher than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate, internally, higher voltages for operation. The number of available charge pumps in a memory device may be higher than the number used for certain memory operations. Gating circuitry may be used to selectively enable charge pump cores based on power demands that may be associated with a mode of operation and/or a command.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Harish N. Venkata, Yu-Feng Chen
  • Patent number: 10396580
    Abstract: A power control and delivery system for improving and prolonging the performance of batteries through a total power source comprised of a battery, a power controller and a power buffer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: August 27, 2019
    Assignee: AT&T Intellectual Property I, L.P.
    Inventor: Jesse Chan
  • Patent number: 10396808
    Abstract: The exemplified technology provides a circuit and clock synthesis technique that suppresses quantization noise in a ?? fractional-N phase-locked loop (PLL) using a fineresolution multi-element fractional divider. The circuit and clock synthesis method beneficially suppresses noise uniformly over the entire frequency range. The circuit can be implemented using mostly digital circuitry, and is applicable for use with both analog and digital PLLs. With an 8-element fractional divider, it is observed that the circuit and clock synthesis technique can suppress quantization noise while incurring only a small increase in hardware complexity.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: August 27, 2019
    Assignee: Board of Regents, The University of Texas System
    Inventor: Nan Sun
  • Patent number: 10388341
    Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Tsuneo Abe
  • Patent number: 10389169
    Abstract: This document discusses, among other things, an electronic circuit and method for defaulting to a valid battery supply to power an electronic device. In an example, an electronic circuit can be configured to receive information about the battery supply (e.g., an internal battery), such as the battery supply voltage (VBAT), and to determine if the battery supply is valid or invalid using the received information (e.g., comparing the VBAT to a threshold). If VBAT is valid, the electronic device can default to receiving power from the battery supply. If VBAT is invalid, the electronic device can receive power from another power supply, such as an external supply.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: August 20, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James A. Siulinski, Kenneth P. Snowdon
  • Patent number: 10381497
    Abstract: An apparatus and method for optical-power-transfer (OPT). A light source converts electrical energy into light, and the light is transmitted from the active layer of the light source directly to the active layers of a series of photovoltaic (PV) devices without first passing through a conduction layer of the PV device. Thus, absorption in the conduction layer is avoided, and the efficiency of the OPT system is improved. The PV devices are configured to each generate equal current, and the PV devices are electrically connected in series. PV devices are arranged in series with light first propagating through PV devices closer to the light source, and farther PV devices having a longer propagation length, such that the light absorbed and current generated by each PV device is equal to the other PV devices. In one implementation, the PV devices are configured in a laser cavity with the light source.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: August 13, 2019
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventor: Masanori Ishigaki
  • Patent number: 10381843
    Abstract: Aspects of a hierarchical power distribution network are described. In some embodiments, a first guided surface waveguide probe launches a first guided surface wave along a surface of a terrestrial medium within a first power distribution region. A guided surface wave receive structure obtains electrical energy from the first guided surface wave. A second guided surface waveguide probe launches a second guided surface wave along the surface of the terrestrial medium within a second power distribution region using the electrical energy obtained from the first guided surface wave.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: August 13, 2019
    Assignee: CPG Technologies, LLC
    Inventors: James F. Corum, Kenneth L. Corum, Basil F. Pinzone, Jr., James D. Lilly
  • Patent number: 10374583
    Abstract: A method is described and in one embodiment includes detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode; placing the circuit in a second hysteresis mode subsequent to the detecting; and returning the receiver to the first hysteresis mode subsequent to completion of receipt of the data packet to await receipt of a next data packet. In certain embodiments, the first hysteresis mode is a high hysteresis mode and the second hysteresis mode is a standard hysteresis mode. In some embodiments, a level of each of the first and second hysteresis modes is dynamically tunable.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: August 6, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Piotr Olejarz, Daniel Saari, Ara Arakelian
  • Patent number: 10374451
    Abstract: The invention relates to a portable, skid mounted, wheeled and/or collapsible hybrid-power lighting and energy management system for harsh, remote and/or high latitude locations. The system combines an internal combustion engine (ICE) power source with a control system for providing power to light system. The system may also include a battery storage system, an ICE heating system and/or renewable solar and/or wind power systems in a manner that improves efficiency and reliability of operation in such locations, while preserving and improving functionality of operation and significantly reducing operator interaction during set-up and operation.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: August 6, 2019
    Assignee: CLEANTEK INDUSTRIES INC.
    Inventor: Joshua Curlett
  • Patent number: 10373671
    Abstract: A device may include an integrated circuit and a jitter generator located on the integrated circuit. The jitter generator may include a random number generator to generate a random number in response to a clock input signal. The jitter generator may also include delay-causing circuitry to receive the clock input signals, where the delay-causing circuitry may create a delayed clock input signal. The jitter generator may also include a phase mixer to receive the random number, the delayed clock input signal, and the clock input signal, where the phase mixer additionally outputs a clock output signal having the clock input signal and having jitter.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Tyler J. Gomm
  • Patent number: 10366828
    Abstract: The present invention relates to a transmitting device for wireless power transmission, which includes: a bowl-shaped transmitting device body; and a transmitting coil unit for wirelessly transmitting power to a receiving device based on power supplied from a power source. The transmitting coil unit may include a multi-loop coil unit wound in the bottom surface of the transmitting device body, and a helical coil unit wound around the side wall of the transmitting device body, the helical coil unit being wound to increase the radius of a coil loop in a direction to the upper part of the transmitting device body, and being extended from the end of the multi-loop coil unit.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: July 30, 2019
    Assignee: KOREA ELECTROTECHNOLOGY RESEARCH INSTITUTE
    Inventors: Young Jin Park, Jin Wook Kim, Kwan Ho Kim, Do Hyun Kim, Jong Ryul Yang
  • Patent number: 10365678
    Abstract: An method comprising activating an internal switch within a packaged electronic device to connect to a reference ground of an internal voltage source to a first input of an analog front end, receiving an external ground potential voltage at a first package pin of the packaged electronic device, generating a zero detector output signal for the packaged electronic device at a second package pin, activating the internal switch to connect the first input of the analog front end to the internal voltage source, receiving a second voltage level at the first package pin that generates a second output signal that matches the zero detector output signal, and receiving trim instructions to trim an internal voltage generated by the internal voltage source to a voltage level that is closer to a target voltage level.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: July 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Maciej Piotr Jankowski, Peng Cao
  • Patent number: 10361593
    Abstract: The Dual frequency HF-UHF identification device comprises a RFID integrated circuit with a power supply having a HF part, formed by a HF rectifier connected to a HF antenna, and a UHF part formed by a UHF rectifier connected to a UHF antenna. The RFID integrated circuit comprises a storage capacitor common to the HF and UHF parts of the power supply. The HF rectifier output and the UHF rectifier output are both continuously connected to the supply terminal of the common storage capacitor. Further, the supply terminal of the common storage capacitor is connected, on the one hand, to the output of the HF rectifier through a diode arranged so as to block a current from said supply terminal to the HF rectifier output and, on the other hand, directly to the output of the UHF rectifier formed by a charge pump.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: July 23, 2019
    Assignee: EM Microelectronic-Marin SA
    Inventors: Jiri Kolman, Goran Stojanovic, Catalin Lazar, Frederic Sacksteder
  • Patent number: 10348243
    Abstract: Embodiments of the present disclosure provide a circuit structure including: a switching transistor including a gate terminal, a back-gate terminal, a source terminal, and a drain terminal; a biasing node coupled to the back-gate terminal of the switching transistor, the biasing node being alternately selectable between an on state and an off state; a first capacitor source-coupled to the switching transistor; a second capacitor drain-coupled to the switching capacitor; and a first enabling node source-coupled to the switching transistor, the first enabling node being alternately selectable between an on state and an off state.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chi Zhang, Arul Balasubramaniyan
  • Patent number: 10348295
    Abstract: A packaged unidirectional power transistor comprises a package with a number of pins which provide a voltage and/or current connection between the outside and the inside. Inside the package, a bidirectional vertical power transistor is present with a controllable bidirectional current path, through a body of the bidirectional vertical power transistor, between a first current terminal of the bidirectional vertical power transistor connected to the first current pin and a second current terminal of the bidirectional vertical power transistor connected to the second current pin. A control circuit connects the control pin to the body terminal and the control terminal to drive the body and the control terminal, which allows current through the body in a forward direction, from the first current terminal to the second terminal, as a function of the control voltage, and to block current in a reverse direction regardless of the voltage.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: July 9, 2019
    Assignee: NXP USA, INC.
    Inventors: Philippe Dupuy, Hubert Michel Grandy, Laurent Guillot
  • Patent number: 10340791
    Abstract: A method of operating a charge pump where successive values of a charge pump output voltage are measured and compared is presented. The result of the comparison is used to adjust one or more parameters of the charge pump operation A charge pump's maximum efficiency is tracked by storing and comparing successive output voltage values, with sample and hold circuitry.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: July 2, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Guillaume de Cremoux
  • Patent number: 10340906
    Abstract: Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor CB, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode DB1 and a second parasitic diode DB2 are provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: July 2, 2019
    Assignees: SOUTHEAST UNIVERSITY, SOUTHEAST UNIVERSITY-WUXI INTEGRATED CIRCUIT TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Weifeng Sun, Yunwu Zhang, Kuo Yu, Jing Zhu, Shen Xu, Qinsong Qian, Siyang Liu, Shengli Lu, Longxing Shi