Patents Examined by Sibin Chen
  • Patent number: 11942931
    Abstract: A switching circuit comprises a radio frequency (RF) switch, a gate resistor, a voltage source, a transmission gate, and coupling circuitry configured to couple a gate of the RF switch, a first side of the gate resistor, and the transmission gate at a first node and the voltage source, a second side of the gate resistor, and the transmission gate at a second node.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: March 26, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Lynn Yun Kong, Yi Yang, Bo Zhou
  • Patent number: 11936381
    Abstract: A switch module with an automatic switching function and a method for automatically switching the switch module according to the load, wherein a first comparator and a second comparator are configured to automatically determine whether the load is light or heavy according to the voltage divided by a first resistor and a second resistor and the voltage of a source resistor, thereby generating a voltage control signal. A plurality of transistors are configured to receive a gate input signal according to the voltage control signal, thereby selectively bringing a GaN transistor or a MOSFET transistor in a conducting state. In this way, the output quality and efficiency of the power supply at light and heavy loads can be improved according to the characteristics of different transistors.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: March 19, 2024
    Assignee: POTENS SEMICONDUCTOR CORP.
    Inventors: Ching Kuo Chen, Wen Nan Huang
  • Patent number: 11929674
    Abstract: In an embodiment, a voltage multiplier comprises an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered sub-sequences. Capacitors are coupled: between each odd intermediate node in the first sub-sequence and the first control node; between each even intermediate node in the first sub-sequence and the second control node; between each odd intermediate node in the second sub-sequence and a corresponding odd intermediate node in the first sub-sequence; and between each even intermediate node in the second sub-sequence and a corresponding even intermediate node in the first sub-sequence. The circuit comprises selectively conductive electronic components coupled to the intermediate nodes.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: March 12, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Francesco Pulvirenti
  • Patent number: 11929753
    Abstract: A non-linear charge pump for phased lock loops. Furthermore, an auxiliary charge pump apparatus, comprising a positive switch electrically connected to a current source configured to supplement power to a charge pump, a negative switch electrically connected to a current sink configured to discharge power from the charge pump, a windowing comparator, further comprising an input signal received from a phase-locked loop, a first comparator configured to compare the input signal against a high voltage threshold, a second comparator configured to compare the input signal against a low voltage threshold, an AND logic gate configured to provide a window signal and an activation circuit electrically connected to the positive switch and negative switch. Additionally, a non-linear charge pump system and method for reacquiring frequency lock of a phase lock loop.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: March 12, 2024
    Assignee: United States of America as represented by the Secretary of the Navy
    Inventors: Jia-Chi Samuel Chieh, Henry Ngo
  • Patent number: 11923862
    Abstract: A first reception processing unit performs a process of receiving a first signal transmitted on a first transmission line, a second reception processing unit performs a process of receiving a second signal transmitted on a second transmission line, and an output speed control unit controls output speeds of the first signal and the second signal subjected to the reception process. A system switching unit selects and outputs the first signal or the second signal subjected to a reception process, and an output processing unit performs a process for output to another apparatus on the output from the system switching unit. A reception side clock output unit outputs a clock signal giving a processing timing of each process, and a clock frequency control unit adjusts a frequency of the clock signal giving the processing timing to the output processing unit.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: March 5, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Fumikazu Inuzuka, Kei Kitamura, Akira Hirano, Masahito Tomizawa, Takuya Ohara
  • Patent number: 11916476
    Abstract: A voltage generator and a voltage generating method are provided. The voltage generator includes at least one first charge pump circuit, at least one second charge pump circuit, an oscillator, a passing circuit, and a voltage detector. The first charge pump circuit is configured to receive a clock signal to generate a first pump voltage. The second charge pump circuit is configured to receive the clock signal to generate a first pump voltage. The oscillator is configured to provide the clock signal. The passing circuit is configured to receive the clock signal, a power-on detection signal and an external command. The voltage detector is configured to receive an operation voltage, and generate the power-on detection signal by detecting the operation voltage. The passing circuit determines whether to transmit the clock signal to the second charge pump circuit or not to activate or deactivate the second charge pump circuit.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: February 27, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ting-Shuo Hsu
  • Patent number: 11916550
    Abstract: A integrated circuit includes a clock generator and a multiplexing latch circuit. The clock generator generates first and second latching clock signals in response to a select signal and a clock signal having a clock signal waveform, each of the first latching clock signal and the second latching clock signal having the clock signal waveform. The multiplexing latch circuit selects either first data on a first data line or second data on a second data line based on the first latching clock signal and the second latching clock signal, and stores and outputs the selected data.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hyunsung Hong
  • Patent number: 11909303
    Abstract: A bypass device of an HVDC sub module according to the present invention comprises: a sub module for generating a voltage in an HVDC system; a bypass switch driving unit for driving a bypass switch located at an input terminal of the sub module; a sub module controller for monitoring a state of the sub module to transmit the monitored state to a system controller, and controlling the sub module and the bypass switch driving unit according to a command of the system controller; and a voltage monitoring unit for controlling the bypass switch driving unit by monitoring a voltage of a capacitor located in the sub module.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: February 20, 2024
    Assignee: HYOSUNG HEAVY INDUSTRIES CORPORATION
    Inventors: Jung Ki Hong, Dong Woo Seo
  • Patent number: 11898428
    Abstract: A signal generator, system, and method for electromagnetically heating of a hydrocarbon formation. The method involves determining a desired output signal having a desired power spectral density; generating a plurality of source signals, based on the desired output signal; modulating the plurality of source signals, based on the desired output signal, to provide a plurality of modulated signals capable of providing the desired power spectral density; combining one or more of the plurality of modulated signals into a combined signal; transforming the combined signal to have the desired power spectral density, thereby providing at least one output signal; and applying the at least one output signal to a load having a frequency-dependent impedance to produce at least one standing electromagnetic wave along a length of the load. The at least one standing electromagnetic wave includes at least a partial standing electromagnetic wave.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: February 13, 2024
    Assignee: Acceleware Ltd.
    Inventors: Jorgen S. Nielsen, Michal M. Okoniewski
  • Patent number: 11881759
    Abstract: A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: January 23, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Fabrizio Bognanni, Giovanni Caggegi, Giuseppe Cantone, Vincenzo Marano, Francesco Pulvirenti
  • Patent number: 11876444
    Abstract: A power control unit is provided to control the efficiency of a charge pump converter having a first input terminal and a second input terminal, a primary attenuator and a secondary attenuator between a first input terminal and the second input terminal, a first output terminal, a second output terminal, a secondary attenuator controlling terminal and a primary attenuator controlling terminal to be plugged to the power control unit. The primary attenuator controlling terminal and the secondary attenuator controlling terminal are to attenuate or amplify a signal of the first input terminal and the second input terminal.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: January 16, 2024
    Assignee: EM Microelectronic-Marin SA
    Inventor: Alessandro Venca
  • Patent number: 11876488
    Abstract: The present disclosure discloses a direct current (DC)-DC boost converter, which includes a battery terminal providing a battery voltage, a charge pump coupled between the battery terminal and an interior node, and a power inductor coupled between the interior node and a power supply terminal that provides a power voltage to a radio frequency transceiver. The charge pump is configured to provide an interior voltage at the interior node based on the battery voltage. Herein, the interior voltage toggles between the battery voltage and two times the battery voltage. The charge pump includes a first switch coupled between the battery terminal and the interior node, a second switch coupled between the battery terminal and a connecting node, a third switch coupled between the connecting node and ground, and a flying capacitor coupled between the interior node and the connecting node of the second switch and the third switch.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: January 16, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Michael R. Kay, Jeffrey D. Potts, Michael J. Murphy
  • Patent number: 11876512
    Abstract: A method of using Josephson Junctions to convert the envelope of radio-frequency signals into baseband control pulses includes injecting a biasing current into an envelope detector circuit. The biasing current is identified based on first and second critical currents of superconducting devices in the envelope detector circuit. The first critical current corresponds to the envelope detector circuit receiving no RF signals. The second critical current corresponds to the envelope detector circuit receiving maximum RF signals. The method further includes receiving a modulated radio frequency (RF) signal at the envelope detector circuit to detect an envelope of the received RF signal. The output of the envelope detector circuit is used to drive an output load. The output is generated based on the detected envelope by the envelope detector circuit.
    Type: Grant
    Filed: July 23, 2022
    Date of Patent: January 16, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Matthew Beck
  • Patent number: 11870442
    Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: January 9, 2024
    Assignee: Apple Inc.
    Inventors: Vivekanandan Venugopal, Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh, Teng Wang
  • Patent number: 11854755
    Abstract: A direct current electric circuit interrupting switch assembly is disclosed that comprises a pyroswitch assembly, which comprises at least two pyroswitches, which are connected in parallel with each other and are each per se integrated in its respective electrically conductive branch together forming a second branch of the primary electric conductor the switch assembly, with a first, preceding pyroswitch and a second, subsequent, or last pyroswitch. Each of said pyroswitches comprises an interrupting member, by means of which each circuit with each of the pyroswitches is either connected during normal operation or is interrupted by displacing each corresponding interrupting member into another position, when a pre-determined condition is met.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: December 26, 2023
    Inventors: Mitja Koprivsek, Brane Lebar
  • Patent number: 11843371
    Abstract: A semiconductor device of the present invention includes: a P-type output transistor configured to have a source to which a power supply voltage is applied, and a drain connected to an external connection pad; a gate wiring configured to be connected to a gate of the output transistor; a signal transmitting portion configured to transmit an input signal to the gate wiring; and a voltage-breakdown protecting portion configured to apply the power supply voltage to a back gate of the output transistor if a voltage on the external connection pad is equal to or lower than the power supply voltage, or the voltage-breakdown protecting portion bringing the signal transmitting portion into a disconnection state and applies the voltage on the external connection pad to the gate and the back gate of the output transistor if the voltage applied on the external connection pad is higher than the power supply voltage.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: December 12, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Fumiaki Yanagihashi
  • Patent number: 11837282
    Abstract: A charge pump apparatus includes a first charge pump system, a second charge pump system, a switch transistor, and a voltage regulation circuit. The first charge pump system converts a first supply voltage into a first boost voltage. The second charge pump system converts a second supply voltage into a second boost voltage. The switch transistor is coupled to the first charge pump system and the second charge pump system, and outputs an output voltage according to the second boost voltage. The switch transistor includes a control terminal receiving the second boost voltage, a first terminal receiving the first boost voltage, and a second terminal outputting the output voltage. The voltage regulation circuit successively adjusts a code of a voltage regulation signal according to the output voltage, in order to control the second charge pump system to successively adjust the second boost voltage according to the voltage regulation signal.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: December 5, 2023
    Assignee: eMemory Technology Inc.
    Inventors: Chia-Fu Chang, Sung-Ling Hsieh
  • Patent number: 11836001
    Abstract: A circuit device includes a first power supply line to which a first power supply voltage is supplied, a second power supply line to which a second power supply voltage is supplied, a third power supply line, a power supply circuit, a predetermined circuit, a first power-on reset circuit, a second power-on reset circuit, and a reset control circuit. When a first power-on reset signal and a second power-on reset signal become a reset release level, the reset control circuit sets a third power-on reset signal output to at least a part of the predetermined circuit to a reset release level.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: December 5, 2023
    Inventor: Sho Matsuzaki
  • Patent number: 11838013
    Abstract: A semiconductor device that normally-off drives a first transistor that normally-on drives, the semiconductor device includes a first circuitry, a second circuitry, and a first diode. The first circuitry that is connected with a power supply voltage and a ground voltage, detects the power supply voltage, and outputs a transition state of the power supply voltage. The second circuitry that is connected with the power supply voltage, the ground voltage, the first circuitry, and a second transistor, and outputs a drive voltage of a second transistor connected in series with the first transistor, based on an output of the first circuitry. The first diode having an anode connected with a drive terminal of the first transistor and a cathode connected with an output terminal of the second transistor.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: December 5, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yasuyuki Fujiwara, Yiyao Liu, Yusuke Sato, Naotsugu Kako, Hideaki Majima
  • Patent number: 11824434
    Abstract: An integrated driver applied to a voltage converter having a switched capacitor conversion circuit, the integrated driver including: a first die having a first-type power transistor; a second die including at least one second-type power transistor, where a withstand voltage of the first-type power transistor is higher than a withstand voltage of the second-type power transistor; and where the first die and the second die are coupled in series between a high potential terminal and a low potential terminal of the voltage converter, such that the first-type power transistor receives a high voltage signal.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: November 21, 2023
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Kaiwei Yao, Wang Zhang, Chen Zhao