Abstract: Aspects of the disclosure relate to a negative bias circuit for power device driving. An apparatus may include a power source, a gate impedance path, a capacitor in series with the gate impedance path, and a clamping circuit for a transistor gate.

Abstract: A sensing circuit coupled to a sensor includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an oscillator. The first transistor, coupled to a first current source and the sensor, receives a sensing current from the sensor. A gate terminal of the first transistor is connected to a source terminal of the first transistor. The second transistor, coupled to the first transistor and a second current source, generates a first current according to the sensing current. The first current is greater than the sensing current. The third transistor, coupled to the second transistor and the second current source, generates a second current according to the first current. The fourth transistor, coupled to the third transistor, generates a third current. The oscillator is coupled to the fourth transistor. The oscillator generates a signal having an oscillation frequency according to the third current.

Abstract: In an embodiment, a voltage multiplier comprises an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered sub-sequences. Capacitors are coupled: between each odd intermediate node in the first sub-sequence and the first control node; between each even intermediate node in the first sub-sequence and the second control node; between each odd intermediate node in the second sub-sequence and a corresponding odd intermediate node in the first sub-sequence; and between each even intermediate node in the second sub-sequence and a corresponding even intermediate node in the first sub-sequence. The circuit comprises selectively conductive electronic components coupled to the intermediate nodes.

Abstract: A voltage converter system includes a negator coupled to a switched-capacitor converter (SCC). The negator circuit is coupled to an input terminal and generates a negative input voltage signal. The negator circuit includes a flying capacitor, a pair of first switches and a pair of second switches connected in a H-bridge configuration. The SCC is coupled to the input terminal and the negator circuit. The SCC includes a plurality of converter stages. Each stage of the plurality of converter stages includes a capacitor and an assembly of a first switch and a second switch. The system further includes a control unit, to activate or deactivate the pair of first switches, the pair of second switches, each of the first switches, and each of the second switches. A configuration of the negator circuit and the SCC results in a voltage conversion ratio between the output voltage signal and the input voltage signal.

Abstract: A semiconductor device includes a first sensing stage configured to sense a voltage differential of a data signal and a reference signal and output a first amplified voltage differential, wherein the first amplified voltage differential includes a first voltage at a first output node and a second voltage at a second output node. The semiconductor device further includes a second sensing stage configured to sense the first amplified voltage differential and output a second amplified voltage differential, where the second amplified voltage differential includes a third voltage at a third output node and a fourth voltage at a fourth output node. A first power gating circuit is coupled to the third output node and a second power gating circuit is coupled to the fourth output node.

Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.

Abstract: A power converter having a charge pump frequency switching control mechanism is provided. In the power converter, frequencies of a plurality of pulse waves of a clock signal are determined, according to a level of a high-side control signal outputted to a control terminal of a high-side switch from a control circuit or a voltage of the control terminal (and a voltage of a second terminal) of the high-side switch. In the power converter, a charge pump supplies power to a high-side driver circuit at the frequencies of the clock signal, and the high-side driver circuit uses the power from the charge pump to drive the high-side switch and to pull up the voltage of the control terminal of the high-side switch.

Abstract: An automatic level control (ALC) circuit includes an input configured to receive a radio frequency (RF) input signal, a level control circuit coupled to the input and configured to control a level of the RF input signal in response to a feedback signal, and an output coupled to the level control circuit and configured to output a level-controlled RF output signal. The ALC circuit further includes a feedback path coupled to the output and configured to sample the level-controlled RF output signal to determine an error detected in the level-controlled RF output signal, and to generate the feedback signal in accordance with the error. The ALC circuit still further includes a feedforward path coupled to the input and configured to emulate a frequency response in the feedback path and to adjust the error determined in the feedback path according to the emulated frequency response.

Abstract: A linear power supply circuit includes an output transistor provided between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied, and a driver configured to drive the output transistor based on the difference between a voltage based on the output voltage and a reference voltage. The driver includes a differential amplifier, a converter, and a first capacitor provided between the output of the differential amplifier and a ground potential. The linear power supply circuit further includes a source follower circuit including a first transistor, and moreover includes a second transistor connected in series with the output transistor and constituting together with the first transistor a current mirror circuit, and a second capacitor connected to the control terminal of the first transistor.

Abstract: A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.

Abstract: A circuit arrangement for driving a semiconductor switch includes an undervoltage detection circuit to indicate an undervoltage state when a supply voltage falls below a voltage threshold value. A temperature detection circuit indicates that a temperature of a semiconductor switch exceeds a temperature threshold value. A control circuit for driving the semiconductor switch deactivates the semiconductor switch when the undervoltage detection circuit indicates an undervoltage state, and to reactivate the semiconductor switch when the undervoltage detection circuit no longer indicates an undervoltage state. In this case, the reactivation is delayed by a defined delay time when the semiconductor switch was previously deactivated due to an undervoltage state and the temperature detection circuit indicates that the temperature of the semiconductor switch exceeds the temperature threshold value.

Abstract: A switching circuit includes a first antenna terminal and a second antenna terminal, a first input-output terminal and a second input-output terminal, a plurality of switches and a ground switch. When an electrical connection destination of the first input-output terminal is switched to the first antenna terminal, a first path switch included in the plurality of switches and provided along a first path connecting the first input-output terminal and the first antenna terminal to each other, and a second path switch and the ground switch provided along a second path connecting the second input-output terminal and the ground to each other, the second path switch included in the plurality of switches, are in conducting states, and a third path switch included in the plurality of switches and provided along a third path connecting the first path and the second path to each other is in a non-conducting state.

Abstract: A dynamic D flip-flop with an inverted output involves an input end (101) used for receiving input data; an output end (102) used for providing output data to respond to the input data; a clock signal end (103) used for receiving a clock signal; a first latch (104) used for latching the input data from the input end (101) and performing inverting transmission on the input data under the control of the clock signal; a second latch (105) used for latching data from the first latch (104) and performing inverting transmission on the data latched by the first latch (104) under the control of the clock signal; and an inverter (106) used for performing inverting output on the data received from the second latch (105), the first latch (104), the second latch (105), and the inverter (106) being sequentially connected in series between the input end and the output end.

Abstract: A signal transmission device 100 includes an isolated signal transmission circuit 10 configured to transmit a pulse signal from a primary circuit system 1p via a first isolating element ISO1 to a secondary circuit system 1s, and an isolated power supply control circuit 20 which serves as a controlling agent of an isolation-type power supply that generates a second supply voltage Vcc2 for the secondary circuit system 1s from a first supply voltage Vcc1 for the primary circuit system 1p and which transmits an output feedback signal of the isolation-type power supply from the secondary circuit system 1s via a second isolating element ISO2 to the primary circuit system 1p.

Abstract: An impedance calibration circuit includes a variable impedance circuit, a detection circuit and a control circuit. The variable impedance circuit includes conduction paths connected in parallel between an output terminal and a supply terminal coupled to a first supply voltage. The variable impedance circuit is configured to adjust an impedance at the output terminal by enabling one or more of the conduction paths according to a calibration code. The detection circuit is configured to detect a change in impedance of the conduction paths by applying a second supply voltage to a reference terminal through a detection path, and accordingly generate an input voltage at the reference terminal. An electric potential of the second supply voltage is equal to an electric potential of the first supply voltage. The control circuit is configured to compare the input voltage with reference voltages to generate the calibration code.

Abstract: The technology of this application relates to a drive circuit with an energy recovery function, including a control circuit, an energy recovery drive circuit, a switch circuit, and a direct current power supply. The control circuit is configured to control an energy storage capacitor in the energy recovery drive circuit to charge a junction capacitor of the switch circuit at a first moment, and enable the direct current power supply to charge the junction capacitor of the switch circuit through the energy recovery drive circuit at a second moment, so that the switch circuit is switched on. The control circuit is further configured to control the junction capacitor of the switch circuit to charge the energy storage capacitor in the energy recovery drive circuit at a third moment, and enable the junction capacitor of the switch circuit to discharge to a ground through the energy recovery drive circuit at a fourth moment, so that the switch circuit is switched off.

Abstract: Disclosed is a semiconductor device which includes at least one flip-flop. The flip-flop includes a first latch that includes a first data path receiving input data in response to a transmission signal and outputting middle data, and a first feedback path feeding back the middle data, and a second latch that includes a second data path receiving the middle data in response to the transmission signal and outputting output data, and a second feedback path feeding back the output data, and at least one of the first feedback path and the second feedback path is disabled prior to the first data path or the second data path.

Abstract: Provided is a gate controller having a primary signal input which is AC coupled to the gate through a capacitor, one or more bias inputs each connected to the gate through a resistor such as to control the DC voltage bias of the gate and therefore the conductivity o the switching element. The bias inputs can be properly connected to internal nodes of the charge pump, or charge pump stages, such that the gate controller is self-biased, without using bias-reference external to the charge pump. The gate controller is programmable by using potentiometers in place of the bias resistors. The programmable gate controller stages can be connected to form a programmable gate controlled charge pump.

Abstract: A computing system including a quantum computing device. The quantum computing device includes a Majorana island, a quantum dot (QD), an electrical ground, and a capacitance sensor. The computing system further includes a controller configured to, in each of a plurality of sampling iterations, control the quantum computing device to electrically couple the Majorana island to the electrical ground, disconnect the Majorana island from the electrical ground, electrically couple the Majorana island to the QD, scan over values of a first plunger gate voltage applied to a first plunger gate and a second plunger gate voltage applied to a second plunger gate, and output quantum capacitance measurements. The controller is further configured to receive the quantum capacitance measurements and determine a measured distribution of resonance regions associated with the sampling iterations.

Abstract: Multiphase power converter with CLC resonant circuit. One example is a method of operation a power converter, the method including: charging, during a first on-time, a first output inductor by way of a first switching-tank circuit defining a first switch node coupled to a first lead of a resonant inductor; creating, during the first on-time, a first current flow into the first switching-tank circuit through the resonant inductor; and then charging, during a second on-time, a second output inductor by way of a second switching-tank circuit defining a second switch node coupled to a second lead of the resonant inductor; and creating, during the second on-time, a second current flow into the second switching-tank circuit through the resonant inductor.