Abstract: A charge pump circuit is provided. The charge pump circuit includes a first transistor, a first capacitor, a second transistor, and a second capacitor. The first transistor has a first end and a second end. The first capacitor has a first end and a second end. The second end of the first capacitor is electrically connected to the second end of the first transistor. The second transistor has a first end and a second end. The first end of the second transistor is electrically connected to the second of the first transistor. The second capacitor has a first end and a second end. The first end of the second capacitor is electrically connected to the second end of the second transistor.

Abstract: An electric device is provided which can reduce risk of malfunction. This electric device is provided with a motor (31), an inverter circuit (30) which has switching elements (S1-S6) and which drives the motor (31), and a charge pump circuit (22) which generates the drive voltage of the switching elements (S1-S6). A discharge circuit (a discharge resistor R and a capacitor C1) is provided between a power line to which a drive voltage (VM) of the motor (31) is supplied and an output terminal (a VGT terminal) of the charge pump circuit (22). Energy of the surge voltage (Vs) generated in a parasitic inductance (Ls) when the switching elements (S4-S6) are turned off is absorbed by the discharge circuit (the discharge resistor R and the capacitor C1).

Abstract: A flip-flop including a scan enable input for receiving a scan enable signal, a clock input for receiving a clock signal, input select circuitry that is configured to select between a data input and a scan input based on a state of the scan enable signal for providing a selected input, latching circuitry that is configured to latch the selected input to a preliminary output node in response to transitions of the clock signal, and output select circuitry that is configured to provide a state of the preliminary output node to a selected one of a scan output and a data output based on a state of the scan enable signal. The flip-flop may be implemented using fast yet leaky transistors. The data output may be disabled to prevent toggling other circuitry when scanning into or out of a memory for data retention.

Abstract: A control circuit, a chip and a control method are disclosed. The control circuit includes: an adjustment signal generation unit configured to detect an electrical signal reflecting a power supplied to a load under control of a current value of a reference signal, generate a feedback signal and output an adjustment signal based on both the feedback signal and the reference signal; and a control unit coupled to the adjustment signal generation unit and configured to control the switching circuit on and off based on the adjustment signal. With the generated adjustment signal that reflects a change in an adjustment metric indicated in the reference signal, the control circuit and the driving system can be adapted in real time to the specifications of any AC power standard. Moreover, much more granular adjustments can be made in the power supplied to the load.

Abstract: An apparatus for in-phase and quadrature phase (“IQ”) generation comprises a CMOS clock distributor for providing a clock input. A first IQ divider circuit is configured for receiving the clock input and dividing the clock input into in-phase and quadrature phase (IQ) output. A clock processing circuit is configured for processing the clock input. A second IQ divider circuit is configured for receiving the processed clock input and dividing the processed clock input into in-phase and quadrature phase (IQ) output. A multiplexer circuit is coupled to the first IQ divider circuit and the second IQ divider circuit for selecting the IQ output from the first IQ divider circuit or the second IQ divider circuit.

Abstract: A linear power supply circuit includes an output transistor provided between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied, and a driver configured to drive the output transistor based on the difference between a voltage based on the output voltage and a reference voltage. The driver includes a differential amplifier, a converter, and a first capacitor provided between the output of the differential amplifier and a ground potential. The linear power supply circuit further includes a source follower circuit including a first transistor, and moreover includes a second transistor connected in series with the output transistor and constituting together with the first transistor a current mirror circuit, and a second capacitor connected to the control terminal of the first transistor.

Abstract: The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.

Abstract: Provided a voltage generating circuits including assist circuits and operating methods thereof. The voltage generating circuit which includes an assist circuit that generates an assist signal indicating an enable mode or a disable mode. When a first power supply voltage is lower than an assist reference voltage, the assist signal indicates the enable mode, and a compensation circuit generates a compensation signal based on the first power supply voltage. An internal voltage converter generates a regulated voltage based on the first power supply voltage, and a charge pump circuit generates a pump voltage based on the regulated voltage. The compensation signal compensates for the regulated voltage.

Abstract: A system includes a level shifter coupled to a voltage source, a first transistor, and a second transistor. The system also includes a first current source coupled to the first transistor and the second transistor and configured to bias the first transistor and the second transistor. The system includes a slew detector coupled to the voltage source and to the first current source, where the slew detector is configured to detect a change in voltage of the voltage source, and further configured to provide current to the first current source responsive to detecting the change. The system also includes a second current source coupled in parallel to the first current source, where the second current source is configured to provide current to the first current source responsive to a control signal.

Abstract: A superconducting AC switch system includes a switch network configuration comprising a Josephson junction (JJ) coupled to a transmission line having a transmission line impedance, and a magnetic field generator that is configured to switch from inducing a magnetic field in a plane of the JJ, and providing no magnetic field in the plane of the JJ. An AC input signal applied at an input of the switch network configuration is passed through to an output of the switch network configuration in a first magnetic state, and substantially reflected back to the input of the switch network configuration in a second magnetic state. The first magnetic state is one of inducing and not inducing a magnetic field in a plane of the JJ, and the second magnetic state is the other of inducing and not inducing a magnetic field in a plane of the JJ.

Abstract: A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.

Abstract: A voltage converter includes a capacitive voltage conversion circuit, an output capacitor, an inductor, a current detector, and a controller. The capacitive voltage conversion circuit includes switches, at least one flying capacitor, and an intermediate capacitor at an output portion. The current detector detects a current flowing in the inductor. The controller controls the switches in the capacitive voltage conversion circuit to change between at least two states by comparing the current flowing in the inductor to a threshold current.

Abstract: Systems and methods for a tunable impedance are provided. A tunable impedance includes a transistor assembly having two terminals and a control input. The transistor assembly includes one or more transistors electrically connected between the two terminals to provide a first impedance between the two terminals, based upon a control signal. One or more replica transistors react to the control signal in a similar fashion as the transistor assembly, to provide a replica impedance based upon the control signal. A control circuit is configured to generate the control signal based upon a voltage across the replica transistor(s) and/or a current through the replica transistor(s).

Abstract: A voltage detection circuit and a charge pump circuit using the voltage detection circuit are provided. The voltage detection circuit includes: a voltage raising circuit configured to adjust a voltage to be measured and then output an adjusted voltage, where the adjusted voltage is equal to the sum of the voltage to be measured and a reference voltage; and the reference voltage is generated by a combination of a first voltage with a positive temperature coefficient and a second voltage with a negative temperature coefficient.

Abstract: Techniques and apparatus for current-based transitioning between a buck converter mode and a charge pump mode in an adaptive combination power supply circuit. One example power supply circuit generally includes a switching regulator and control logic coupled to the switching regulator. The control logic is generally configured to compare an indication of a current associated with the switching regulator to a threshold and to control a transition of the switching regulator between a buck converter mode and a charge pump mode based on the comparison.

Abstract: A data synthesizer includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to latch a first data under control of a first latch clock signal. The second input circuit is configured to latch a second data under control of the first latch clock signal. A phase of the first data is the same as a phase of the second data. The output circuit is connected to the first input circuit and the second input circuit. The output circuit is configured to output the first data and the second data in sequence.

Abstract: Aspects of the subject disclosure may include, for example, obtaining, by a first circuit of a charge pump circuit, charge sourced from a power supply operative at a first voltage level, wherein the first circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors is rated for operation at an applied voltage that is less than the first voltage level, storing the charge in a first capacitor of the first circuit at a first point in time, and transferring the charge stored in the first capacitor to a second capacitor of a second circuit of the charge pump circuit at a second point in time such that the second capacitor stores the charge, wherein the second point in time is subsequent to the first point in time. Other embodiments are disclosed.

Abstract: In a DC pulse power supply device according to the present invention, at the time of starting pulsing operation, the duty of the pulsing operation of a chopper circuit is controlled, a switching element is set to an ON state, and the pulse width at which the DC reactor is in an energized state is made variable over the period until the capacitor voltage is charged to a sufficient voltage to reset the magnetic saturation of the DC reactor. Gradually increasing the pulse width suppresses the degree of increase in the DC reactor current, and suppresses the DC reactor current below the magnetic saturazion level. As a result, the magnetic saturation of the DC reactor is suppressed at the time of starting pulsing operation.

Abstract: A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. Each level shifter is configured to output a corresponding phase clock signal of the first set of phase clock signals. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to at least one of a first or second phase clock signal of the first set of phase clock signals or a set of control signals. The first clock output signal has a second duty cycle. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle based on an input duty cycle, and generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.

Abstract: A method includes configuring a switched capacitor converter to operate in a switching mode and configuring the switched capacitor converter to enter into a bypass mode after applying a charging mode to the switched capacitor converter, wherein as a result of applying the charging mode, the switched capacitor converter has a smooth transition from the switching mode to the bypass mode.