Abstract: A method of using Josephson Junctions to convert the envelope of radio-frequency signals into baseband control pulses includes injecting a biasing current into an envelope detector circuit. The biasing current is identified based on first and second critical currents of superconducting devices in the envelope detector circuit. The first critical current corresponds to the envelope detector circuit receiving no RF signals. The second critical current corresponds to the envelope detector circuit receiving maximum RF signals. The method further includes receiving a modulated radio frequency (RF) signal at the envelope detector circuit to detect an envelope of the received RF signal. The output of the envelope detector circuit is used to drive an output load. The output is generated based on the detected envelope by the envelope detector circuit.

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

Abstract: A direct current electric circuit interrupting switch assembly is disclosed that comprises a pyroswitch assembly, which comprises at least two pyroswitches, which are connected in parallel with each other and are each per se integrated in its respective electrically conductive branch together forming a second branch of the primary electric conductor the switch assembly, with a first, preceding pyroswitch and a second, subsequent, or last pyroswitch. Each of said pyroswitches comprises an interrupting member, by means of which each circuit with each of the pyroswitches is either connected during normal operation or is interrupted by displacing each corresponding interrupting member into another position, when a pre-determined condition is met.

Abstract: A semiconductor device of the present invention includes: a P-type output transistor configured to have a source to which a power supply voltage is applied, and a drain connected to an external connection pad; a gate wiring configured to be connected to a gate of the output transistor; a signal transmitting portion configured to transmit an input signal to the gate wiring; and a voltage-breakdown protecting portion configured to apply the power supply voltage to a back gate of the output transistor if a voltage on the external connection pad is equal to or lower than the power supply voltage, or the voltage-breakdown protecting portion bringing the signal transmitting portion into a disconnection state and applies the voltage on the external connection pad to the gate and the back gate of the output transistor if the voltage applied on the external connection pad is higher than the power supply voltage.

Abstract: A charge pump apparatus includes a first charge pump system, a second charge pump system, a switch transistor, and a voltage regulation circuit. The first charge pump system converts a first supply voltage into a first boost voltage. The second charge pump system converts a second supply voltage into a second boost voltage. The switch transistor is coupled to the first charge pump system and the second charge pump system, and outputs an output voltage according to the second boost voltage. The switch transistor includes a control terminal receiving the second boost voltage, a first terminal receiving the first boost voltage, and a second terminal outputting the output voltage. The voltage regulation circuit successively adjusts a code of a voltage regulation signal according to the output voltage, in order to control the second charge pump system to successively adjust the second boost voltage according to the voltage regulation signal.

Abstract: A circuit device includes a first power supply line to which a first power supply voltage is supplied, a second power supply line to which a second power supply voltage is supplied, a third power supply line, a power supply circuit, a predetermined circuit, a first power-on reset circuit, a second power-on reset circuit, and a reset control circuit. When a first power-on reset signal and a second power-on reset signal become a reset release level, the reset control circuit sets a third power-on reset signal output to at least a part of the predetermined circuit to a reset release level.

Abstract: A semiconductor device that normally-off drives a first transistor that normally-on drives, the semiconductor device includes a first circuitry, a second circuitry, and a first diode. The first circuitry that is connected with a power supply voltage and a ground voltage, detects the power supply voltage, and outputs a transition state of the power supply voltage. The second circuitry that is connected with the power supply voltage, the ground voltage, the first circuitry, and a second transistor, and outputs a drive voltage of a second transistor connected in series with the first transistor, based on an output of the first circuitry. The first diode having an anode connected with a drive terminal of the first transistor and a cathode connected with an output terminal of the second transistor.

Abstract: An integrated driver applied to a voltage converter having a switched capacitor conversion circuit, the integrated driver including: a first die having a first-type power transistor; a second die including at least one second-type power transistor, where a withstand voltage of the first-type power transistor is higher than a withstand voltage of the second-type power transistor; and where the first die and the second die are coupled in series between a high potential terminal and a low potential terminal of the voltage converter, such that the first-type power transistor receives a high voltage signal.

Abstract: Provided is a gate controller having a primary signal input which is AC coupled to the gate through a capacitor, one or more bias inputs each connected to the gate through a resistor such as to control the DC voltage bias of the gate and therefore the conductivity of the switching element. The bias inputs can be properly connected to internal nodes of the charge pump, or charge pump stages, such that the gate controller is self-biased, without using bias-reference external to the charge pump. The gate controller can be made programmable by using potentiometers in place of the bias resistors. The programmable gate controller stages can be connected to form a programmable gate controlled charge pump.

Abstract: A hybrid charge pump is disclosed that employs novel arrangements of depletion-mode n-channel semiconductor devices and enhancement-mode p-channel semiconductor devices that eliminate or otherwise substantially reduce voltage drops that would otherwise occur across semiconductor device arrangements in existing charge pumps. As a result, the hybrid charge pump disclosed herein achieves the same output voltages as conventional charge pumps while requiring a reduced physical die area. Additionally, a hybrid charge pump arrangement disclosed herein employs a novel clocking scheme that reduces or eliminates reverse currents in the hybrid charge pump arrangement.

Abstract: The present invention provides a circuit for controlling a voltage for driving liquid lens including a first voltage generator for outputting a first voltage; a second voltage generator for outputting a second voltage having an opposite polarity to the first voltage; a first switch for selecting one of the first voltage and a ground voltage, and transmitting the selected voltage; a second switch for selecting one of the second voltage and the ground voltage, and transmitting the selected voltage; and a third switch for selecting one of a voltage selected by the first switch and the voltage selected by the second switch, and transmitting the selected voltage, wherein the third switches is plural in number, and the first switch is connected in common to the plurality of third switches.

Abstract: Aspects of the invention include receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit includes a main path including a main multiplexer (MUX) having a first input and a main driver circuit, a replica path including a replica MUX having a second input and a replica driver circuit, a selection MUX connected to the main path and the replica path, operating the selection MUX, during a period for the chip initialization, to select the main path as an input to the selection MUX, inputting a pre-defined data pattern to the main path, comparing an output of the selection MUX with the pre-defined data pattern to determine duty cycle issue, and generating an adjustment vector based on the determined duty cycle issue.

Abstract: The present invention belongs to the technical field of aviation electrics and electric power, and provides an aircraft grid phase angle tracker based on nonlinear active disturbance rejection, which is used to estimate the grid phase angle on AC side of an aircraft grid. A embedded generator in the aircraft grid is arranged inside a compressor of an aviation gas turbine engine, and the embedded generator is directly coupled with the aviation gas turbine engine so that the AC frequency of the embedded generator varies with the speed of the aviation gas turbine engine. The present invention applies the nonlinear active disturbance rejection technology to the phase angle tracking of the more electric aircraft grid, is simple in operation and high in accuracy, and can realize high-accuracy tracking of the grid phase angle. The method has certain extensibility and can be extended to other fields.

Abstract: A pulse-based flip flop circuit includes a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving either a data signal or the scan input signal responsive to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes a direct path providing a clock signal as a direct path input to a NAND circuit; a delay path including a number of plural stages that delay the clock signal and provide a delayed clock signal as a delay path input to the NAND circuit that performs a NAND operation on the direct path and delay path inputs to generate the inverted pulse signal; and a feedback path providing the pulse signal to a first stage among the stages of the delay path.

Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.

Abstract: A system and method is disclosed, to generate an AC signal having a positive and negative half-cycles, each comprising a plurality of PWM pulses each with an individually designated pulse width, the system comprising: a first clock circuit; a second, faster, clock circuit; clock ratio measurement circuitry configured to output a first measurement being a ratio of frequencies; a propagation delay circuit configured to measure a number of propagation elements through which a bit transition propagates within a second clock signal period; pulse data calculation element configured to determine pulse shaping data; and for each of the half-cycles, a respective pulse synthesis circuit configured to synthesise the respective plurality of PWM pulses, each pulse having a respective start defined by the first clock signal, and a pulse width defined by the pulse shaping data and synthesised from the second clock and an output pulse from the propagation delay circuit.

Abstract: Provided are a circuit for generating a bias signal and a clock input circuit for applying the circuit for generating a bias signal. The circuit for generating a bias signal includes: a first subcircuit, a first terminal of the first subcircuit being connected to a power supply voltage by means of a first node, a second terminal of the first subcircuit being connected to a current stabilization circuit by means of a second node, the first subcircuit being configured to generate a bias signal and output the bias signal by means of the second node, and the current stabilization circuit being configured to provide a constant current to the second node; and a second subcircuit, two terminals of the second subcircuit being respectively connected to the first node and the second node, the second subcircuit including a first resistor element and a first switch element connected in series.

Abstract: A circuit includes first and second power nodes having differing first and second voltage levels, and a reference node having a reference voltage level. A master latch outputs a first data bit based on a received data bit; a slave latch includes a first inverter that outputs a second data bit based on the first data bit and a second inverter that outputs an output data bit based on a selected one of the first data bit or a third data bit; a level shifter outputs the third data bit based on a fourth data bit; and a retention latch outputs the fourth data bit based on the second data bit. The first and second inverters and the level shifter are coupled between the first power node and the reference node, and the retention latch includes a plurality of transistors coupled between the second power node and the reference node.

Abstract: A superconducting DC switch system is provided. The superconducting DC switch system comprises one or more Josephson junctions (JJs), and a magnetic field generator that is configured to switch from inducing a magnetic field in a plane of the one or more JJs, and providing no magnetic field in the plane of the one or more JJs. A DC input signal applied at an input of the one or more JJs is passed through to an output the one or more JJs in the absence of an induced magnetic field, and the DC input signal is substantially suppressed at the output of the one or more JJs in the presence of the magnetic field.

Abstract: One or more systems, devices and/or methods of use provided herein relate to a device that can support a signal generation. A current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. Analog inputs and outputs of the DAC and upconverting mixer can be represented as currents, and the DAC can generate a baseband signal. The DAC and upconverting mixer each can comprise switching transistors of the same type, such as p-type metal-oxide semiconductor (PMOS) switching transistors. In one or more embodiments, a current source and a diode-connected transistor can be arranged in parallel in the current-mode signal path, and the current source passes a static current, while the diode-connected transistor passes both a static current and a dynamic current.