Abstract: Regulation systems and methods use a first regulator and a tracking second regulator. The first regulator receives a reference voltage and generates a first voltage output based upon the reference voltage, which is coupled as a back-bias voltage to a first load region within the integrated circuit. The first regulator also receives a sampled version of the first voltage output as feedback. A second regulator receives the first sampled voltage output and generates a second voltage output. The second regulator also receives a sampled version of the second voltage output as feedback. During operation, the second voltage output tracks (e.g., by a symmetry ratio) the first voltage output and is coupled as a back-bias voltage to a second load region within the integrated circuit. Further, switched-capacitor operation can be implemented, and clock frequency can be adjusted based upon the first sampled voltage output to reduce power consumption.

Abstract: Embodiments of methods and systems for attenuator phase compensation are described. In an embodiment, a method for attenuator phase compensation involves determining a phase compensation value for an attenuator based on an attenuation configuration of the attenuator and performing phase compensation according to the phase compensation value to maintain a constant phase response.

Abstract: A shift register circuit, a driving method, a gate driving circuit, and a display device are provided. The shift register circuit includes a clock signal adjustment circuit and a self-control conduction circuit; the clock signal adjustment circuit includes a first clock signal input terminal, a second clock signal input terminal, and a clock signal adjustment output terminal; the clock signal adjusting circuit is configured to, in the case that the first clock signal and the second clock signal are both at a second level, output a first level via a clock signal adjustment output terminal; the self-control conduction circuit is configured to, in the case that the pull-up node is at the first level, control the clock signal adjustment output terminal connect with a pull-up node, or in the case that the pull-up node is at a second level, disconnect the clock signal adjustment output terminal from the pull-up node.

Abstract: A vector sum circuit and a phase controller including the vector sum circuit are provided. The vector sum circuit includes an amplifier configured to amplify an input orthogonal signal by using a first metal oxide semiconductor field effect transistor (MOSFET), and a self body-biasing circuit comprising a resistor. The self body-biasing circuit is configured to connect a drain and a body of the first MOSFET to reduce a voltage connected to the body as a current at the drain increases.

Abstract: A semiconductor device according to one embodiment comprises a first transistor, a second transistor, a switch, and a first control circuit. The first transistor including, one end of a current path connected to a first node, another end of the current path connected to a second node, and a gate connected to a third node. The second transistor including, one end of a current path connected to the second node, another end of the current path connected to a fourth node, and a gate connected to the third node. The switch configured to connect the second node and the third node. The first control circuit configured to control the switch.

Abstract: A lock detector (8) detects an unlocked state from an output of a phase frequency comparator (1). A counter (9) counts a reference signal, in a case where an unlocked state is detected by the lock detector (8). A parameter controlling circuit (10) acquires the count value of the counter (9), and controls switching on and off of a switch (12) for a D/A converter (11) that generates a signal to be added to an output of a loop filter (3), and the output voltage of the D/A converter (11) so that the count value of the counter (9) falls within a set value.

Abstract: A drive circuit is provided for driving a plurality of object switches mutually connected in parallel. The drive circuit includes: an off holding switch provided for each of the object switches, short-circuiting between a control terminal of each object switch and a reference potential unit to which discharge from the control terminal is discharged; and off control units each provided for the off holding switch. The off holding switch is driven by an own control unit and other control units. The own control unit is provided as an off control unit corresponding to own off holding switch, among the off control units. Other control units are at least one of the off control units other than the own control unit.

Abstract: A controllable splitting method comprises: electrically connecting a photoconductive switch between input and output ends of a current pulse; connecting a time domain signal of the input current pulse to an external triggering port of a pulse laser; emitting a laser pulse to irradiate the switch; when no current pulse is input, failing to receive an external triggering signal and not outputting the laser pulse, the switch being in an off state without the irradiation of the laser pulse, and no current being output; when the current pulse is input, triggering the pulse laser to synchronously output the laser pulse on a time domain, irradiating the switch so that the switch is in an on state and the current pulse is output; and forming, at the output end, a current pulse signal synchronous with a time domain of the input end and having a split waveform.

Abstract: A device for providing a reset signal to one or more sequential logic circuits in an electronic system responsive to a supply voltage condition includes a first voltage detector circuit to generate a first pulse after the supply voltage rises to a first threshold voltage level. The device further includes a second voltage detector circuit to generate a second pulse after the supply voltage falls below a second threshold voltage level. The device additionally includes a latch circuit to store a first value based on the first pulse after the supply voltage rises to the first threshold voltage level, disable the first voltage detector circuit after storing the first value, reset to store a second value based on the second pulse after the supply voltage falls below the second threshold voltage level, and to disable the second voltage detector circuit after the resetting.

Abstract: An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.

Abstract: Power combiners having increased output power, such as may be useful in millimeter-wave devices. The power combiner comprise at least two channels, wherein each channel comprises a phase alignment circuit, wherein the phase alignment circuit comprises a first differential input subcircuit comprising a first inverter and a second inverter, and a second differential input subcircuit comprising a third inverter and a fourth inverter, wherein the first inverter, the second inverter, the third inverter, and the fourth inverter each comprise a PMOS transistor and an NMOS transistor each having an adjustable back gate bias voltage. By adjusting the back gate bias voltage, the phases of the signal through each channel may be aligned, which may increase the output power of the power combiner. Methods of increasing output power of such power combiners. Systems for manufacturing devices comprising such power combiners.

Abstract: A phase controlled power regulation circuit is isolated from a line voltage and therefore overcomes some of the safety issues associated with currently available potentiometers. A phase controlled power regulation circuit employs a potentiometer that is electrically isolated from mains power. A transformer regulates the line voltage down to a reduced reference voltage that is used by the power regulation circuit. Any single point failure of a component within the power regulation circuit will not create unsafe condition. This greatly simplifies regulatory approval and opens new applications. Since the potentiometer is operated at low voltage, it may be remotely located from the circuits that handle the power with two conductors of class 2 wiring. Also, the potentiometer need not be of a panel mounted rotary or sliding type. It may be a potentiometer integrated circuit controllable from a microprocessor that enables complex regulation and/or sequencing control.

Abstract: Some embodiments include apparatus and methods for using a switch to couple an inductor to an energy harvester for a time interval to allow charging of the inductor during the time interval, and using a circuit to generate control information for power management. A value of the control information is based on a value of the time interval.

Abstract: Memory devices may have internal circuitry that employs voltages higher than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate, internally, higher voltages for operation. The number of available charge pumps in a memory device may be higher than the number used for certain memory operations. Gating circuitry may be used to selectively enable charge pump cores based on power demands that may be associated with a mode of operation and/or a command.

Abstract: A current comparator including a first comparator configured to generate a first output signal based on a comparison of a first current to at least a second current; a second comparator configured to generate a second output signal based on a comparison of the first current to at least a third current; and a circuit configured to: direct the first current to the first comparator to perform the comparison of the first current to the at least the second current while blocking the first current from being applied to the second comparator; or direct the first current to the second comparator to perform the comparison of the first current to the at least the third current while blocking the first current from being applied to the first comparator.

Abstract: A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.

Abstract: A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

Abstract: The present invention relates to a device for controlling a transistor, comprising: a separating assembly for generating a first voltage, a transformer for obtaining a first and second converted voltage from the first voltage, a rectifier circuit for generating a third voltage from parts of the same sign of the first converted voltage and of the opposite of the second converted voltage, a latch for generating a fourth voltage from the converted voltages, a switching assembly for multiplying the third voltage with a fourth voltage normalized in order to obtain a multiplied voltage, and a shifting circuit for shifting the multiplied amplitude in order to obtain a control voltage.

Abstract: An integrated circuit includes a voltage monitor circuit having a first input coupled to a reference voltage and a second input, a successive approximation register (SAR) circuit having an input coupled to an output of the voltage monitor circuit, a low drop out (LDO) regulator having an input coupled to an output of the SAR circuit and an output coupled to the second input, a discharge circuit coupled to the LDO output, voltage sensing circuit having a first input coupled to the reference voltage during a trim mode and coupled to the LDO output during a monitor mode, having a second input coupled to the reference voltage, and an output which asserts a sense indicator that indicates when a voltage at the first input goes higher or lower than the reference voltage by a predetermined amount. Control circuitry is configured to, during trim mode, periodically discharge the LDO output voltage.

Abstract: A driving apparatus is provided, the driving apparatus including: a gate driving unit that drives a semiconductor element; a sampling unit that samples, in an on-period of the semiconductor element, an observation value that changes according to an on-current flowing through the semiconductor element; and a changing unit that changes a driving condition under which the gate driving unit drives a gate of the semiconductor element when the semiconductor element is turned off according to the observation value sampled in an on-period of the semiconductor element.