Abstract: Improved clock gating cells and related methods are provided. The clock gating cells include a first mutually exclusive element (ME1), a first inverter and a second mutually exclusive element (ME2). ME1 receives a clock input and an enable signal, which is asynchronous to the clock input, and outputs the enable signal based on a timing relationship between the clock input and the enable signal. The first inverter receives the enable signal output from ME1 and provides an inverted enable signal to ME2. ME2 receives the clock input and the inverted enable signal, and provides a clock output based on a timing relationship between the clock input and the inverted enable signal. Together, ME1 and ME2 resolve meta-stability and eliminate glitches in the clock output by preventing rising and falling edges of the enable signal from passing through the mutually exclusive elements during active phases of the clock input.

Abstract: A driving apparatus including: gate driving circuit to drive gates of a first semiconductor element and a second semiconductor element connected in series between a positive side power supply line and a negative side power supply line; a first timing generating circuit to generate a first timing signal when voltage applied to the second semiconductor element becomes reference voltage during a turn-off period of the first semiconductor element; and a first driving condition change circuit, wherein the gate driving circuit relaxes change in a charge amount of the gate of the first semiconductor element, according to the first timing signal.

Abstract: Disclosed is a phase-locked loop which alternately operates in a sleep state and an active state. A frequency-divided output signal of the phase-locked loop is synchronized with a frequency-divided reference signal. When the phase-locked loop switches from a sleep state to an active state, a frequency of the frequency-divided output signal is identical to a frequency of a frequency-divided output signal which has been synchronized in a previous active state. Information corresponding to the frequency of the frequency-divided output signal which has been synchronized in the previous active state is stored in a memory device.

Abstract: A gate-charge harvester includes a harvest capacitor that has a first plate and a second plate. The second plate is coupled to a lower rail and the first plate is coupled to send a voltage towards a regulator. The gate-charge harvester also includes a low-side harvest transistor having a first terminal coupled to a gate of a low-side power transistor and a second terminal coupled to the first plate.

Abstract: A method for detecting a plurality of useful signals in a total signal. The useful signals correspond to radiofrequency signals emitted by different terminals in a multiplexing frequency band. A plurality of spectrograms calculated that have a compensated linear frequency drift and are respectively associated with different linear frequency drift values. For each analysis frequency and each spectrogram, time envelope filtering of the values is performed at the different times for analyzing the spectrogram at the analysis frequency using a filter representing a reference time envelope of the useful signals. A useful signal is detected at an analysis time and at an analysis frequency in response to a verification of a predefined detection criterion by the value from a spectrogram resulting from filtering at the analysis time and at the analysis frequency.

Abstract: An electronic device comprises a regulator, and an oscillator and a resistor coupled to the regulator. The electronic device further comprises a feedback controller that includes a differential amplifier coupled between the oscillator, the resistor, and the regulator. The feedback controller is configured to apply a control voltage to the regulator in response to a resistor voltage upon the resistor and an oscillator voltage upon the oscillator. The feedback controller can be coupled to control a substantially equal voltage upon the resistor and the oscillator.

Abstract: High power radio frequency (RF) switches with low leakage current and low insertion loss are provided. In one embodiment, an RF switch includes a plurality of transistors and is configured to selectively connect one of a transmit path or a receive path to an antenna. All of the transistors are configured to be in an on state when the RF switch operates in a high power mode and all of the transistors are configured to be in an off state when the RF switch operates in a low power mode.

Abstract: The elementary pumping cell comprises an input (E) receiving an input voltage (Vin), a clock terminal (H) receiving a first clock signal (CK1) and an output (S), a first capacitor (C1) having a first terminal connected to the clock terminal and a second terminal, a first transistor (A1) having a first source/drain terminal coupled to the input, a second source/drain terminal and a gate terminal, a second transistor (A2) having a first source/drain terminal, a second source/drain terminal coupled to the input and a gate terminal coupled to the second terminal of the first capacitor, a third transistor (A3) having a first source/drain terminal coupled to the first source/drain terminal of the second transistor, a second source/drain terminal coupled to the gate terminal of the second transistor and a gate terminal coupled to the input, and a fourth transistor (A4) having a first source/drain terminal coupled to the second source/drain terminal of the first transistor, a second source/drain terminal coupled to t

Abstract: A device may include an integrated circuit and a jitter generator located on the integrated circuit. The jitter generator may include a random number generator to generate a random number in response to a clock input signal. The jitter generator may also include delay-causing circuitry to receive the clock input signal, where the delay-causing circuitry may create a delayed clock input signal. The jitter generator may also include a phase mixer to receive the random number, the delayed clock input signal, and the clock input signal, where the phase mixer additionally outputs a clock output signal having the clock input signal and having jitter.

Abstract: A clock circuit includes a set of level shifters, and adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle, and is coupled to the adjustment circuit. The adjustment circuit is configured to generate a first clock output signal responsive to a first phase clock signal and a second phase clock signal of the first set of phase clock signals, and adjust the first clock output signal and a second duty cycle of the first clock output signal responsive to a set of control signals. The calibration circuit is coupled to the adjustment circuit, and configured to perform a duty cycle calibration of the second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration.

Abstract: Provided is a low-power-consumption Constant-On-Time (COT) timing circuit design method and a timing circuit. A Resistor-Capacitor (RC) circuit is adopted for timing, to eliminate static power consumption of a timer. A specific structure includes a fourth P-channel Metal Oxide Semiconductor (MOS) transistor M4 of which a source is connected to an input voltage VIN, a gate is connected to a COT control terminal TON_CONTROL and a drain is connected with one end of a fourth resistor R4. The other end of the fourth resistor R4 is connected with one end of a fourth capacitor C4. The other end of the fourth capacitor C4 is grounded. A negative input of a comparator VCMP is connected with a reference voltage, and a positive input is connected between the fourth capacitor C4 and the fourth resistor R4.

Abstract: A Phase-locked loop circuit including: a local oscillator, configured to generate a timing signal; a variable-length shift register, controlled by the timing signal; and a feedback control circuit, which receives a pulsed input signal and receives a local signal from the shift register. The feedback control circuit detects whether each pulse of the input signal respects a condition of temporal proximity with a corresponding pulse of the local signal and detects, for each pulse of the input signal that respects the proximity condition, whether the edge falls early, late, or within a predefined portion of the corresponding pulse of the local signal. The feedback control circuit controls the length of the shift register and the frequency of the timing signal, as a function of the detections made.

Abstract: A switching element control circuit is configured to perform a measurement mode in which a threshold voltage of a switching element is measured and a control mode in which an ON/OFF operation of the switching element is controlled in a switching manner. The switching element control circuit includes: a threshold voltage measurement power source; a third electrode voltage control part; an ON/OFF state determination part; and a memory part which stores the third electrode voltage applied to the third electrode as a threshold voltage of the switching element. The third electrode voltage control part controls, in the control mode, the third electrode voltage based on information including the threshold voltage stored in the memory part at the time of bringing the switching element into an ON state.

Abstract: A sensing circuit for sensing an analog signal includes a level shifter that shifts the analog signal from a high voltage domain to a low voltage domain. The signal originates from the high voltage domain, and is passed to the low voltage domain through the level shifter. A source line provides the analog signal, which can be selectively switched into a sense amplifier circuit. The sense amplifier is in the low voltage domain and generates a digital output to represent the sensed analog signal.

Abstract: A driver circuit for driving, for example, ultrasonic transducers in medical equipment, such as ultrasound scanning equipment. The driver circuit includes first inputs receptive of a pulsed signal, second inputs receptive of an analog signal, an output for applying a pulsed drive signal or an analog drive signal to a load. A pair of output transistors of complementary polarities are positioned with their current paths in series between opposing supply lines with a connection point intermediate between the transistors of the pair of transistors. The connection point between output transistors is coupled to the output of the circuit. The control terminals of the output transistors, which are coupled together, may be coupled to the first inputs with the driver functioning as a pulser, or else coupled to the second inputs with the driver functioning as a linear driver.

Abstract: A controlled active resistance. The active resistance is implemented on an integrated circuit. In some embodiments, the active resistance includes a MOSFET. In alternate embodiments, the active resistance includes a MOSFET and a resistor. The control for the active resistance includes a reference resistor and an operational amplifier. The control for the active resistance further includes two current sources: i) a current source producing a current that is proportional to absolute temperature, and ii) another current source that is produced by a bandgap voltage reference. In one aspect, the active resistance generates an effective resistance that is proportional to thermal voltage. In another aspect, the active resistance generates an effective resistance that is proportional to inverse of the thermal voltage. In an alternate aspect, the current sources have various dependencies, and the active resistance generates an effective resistance that is proportional to those dependencies.

Abstract: A power adaptor includes a power input interface, a communication protocol chip, a voltage conversion chip and a power output interface; a first detection terminal of the communication protocol chip is connected to the power input interface, a second detection terminal of the communication protocol chip is connected to the power output interface, a control terminal of the communication protocol chip is connected to the voltage conversion chip; and an input terminal of the voltage conversion chip is connected to the power input interface, and an output terminal of the voltage conversion chip is connected to the power output interface.

Abstract: In one embodiment, a control circuit for a high side driver forms alternate signals to control a store mode and a maintain mode. An embodiment of the control circuit stores a voltage that is greater than an input voltage which results in storing a large charge for at least a portion of one of the cycles. The charge is used to supply operating voltage to the driver for at least a portion of another of the cycles.

Abstract: A wide supply range digital level shifter circuit shifts between a variable desired output voltage ranging from a first voltage level and a second voltage level. The wide supply range digital level shifter circuit includes a latch circuit, a first bleeder circuit, and a second bleeder circuit. The latch circuit receives the first voltage level and the second voltage level, and includes first and second clocked differential switches. The first bleeder circuit is connected between the second voltage rail and the first differential switch and is configured to receive a first digital input voltage. The second bleeder circuit is connected between the second voltage rail and the second differential switch and is configured to receive a second digital input voltage. The first and second bleeder circuits isolate the first and second digital input voltages from the variable desired output voltage.

Abstract: In some embodiments, a threshold calibration system to provide a zero voltage switching signal is presented. The system includes a divider coupled to a switching node; a calibration ramp generator; a reference voltage generator; a comparator; a first multiplexer coupled to receive a divider output signal from the divider and a calibration ramp signal from the calibration ramp generator and provide a signal to the comparator based on a calibration enable signal; a second multiplexer coupled to receive reference voltages from the reference voltage generator, the second multiplexer provided a threshold signal to the comparator; and a digital feedback circuit receiving an output signal from the comparator and providing the zero voltage switching signal.