Abstract: A drive circuit includes: a control section generating a control signal; a first level shift section raising a level of a signal from the control section; a high side drive section controlling a semiconductor device; and a second level shift section lowering a level of a signal from the high side drive section for input to the control section. The high side drive section has an error detection section maintaining an output of an error detection signal when the semiconductor device is in an error status until a release signal is input, the control section has an error handling section outputting the release signal to the high side drive section via the first level shift section when the error detection signal is input via the second level shift section, and the error detection section stops the output of the error detection signal when the release signal is input.

Abstract: An object of the present technology is to stably operate a power supply circuit. A charge switch is connected to a first terminal of a capacitor and charges the capacitor with an input voltage on the basis of a control signal inputted to a control terminal. A discharge switch is complementary with the charge switch, is connected to the first terminal of the capacitor, and discharges on the basis of the control signal inputted to the control terminal the voltage charged to the capacitor, thereby generating an output voltage. A charge control signal converting section converts a charge control signal that controls the charge into a control signal referenced to the input voltage and inputs the resulting control signal to the control terminal of the charge switch. A discharge control signal converting section converts a discharge control signal that controls the discharge into a control signal referenced to the output voltage and inputs the resulting control signal to the control terminal of the discharge switch.

Abstract: A device for limiting a power loss during the sampling of a digital signal is illustrated. The device comprises a circuit disposed in the signal path of the digital signal, the circuit being configured to reduce a current flow along the signal path in response to a control signal which indicates a sampling pause.

Abstract: In a level shifter circuit that transmits a set signal and a reset signal input to input terminals of a high-side latch circuit, the source sides of high voltage transistors are connected to current negative feedback resistors, and transistors are connected in parallel to the current negative feedback resistors. Further included is a high-side voltage detection circuit that detects whether the voltage of a high-side power supply terminal is a high voltage. When a high voltage is detected, the transistors are turned OFF to make the drain currents that flow smaller, thereby making it possible to improve the trade-off between heat generation and propagation delay characteristics in the high voltage transistors.

Abstract: A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.

Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.

Abstract: Power combiners having increased output power, such as may be useful in millimeter-wave devices. The power combiner comprise at least two channels, wherein each channel comprises a phase alignment circuit, wherein the phase alignment circuit comprises a first differential input subcircuit comprising a first inverter and a second inverter, and a second differential input subcircuit comprising a third inverter and a fourth inverter, wherein the first inverter, the second inverter, the third inverter, and the fourth inverter each comprise a PMOS transistor and an NMOS transistor each having an adjustable back gate bias voltage. By adjusting the back gate bias voltage, the phases of the signal through each channel may be aligned, which may increase the output power of the power combiner. Methods of increasing output power of such power combiners. Systems for manufacturing devices comprising such power combiners.

Abstract: Provided are a latch circuit and a flip-flop circuit each having more excellent tolerance to single event upset (SEU). The single event upset (SEU)-tolerant latch circuit of the present invention is configured such that three transistors for redundancy are added to each of eight transistors constituting a conventional DICE latch circuit, at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel, and each of a first data input part and a second data input part is also made dually redundant.

Abstract: Systems and methods for a tunable impedance are provided. A tunable impedance includes a transistor assembly having two terminals and a control input. The transistor assembly includes one or more transistors electrically connected between the two terminals to provide a first impedance between the two terminals, based upon a control signal. One or more replica transistors react to the control signal in a similar fashion as the transistor assembly, to provide a replica impedance based upon the control signal. A control circuit is configured to generate the control signal based upon a voltage across the replica transistor(s) and/or a current through the replica transistor(s).

Abstract: One example includes a phase-locked loop (PLL) circuit. The circuit includes a frequency divider and phase detector configured to generate a plurality of non-overlapping switching signals based on an input signal and a PLL output signal. The circuit also includes a linear frequency-to-current (F2I) converter configured to generate a control current having an amplitude that is based on the plurality of non-overlapping switching signals. The circuit further includes a linear current-controlled oscillator configured to generate the PLL output signal to have a frequency and phase to be approximately equal to the input signal based on the amplitude of the control current.

Abstract: Embodiments describe a battery system that includes a first battery module coupled to a regenerative braking system and a control module that controls operation of the battery system by: determining a predicted driving pattern over a prediction horizon using a driving pattern recognition model based in part on a battery current and a previous driving pattern; determining a predicted battery resistance of the first battery module over the prediction horizon using a recursive battery model based in part on the predicted driving pattern, the battery current, a present bus voltage, and a previous bus voltage; determining a target trajectory of a battery temperature of the first battery module over a control horizon using an objective function; and controlling magnitude and duration of electrical power supplied from the regenerative such that a predicted trajectory of the battery temperature is guided toward the target trajectory of the battery temperature during the control horizon.

Abstract: Several embodiments of electrical circuit devices and systems with a duty cycle correction apparatus that includes a duty cycle adjustment circuit that is configured to adjust a duty cycle of the input clock signal based on an averaged code value. The duty cycle correction apparatus includes a duty cycle detector circuit that receives first and second clock signals from a clock distribution network. The duty cycle detector is configured to output a duty cycle status signal that indicates whether the first clock signal is above or below a 50% duty cycle based on a comparison of the first clock signal to the second clock signal. The duty cycle correction apparatus also includes a counter logic circuit configured to determine the average code value, and the counter logic circuit automatically cancels an offset of the duty cycle detector when determining the averaged code value.

Abstract: A circuit includes a slave latch including a first input and an output, the first input being coupled to a master latch, and a retention latch including a second input coupled to the output. The master latch and the slave latch are configured to operate in a first power domain having a first power supply voltage level, the retention latch is configured to operate in a second power domain having a second power supply voltage level different from the first power supply voltage level, and the circuit further includes a level shifter configured to shift a signal level from one of the first power supply voltage level or the second power supply voltage level to the other of the first power supply voltage level or the second power supply voltage level.

Abstract: The control system according to embodiments includes a switching element, a control unit controlling the conductive state of the switching element, and a first capacitor storing charge supplied to the control unit. The first capacitor and the control unit are connected with each other via the switching element.

Abstract: A flip-flop circuit is disclosed. The flip-flop circuit includes a single-input inverter, a dual-input inverter, a single-input tri-state inverter, a dual-input tri-state inverter, and two single-event transient (SET) filters. The single-input tri-state inverter receives an input signal D. The dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the dual-input inverter and the second input receives output signals from the dual-input inverter via the first SET filter. The output of the dual-input tri-state inverter sends output signals to a first input of the dual-input inverter and a second input of the dual-input inverter via the second SET filter. The single-input inverter receives inputs from the dual-input inverter to provide an output signal Q for the flip-flop circuit.

Abstract: A true random number generator based on a voltage-controlled oscillator includes a thermal noise generator, a ring oscillator, a voltage-controlled oscillator, a D flip-flop, and a post-processing circuit. The D flip-flop has a clock terminal, an input terminal, and an output terminal. An output terminal of the thermal noise generator is connected with an input terminal of the voltage-controlled oscillator. An output terminal of the voltage-controlled oscillator is connected with the clock terminal of the D flip-flop. An output terminal of the ring oscillator is connected with the input terminal of the D flip-flop. The output terminal of the D flip-flop is connected with an input terminal of the post-processing circuit. An input terminal of the thermal noise generator is connected with a reference level. The thermal noise generator includes a digital-analog converter, an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor.

Abstract: A low-power-consumption high-speed zero-current switch includes a delay controller, a driving stage and a power transistor MN, wherein: an input of the delay controller is connected with an external clock CLK, an output of the delay controller is connected with an input of the driving stage, and an output of the driving stage is connected with a gate of the power transistor MN; the delay controller includes a gate signal generator, a sampling circuit and a current controller, and three of which form a negative feedback loop for stabilizing the turn-on voltage VON and the turn-off voltage VD to 0, so that when the power transistor MN is turned on or off, the source-drain voltage thereof is 0. The present invention no longer uses a high-power-consumption high-speed comparator, but uses a low-power-consumption delay controller to generate turn-on and turn-off signals of the power transistor.

Abstract: A semiconductor device includes a transmission circuit coupled between a first voltage supply node and a second voltage supply node, and suitable for outputting an output data signal corresponding to a data value to an output terminal during a data output enable period, and a switching circuit coupled between the first and second voltage supply nodes, and suitable for providing a current path between the first and second voltage supply nodes during a data output disable period.

Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. As example apparatus includes a power supply line configured to provide a supply voltage and further includes first and second nodes. An impedance element is coupled between the power supply line and the first node and a first transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. A reference line is configured to provide a reference voltage. A second transistor has a gate, a source coupled to the reference line, and a drain. The gate and the drain of the second transistor are coupled to the gate of the first transistor.

Abstract: A method includes generating a filtered phase difference signal based on a reference clock signal and a feedback clock signal. The method includes generating a first output clock signal based on a first divider control signal and an input clock signal. The feedback clock signal is based on the first output clock signal. The method includes generating a first time code based on a counter signal and a first update of the first output clock signal in response to an update of the filtered phase difference signal to a first value from a second value. The second output clock signal is based on a second divider control signal, the input clock signal, and an error correction signal generated based on the first value, the second value, the first time code, and the second time code. The first and second divider control signals are based on the filtered phase difference signal.