Abstract: A method and an apparatus for reading cache data, and a storage medium are provided. The method includes: receiving a read instruction; converting at least one type of address offset position corresponding to the read instruction into a coupled address offset position according to a preset rule; performing a matching operation in a data group according to the coupled address offset position which corresponds to the at least one type of address offset position and obtaining corresponding cache data; reading the cache data obtained through matching. This method is able to simultaneously perform matching operations and reading operations for at least two combined address offset positions, thereby greatly improving data reading efficiency and doubling cache data reading throughput without significantly increasing hardware logic. Furthermore, this configuration is applicable to read-only cache, read-write cache, and write-only cache, possessing great versatility.

Abstract: An apparatus is described having processing circuitry for performing operations during which access requests to memory are generated. The processing circuitry generates memory addresses for the access requests using capabilities, where each capability indicates a pointer value and constraining information used to constrain access to memory using memory addresses derived from the pointer value. A marker indication field is stored in association with each capability to provide a marker value used to distinguish between static capabilities used to access statically allocated memory and dynamic capabilities used to access dynamically allocated memory.

Abstract: A method for safe storage of a data portion, the method includes (a) receiving, at a storage system, the data portion; (b) selecting, based on at least a timing parameter, a redundancy scheme for safe storage of the data portion; wherein the redundancy scheme is selected out of (i) mirroring the data portion and (ii) applying a stripe based protection on the data portion, at a storage space of the storage system; and (c) safe storing the data portion by applying the selected redundancy scheme.

Abstract: A memory buffer device facilitates secure read and write operations associated with data that includes a predefined data pattern. For read operations, the memory buffer device detects a read data pattern in the read data that matches a predefined data pattern. The memory buffer device may then generate a read response that includes metadata identifying the read data pattern without sending the read data itself. The memory buffer device may also receive Write Request without Data (RwoD) commands from the host that include metadata identifying a write data pattern. The memory buffer device identifies the associated data pattern and writes the data pattern or the metadata to the memory array. The memory buffer device may include encryption and decryption logic for communicating the metadata in encrypted form.

Abstract: Disclosed is an electronic device including a processor configured to receive a command requesting an operation for a plurality of group zones from a host, transmit a completion response to the command to the host, and perform a background operation for the command; and a plurality of storage devices, the processor configured to control the plurality of storage devices, each of the plurality of group zones including a plurality of zones included in one or more storage devices among the plurality of storage devices, and the processor being configured to perform the background operation including generating a plurality of distribution commands for each of the plurality of storage devices from the command, and issuing one or more distribution commands among the plurality of distribution commands to one or more storage devices corresponding to the one or more distribution commands, respectively.

Abstract: A method and system for building a block data transfer (BT) DRAM provides a solution to fix the performance gap between memory and processor. The data conversion time per word between the analog circuits and the digital circuits inside the BT DRAM is smaller than the processor clock cycle time, that enables the average data transfer speed of a BT DRAM to match to the operation speed of a processor. When continuously transferring a plurality of data blocks, a BT DRAM can achieve a close-to-zero-latency performance and is completely self-refreshing.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support enhanced exclusive read and write operations and scalable exclusive monitor architectures. In one aspect, device includes a processing system that includes one or more shared memory devices and one or more request nodes. The processing system also includes one or more network interface units (NIUs), each NIU of the one or more NIUs including an exclusive monitor configured to monitor exclusive accesses to shared memory addresses for a corresponding request node. The processing system includes one or more home nodes coupled to a corresponding shared memory device of the one or more shared memory devices. The processing system further includes an interconnect coupled to each NIU and to each home node and configured to couple the one or more request nodes to the one or more shared memory devices. Other aspects and features are also claimed and described.

Abstract: A system may include a non-volatile memory (NVM), a first memory, a second memory that has a higher speed than the first memory, and a controller. The controller may be configured to receive a first read command from a host computer, and determine a size of one or more buffers that are allocated for one or more read commands that have been received and not returned read data to the host computer. The controller may be configured to determine a number of the one or more read commands, and determine, based on at least the size of the one or more buffers and the number of the one or more read commands, whether to start processing the first read command. In response to determining to start processing the first read command, the controller may be configured to allocate, in the first memory, a first buffer for the first read command.

Abstract: A memory expander includes a memory device that stores a plurality of task data. A controller controls the memory device. The controller receives metadata and a management request from an external central processing unit (CPU) through a compute express link (CXL) interface and operates in a management mode in response to the management request. In the management mode, the controller receives a read request and a first address from an accelerator through the CXL interface and transmits one of the plurality of task data to the accelerator based on the metadata in response to the read request.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive die selection for block family scan operations. The controller assigns a set of memory components to one or more groups of a plurality of groups based on respective storage characteristics of the set of memory components, each of the plurality of groups corresponding to different storage characteristics. The controller determines a maximum quantity of memory components to perform block family (BF) scan operations at an individual measurement period. The controller distributes the maximum quantity of memory components across the one or more groups to which the set of memory components are assigned and, at the individual measurement period, performs the BF scan operations on a portion of the set of memory components corresponding to the maximum quantity of memory components.

Abstract: An apparatus has address translation circuitry to translate a target virtual address (VA) specified by a memory access request into a target physical address, first/second translation table address storage circuitry to store first/second translation table addresses; and protected region defining data storage circuitry to store region defining data specifying at least one protected region of virtual address space. In response to the memory access request: when the target VA is in the protected region(s), the address translation circuitry translates the target VA based on address translation data from a first translation table structure identified by the first translation table address. When the target VA is outside the protected region(s), the target VA is translated based on address translation data from a second translation table structure identified by the second translation table address.

Abstract: A resource eviction method, an electronic device and a readable storage medium, which relate to the field of artificial intelligence technologies, such as cloud service technologies, big data technologies, or the like, are disclosed. The resource eviction method includes: acquiring an access day number of at least one target resource in a current cache period, and acquiring an access frequency of the at least one target resource according to the access day number and a preset time interval; acquiring a time heat factor corresponding to the current cache period, and acquiring resource heat of the at least one target resource according to the access frequency and the time heat factor; acquiring target heat according to the time heat factor; and evicting the target resource with the resource heat smaller than or equal to the target heat, updating the time heat factor according to a preset update value, and taking the updated time heat factor as a time heat factor corresponding to a next cache period.

Abstract: A memory module may include one or more memory devices, and a near-memory computing module coupled to the one or more memory devices, the near-memory computing module including one or more processing elements configured to process data from the one or more memory devices, and a memory controller configured to coordinate access of the one or more memory devices from a host and the one or more processing elements. A method of processing a dataset may include distributing a first portion of the dataset to a first memory module, distributing a second portion of the dataset to a second memory module, constructing a first local data structure at the first memory module based on the first portion of the dataset, constructing a second local data structure at the second memory module based on the second portion of the dataset, and merging the first and second local data structures.

Abstract: Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system. The processor-based system is configured to receive a cache allocation request to allocate a line in a share cache structure, which may further include a client identification (ID). The cache allocation request and the client ID can be compared to a sub-non-uniform memory access (NUMA) (sub-NUMA) bit mask and a client allocation bit mask to generate a cache allocation vector. The sub-NUMA bit mask may have been programmed to indicate that processing cores associated with a sub-NUMA region are available, whereas processing cores associated with other sub-NUMA regions are not available, and the client allocation bit mask may have been programmed to indicate that processing cores are available.

Abstract: A state-of-the-art memory controller and methods for using the same are disclosed. The memory controller is intended for use with dynamic random-access memory (DRAM) circuitry. In one example, a memory controller includes a reordering preprocessor circuitry coupled to a reordering scheduler circuitry. The reordering scheduler circuitry is configured to control a reordering scheduler queue, and is coupled to DRAM circuitry. The reordering preprocessor circuitry is configured to control a preprocessor queue and reorder transactions in the preprocessor queue so as to increase the DRAM circuitry performance.

Abstract: A storage device includes a nonvolatile memory device including a replay protected memory block; and a memory controller for, as a submission command requesting access to the replay protected memory block is received from an external host including a host memory having a plurality of Physical Region Pages (PRPs), acquiring a host replay protected memory block data frame stored in one of the plurality of PRPs included in the external host and accessing the replay protected memory block. The submission command may include information on a position at which the memory controller is to store a response to the submission command among the plurality of PRPs.

Abstract: A method for filtering addresses from a cache includes receiving, by a filter, a data request including an address specifying a memory location of the requested data, querying the filter to determine whether the address is cacheable or non-cacheable, and in response to determining the address is non-cacheable, preventing caching of the data and the address associated with the data. Other example methods, systems and non-transitory computer readable mediums for filtering addresses from a cache are also provided.

Abstract: Quad-to-single (Q2S) data structure comprising a plurality of entries maintained on a volatile memory device. Each Q2S mapping entry, identified by a physical address of a quad-level cell (QLC) block stripe of a non-volatile memory device, comprises a bit flag and a pointer to a linked list on the volatile memory device. Responsive to programming at least one single-level cell (SLC) block stripe of a plurality of SLC block stripes with data to be programmed to a QLC block stripe, an entry for an identification of the QLC block stripe to be programmed and an entry for each physical address of the at least one SLC block stripe of the plurality of SLC block stripes programmed with data to be programmed to the QLC block stripe is appended to a linked list corresponding to a Q2S mapping entry associated with the QLC block stripe to be programmed.

Abstract: A computing device comprises a processor, a table walker, and a memory storing a segmented reverse map table in multiple non-contiguous portions of the memory. The table walker is configured to translate a virtual memory address specified by a memory access request to a physical memory address associated with the virtual memory address; and provide a requester associated with the memory access request with access to the associated physical memory address in response to an indication at the reverse map table that the requester is authorized to access the associated physical memory address.

Abstract: A storage apparatus includes a first controller having a first memory, a second controller having a second memory, and a memory module having a third memory. The first memory stores drive control information including a correspondence between a logical address and a physical address, first cache data in a data input-output (I/O) process, and first cache control information including a correspondence between a logical address and a cache address of the first cache data. The second memory stores drive control information, second cache data in the data I/O process, and second cache control information including a correspondence between a logical address and a cache address of the second cache data. The third memory stores first cache data provided with redundancy and second cache data provided with redundancy.