Abstract: A method for securing data stream processing includes implementing a stage of a data processing pipeline in a trusted execution environment. A state of the stage is represented by a graph-based data structure. Protected memory of the trusted execution environment is reserved for computations of the stage. A key-value store is maintained in the protected memory. The key-value store includes hashes of graph segments of the graph-based data structure for the computations and memory locations of the graph segments. A state part of the computations is moved from the protected memory to unprotected memory. The state part of the computations is loaded back to the protected memory. An integrity of a computation using the state part of the computations is checked using the hashes in the key-value store.

Abstract: A method and apparatus of protecting a memory from a write attack includes dividing a cacheline of memory into a plurality of sub-blocks. A codeword is generated from at least one sub-block of the plurality of sub-blocks and a complement of the at least one sub-block. One of the generated codewords is selected, wherein the selected codeword is used for storage in memory.

Abstract: A memory management method of a computer including a memory and a processor connected to the memory, the method includes, by the processor, executing an OS and executing a plurality of processes on the OS. The plurality of processes include a virtual storage device and an application. The processor provides the application with a physical area of the memory, which is managed by the OS, controls the virtual storage device to use a physical area of the memory, which is mounted on the computer, but is not managed by the OS, secures continuous physical areas from the physical area of the memory, which is managed by the OS, to be used by the virtual storage device, and performs DMA transfer between the virtual storage device and the application by using the secured continuous physical areas.

Abstract: A data processing system may be configured to include a memory device, a controller configured to access the memory device when a host requests offload processing of an application, and process the application, and a sharing memory management component within the controller and configured to: set controller owning rights of access to a target region of the memory device in response to the host stores, in the target region, data used for the requested offload processing of the application; and set the controller owning rights of access or the host owning rights of access to the target region based on a processing state of the application.

Abstract: An embedded information system includes a load control circuit coupleable to an external memory that contains instructions and constant data (organized by variable sized load units, LUs, and where at least one property of a LU is specified within metadata) associated with application code of a software application, at least one processor configured to execute the at least one application code; an internal memory configured as main system memory in a first part and as a cache for storing the instructions and constant data for an execution of the at least one application code from the external memory in a second part. The load control circuit is configured to load the LUs associated with the at least one application code from the external memory with a granularity of a single LU into the internal memory.

Abstract: An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed.

Abstract: Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.

Abstract: An apparatus to facilitate dynamic cache control is disclosed. The apparatus includes one or more processors to profile execution characteristics of a graphics workload at a processing resource to generate profile data indicating a quantity of cache hits that occur at a cache memory and apply one or more cache settings to the cache memory based on the profile data.

Abstract: Various examples are directed to systems and methods for managing a memory device. Processing logic may identify a set of retired blocks at the memory device that were retired during use of the memory device. The processing logic may modify a first table entry referencing the first block to indicate that the first block is not retired. The processing logic may also modify a second table entry referencing the second block to indicate that the second block is not retired. The processing logic may also recreate a logical-to-physical table entry for a first page of at the first block, the logical-to-physical table entry associating a logical address with the first page.

Abstract: A method of operating a storage appliance is provided.

Abstract: In an approach to optimizing metadata management to boost overall system performance, a cache for a storage system is initialized. Responsive to receiving a cache hit from a host cache during a host I/O operation, a first metadata of a plurality of metadata is transferred to a storage cache, where the first metadata is associated with a user data from the host I/O operation, and further wherein the first metadata is deleted from the host cache. Responsive to determining that the storage cache is full, a second metadata of the plurality of metadata is destaged from the storage cache, where the second metadata is destaged by moving the second metadata to the host cache, and further wherein the second metadata is deleted from the storage cache.

Abstract: Systems and methods for implementing a secure communication channel between kernel and user mode components are provided. According to an embodiment, a shared memory is provided through which a kernel mode process and a user mode process communicate. The kernel mode process is assigned read-write access to the shared memory. The user mode process is assigned read-only access to the shared memory. An offset-based linked list is implemented within the shared memory. Kernel-to-user messages are communicated from the kernel mode process to the user mode process by adding corresponding nodes to the offset-based linked list. One or more kernel-to-user messages are read by the user mode process following the offset-based linked list in order. The kernel mode process is signaled by the user mode process that a kernel-to-user message has been consumed by the user mode process through an input output control (ioctl) system call or an event object.

Abstract: A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.

Abstract: The disclosure provides a data prefetching auxiliary circuit, a data prefetching method, and a microprocessor. The data prefetching auxiliary circuit includes a stride calculating circuit, a comparing module, a stride selecting module, and a prefetching output module. The stride calculating circuit receives an access address to calculate and provide a stride. The comparing module receives the access address and the stride, generates a reference address based on a first multiple, the access address and the stride, determines whether the reference address matches any of a plurality of history access addresses, and generates and outputs a hit indicating bit value. The stride selecting module receives the hit indicating bit value, and determines whether to output the hit indicating bit value based on a prefetch enabling bit value. The prefetching output module determines a prefetch address according to the output of the stride selecting module.

Abstract: A processing device in a memory system determines to send system state information associated with the memory device to a host system and identifies a subset of a plurality of event entries from a staging buffer based on one or more filtering factors, the plurality of event entries corresponding to events associated with the memory device. The processing device further sends the subset of the plurality of event entries as the system state information to the host system over a communication pipe having limited bandwidth.

Abstract: Disclosed is a method of operating a non-volatile memory device. A method of operating a non-volatile memory device according to an embodiment of the present disclosure, in a method of operating a non-volatile memory device including a log storage area, a data storage area, and an ACK generation unit, may include receiving a log and data from a cache memory, storing the received log in the log storage area, storing the received data in the data storage area, and transmitting an ACK signal to the cache memory according to a result of storing the log and the data.

Abstract: A Key-Value Solid State Drive (KV-SSD) is disclosed. The KV-SSD may include storage for data. The data may include a data value encrypted using an object encryption key. The data value may be associated with an object key: the data value and the object key forming an object. A user secure object map may map the object key to a hash value. A secure key share table may map the hash value to the object encryption key. A dedup map may map the hash value to an address where the data value is stored on the KV-SSD.

Abstract: The disclosed systems and methods may secure the fuse programming process in programmable devices to reduce or eliminate malicious discovery of data (e.g., the encryption key, the configuration bitstream) stored in nonvolatile memory via side-channel attacks. A processor may generate a randomized fuse list and the fuses may be blown in the randomized order. Additionally or alternatively, the processor may randomize the wait time between programming of each fuse. Further, the processor may generate a simplified fuse list including only fuses to be blown. The disclosed security systems and methods may be used individually or in combination to prevent determination of sensitive data, such as the encryption key, by monitoring, for example, power consumption in side-channel attacks.

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

Abstract: Disclosed embodiments relate to systems and methods for providing an end-to-end secure lifecycle of data. Techniques include receiving a request from a client to access data; reserving a designated memory region; protecting the designated memory region using access restriction to certain processes of an operating system; receiving data from a trusted source; injecting the data into the designated memory region in a zero-copy manner; sending the data to the client in a zero-copy manner; receiving an indication that the client performed an interaction; and in response to the indication, disposing of the data and the designated memory region.