Abstract: Reducing file write latency includes receiving incoming data, from a data source, for storage in a file and a target storage location for the incoming data, and determining whether the target storage location corresponds to a cache entry. Based on at least the target storage location not corresponding to a cache entry, the incoming data is written to a block pre-allocated for cache misses and the writing of the incoming data to the pre-allocated block is journaled. The writing of the incoming data is acknowledged to the data source. A process executing in parallel with the above commits the incoming data in the pre-allocated block with the file. Using this parallel process to commit the incoming data in the file removes high-latency operations (e.g., reading pointer blocks from the storage media) from a critical input/output path and results in more rapid write acknowledgement.

Abstract: An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.

Abstract: An approach is provided for providing optimized identification of duplicate data in a networked computing environment. An aggregate feature vector is created that is specific to an attribute of the data (e.g., a field that holds specific informational content). The aggregate feature vector has a set of dimensions that each define a specific comparison function used to test for similarity between data entries in the attribute. Each dimension in the aggregate feature vector is assigned an effectiveness, and a cost is computed for each dimension. Based on these two, a subset of dimensions is selected to form an optimized feature vector. This optimized feature vector can then be used to analyze a dataset to find matching data.

Abstract: Methods, devices, and systems for prefetching data. First data is loaded from a first memory location. The first data in cached in a cache memory. Other data is prefetched to the cache memory based on a compression of the first data and a compression of the other data. In some implementations, the compression of the first data and the compression of the other data are determined based on metadata associated with the first data and metadata associated with the other data. In some implementations, the other data is prefetched to the cache memory based on a total of a compressed size of the first data and a compressed size of the other data being less than a threshold size. In some implementations, the other data is not prefetched to the cache memory based on the other data being uncompressed.

Abstract: Various implementations described herein are directed to a system and methods for memory compiling. For instance, a method may include selecting source corners from a memory compiler configuration and generating a standardized set of memory instances for the selected source corners. Also, the method may include deriving a reduced set of memory instances based on the standardized set of memory instances and building a memory compiler database for a compiler space based on the standardized set of memory instances and the reduced set of memory instances.

Abstract: Methods and apparatuses related to access to data stored in quarantined memory media are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile) and data (e.g., information included in) stored in the memory media often are subject to risks of the data being undesirably exposed to the public. For example, requests to write data in the memory media can often be made and accepted without a user's awareness, which can lead to the undesirable exposure of the data. According to embodiments of the present disclosure, a particular portion and/or location in the memory media can provide a data protection scheme such that data stored in the particular location can be refrained from being transferred out of the computing system.

Abstract: Devices and techniques for managing hazards in a memory controller are described herein. The memory controller can receive a memory request that includes a base memory address. An index can be computed from the base memory address and a lookup, using the index, can be performed to find a lock. When the lock is found, the memory controller can store the memory request in a buffer that corresponds to the lock. In response to a signal to clear the lock, the memory controller removes the memory request from the buffer and performs the memory request.

Abstract: A data storage device includes a first memory device; a second memory device including a fetch region configured to store data evicted from the first memory device and a prefetch region divided into a plurality of sections; storage; and a controller configured to control the first memory device, the second memory device, and the storage. The controller may include a memory manager configured to select prefetch data having a set section size from the storage, load the selected prefetch data into the prefetch region and update the prefetch data based on a data read hit ratio of each of the plurality of sections.

Abstract: Described apparatuses and methods partition a cache memory based, at least in part, on a metric indicative of prefetch performance. The amount of cache memory allocated for metadata related to prefetch operations versus cache storage can be adjusted based on operating conditions. Thus, the cache memory can be partitioned into a first portion allocated for metadata pertaining to an address space (prefetch metadata) and a second portion allocated for data associated with the address space (cache data). The amount of cache memory allocated to the first portion can be increased under workloads that are suitable for prefetching and decreased otherwise. The first portion may include one or more cache units, cache lines, cache ways, cache sets, or other resources of the cache memory.

Abstract: An example method of memory management in a computing system having a plurality of processors includes: receiving a first memory allocation request at a memory manager from a process executing on a processor of the plurality of processors in the computing system; allocating a local memory pool for the processor from a global memory pool for the plurality of processors in response to the first memory allocation request; and allocating memory from the local memory pool for the processor in response to the first memory allocation request without locking the local memory pool.

Abstract: An apparatus to facilitate security of a shared memory resource is disclosed. The apparatus includes a memory device to store memory data, wherein the memory device comprises a plurality of private memory pages associated with one or more trusted domains and a cryptographic engine to encrypt and decrypt the memory data, including a key encryption table having a key identifier associated with each trusted domain to access a private memory page, wherein a first key identifier is generated to perform direct memory access (DMA) transfers for each of a plurality of input/output (I/O) devices.

Abstract: An apparatus controls access to a memory module coupled to a host controller via a data bus to exchange data with the host controller. The apparatus has a configurable information memory and comprises: an access control input port via which the apparatus receives a data access command from the host controller; a control unit to identify a data access command including an access address directed to a predetermined storage region of the memory module, and generate an information processing command based at least on the access address directed to the predetermined storage region, such that the control unit can configure the information memory based on the information processing command or provide the information processing command to the memory module; and an access control output port via which the apparatus provides the information processing command to the memory module, such that the memory module outputs corresponding data information to the host controller based on the information processing command.

Abstract: A technique to facilitate efficient, parallelized execution of a program using a multiprocessor system having two or more processors includes detecting and, optionally, minimizing broadcast data communication between a shared memory and two or more processors. To this end, the broadcast space of a data structure is generated as an intersection of the reuse space of the data structure and the placement space of a statement accessing the data structure. A non-empty broadcast space implies broadcast data communication that can be minimized by rescheduling the statement accessing the data structure.

Abstract: A realm management unit (RMU) manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitry enforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The memory access circuitry permits execution, from within a current realm, of program code stored in a target memory region having an owner realm other than the current realm, when the target memory region is owned by a code realm and a code realm authorisation table 908 stored in at least one memory region owned by the current realm indicates that execution of program code from the target memory region is permitted by the current realm.

Abstract: Provided is a method of data storage, the method including receiving a write request including a user key, determining the user key exists in a cache, generating or updating metadata corresponding to the user key, writing data corresponding to the write request to a storage device, converting the metadata to a device format corresponding to the storage device, and storing the metadata on the storage device.

Abstract: Signals sent to a memory component are received by circuitry included in the memory component. The circuitry comprises a comparator circuit to process the received signals. The circuitry further comprises a resistor-capacitor (RC) circuit coupled to the comparator circuit to increase bandwidth and reduce interference in the received signals processed by the comparator circuit.

Abstract: A method and system described herein for classifying data of virtual machines in a heterogeneous computing comprising virtual machines and non-virtual machines. The system may access a secondary copy of data stored by a virtual machine, create metadata associated with that data, store the metadata in an index that comprises metadata associated with data stored on non-virtual machines, using a journal file, determine modified data objects within the data stored by the virtual machine, access or create metadata associated with modified data objects, and update the index accordingly.

Abstract: A memory controller may include a host interface controller, a first queue, a second queue, and a cache memory. The host interface controller may be configured to generate, based on a request received from a host, one or more command segments corresponding to the request. The first queue may be configured to store the one or more command segments. The second queue may be configured to store a target command segment from among the one or more command segments. The memory controller caches a target map segment corresponding to the target command segment into the cache memory in response to the target command segment being transferred from the first queue to the second queue.

Abstract: A method for securing data stream processing includes implementing a stage of a data processing pipeline in a trusted execution environment. A state of the stage is represented by a graph-based data structure. Protected memory of the trusted execution environment is reserved for computations of the stage. A key-value store is maintained in the protected memory. The key-value store includes hashes of graph segments of the graph-based data structure for the computations and memory locations of the graph segments. A state part of the computations is moved from the protected memory to unprotected memory. The state part of the computations is loaded back to the protected memory. An integrity of a computation using the state part of the computations is checked using the hashes in the key-value store.

Abstract: A method and apparatus of protecting a memory from a write attack includes dividing a cacheline of memory into a plurality of sub-blocks. A codeword is generated from at least one sub-block of the plurality of sub-blocks and a complement of the at least one sub-block. One of the generated codewords is selected, wherein the selected codeword is used for storage in memory.