Abstract: A method, apparatus, and system for reducing pipeline stalls due to address translation misses is presented. An apparatus comprises a memory access instruction pipeline, a translation lookaside buffer coupled to the memory access instruction pipeline, and a TLB miss queue coupled to both the TLB and the memory access instruction pipeline. The TLB miss queue is configured to selectively store a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB along with information associated with the first memory access instruction. The TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.

Abstract: An information processing system, computer readable storage medium, and a method for managing computer memory. The method includes initializing at least one memory allocator within a computing system; deploying the at least one memory allocator on a multi-user or cloud system where users are charged a monetary fee based on consumption of at least one memory resource that is allocated by a memory allocator for at least one executing program; determining, by the at least one memory allocator, a consumption of the at least one memory resource; determining a cost associated with the consumption that has been determined; and determining a monetary fee to charge the user based on the cost that has been determined.

Abstract: A data synchronization method includes checking first to-be-checked information stored in an active area of a first board to obtain a first check result and second to-be-checked information stored in an active area of a second board to obtain a second check result before data synchronization, where the first board and the second board are include in an out-of-band management device, determining an active board and a standby board from the first board and the second board according to the first check result and the second check result, and synchronizing data in an active area of the active board to a standby area of the standby board. Hence, the method can be implemented to ensure validity of data synchronization.

Abstract: Disclosed is a system and method for providing host adjustable performance parameters for SSDs. The method includes accessing a latency profile based on a determined device age of a solid state drive (SSD). The method also includes providing for display a user interface comprising a plurality of interface elements to adjust a respective plurality of performance specifications of the SSD, wherein the user interface is configured based on the latency profile. The method also includes receiving, via the user interface, an adjustment to the plurality of performance specifications. The method also includes sending an instruction to the SSD to configure the SSD with a parameter set based on the adjusted plurality of performance specifications.

Abstract: An asynchronous storage system may perform asynchronous writing of data from different sets of received non-consecutive synchronous write requests based on a dynamic write threshold that varies according to parameters of the storage device and/or synchronous write request patterns. The asynchronous writing may include coalescing data from a set of non-consecutive write requests in a plurality of received write requests that contain different data for a particular file, issuing a single asynchronous write request with the data that is coalesced from each write request of the set of non-consecutive write requests to the storage device instead of each write request of the set of non-consecutive write requests, and writing the data that is coalesced from each write request of the set of non-consecutive write requests to the storage device with a single write operation that is executed in response to the single asynchronous write request.

Abstract: According to some exemplary embodiments of the present disclosure, a method for index recovery performed by a database server is disclosed. The method is an index redo logging method performed by a database server.

Abstract: The present disclosure includes apparatuses and methods related to dual speed memory. A memory module can include a number of memory devices that coupled to a host via a number of first ports and coupled to a controller via a number of second ports. The memory module can be configured to transfer data on the first number of ports at a first clock speed and transfer data on the second number of ports at a second clock speed.

Abstract: Embodiments of the present disclosure provide method, device and computer product for predicting disk failure. The method disclosed herein comprising: obtaining operation data of a disk, each data item of the operation data indicating values for one or more attributes of the disk at an associated time point; identifying null values for the one or more attributes from the data items of the operation data; adjusting the operation data based at least on the identifying of the null values; and processing the adjusted operation data with a machine learning model, to obtain a failure prediction on whether the disk will fail within a predetermined time period after the associated time point.

Abstract: Techniques for determining unique ownership of data blocks includes selecting a first data block referenced by a first logical address of a first logical device, wherein first metadata for the first data block includes a reference count and a result used in determining sole unique ownership of the first data block; determining C1, an expected value of the result of the first metadata when the first logical device is a sole unique owner of the first data block; and performing first processing that determines whether the first logical device is the sole unique owner of the first data block. The first processing includes: determining whether C1 equals a current value of the result of the first metadata; and determining that the first logical device is the sole unique owner of the first data block if C1 equals the current value of the result of the first metadata.

Abstract: The disclosure relates in some aspects to optimizing writes levels used for programming a non-volatile memory device. In some aspects, the disclosure relates to an algorithmic approach for adjusting write levels for a NAND flash device. For example, write level gradients may be iteratively generated based on memory cell bin distribution statistics relating to the number and direction of errors across bin boundaries.

Abstract: Techniques are disclosed for generating and utilizing a time-based distribution of I/O latency and other performance characteristics to identify potential device failures in a system that includes storage devices, such as a distributed software-defined storage system. A user interface is implemented that allows users to request and selectively view I/O latency and other data over a configurable time-based or histogram-based distribution. The user interface further enables comparison of the I/O latency distribution to data from other devices in the same class to identify potential failures.

Abstract: Systems and methods for fast storage allocation for encrypted storage are disclosed. An example method may include receiving, by a processing device executing an operating system, an identification of a first storage block that has been released by a first virtual machine; tracking, by the operating system, an encryption status corresponding to the first storage block to indicate whether the first storage block contains encrypted content; receiving a request to allocate storage to a second virtual machine; analyzing, by the operating system, the first storage block to determine that the first storage block contains encrypted content in view of the encryption status corresponding the first storage block; and allocating the first storage block containing the encrypted content to the second virtual machine without clearing the encrypted content of the first storage block.

Abstract: An apparatus to facilitate a tracking of surface properties is disclosed. The apparatus includes one or more processors to receive a memory request, access a virtual to virtual page table to retrieve an address storing surface properties metadata, and process the memory request, wherein the virtual to virtual page table provides a mapping between a main surface and an auxiliary surface including the surface properties metadata.

Abstract: A method is disclosed for recovering metadata, the method comprising: identifying a corrupt or missing metadata entry, the corrupt or missing metadata entry being part of a mapping structure that is stored in a random-access memory (RAM) of a storage system; selecting a metadata backup page that is associated with the mapping structure; identifying a plurality of copies of the selected metadata backup page; identifying a most recent copy among the plurality of copies of the selected metadata backup page; and recovering the corrupt or missing metadata entry based on the most recent one of the plurality of copies of the metadata backup page.

Abstract: A system, computer program product, and computer-implemented method for smart contract dependent resource transfer are disclosed. The system is configured to establish a smart contract between a first storage location and a second storage location, the smart contract being configured for conditionally transferring resources between the first storage location and the second storage location; monitor the first storage location to determine that a first transfer condition has been met; based on determining that the first transfer condition has been met, automatically transfer a number of resources from the second storage location to the first storage location; determine that a second transfer condition has been met; and automatically transfer the number of resources from the first storage location to the second storage location based on determining that the second transfer condition has been met.

Abstract: A memory system includes a semiconductor storage device and a memory controller. The memory controller includes a command buffer and a descriptor buffer. The memory controller stores a first command received from outside in the command buffer, fetches a first descriptor from the host device, based on the stored first command, stores the fetched first descriptor in the descriptor buffer, stores a second command received from the outside in the command buffer, discards an unused part of the first descriptor from the descriptor buffer, fetches a second descriptor from the host device, based on the stored second command, and stores the fetched second descriptor at an address where the discarded part of the first descriptor was stored.

Abstract: A non-volatile memory includes a plurality of blocks of physical memory, including a target block and at least one source block containing at least some valid data and some invalid data. Responsive to determining to perform garbage collection for the non-volatile memory, the controller transfers valid data from the at least one source block to the target block. The controller ends garbage collection on the at least one source block with at least some valid data present in the at least one source block and all interfaces of the target block closed at the boundary of independent layers. In at least some embodiments, the target block may be configured to store more bits per cell than the at least one source block.

Abstract: An embodiment of a semiconductor apparatus for use with redundant storage may include technology to cache all data for a write request for at least two member persistent storage drives in a persistent cache with a write access latency at least as low as a lowest write access latency of the at least two member persistent storage drives, write the data for the write request to one member persistent storage drive of the at least two member persistent storage drives, and indicate that the write request is complete after the data for the write request is redundantly stored in the persistent cache and the one member persistent storage drive. Other embodiments are disclosed and claimed.

Abstract: A memory controller may include a buffer memory configured to store a plurality of metadata groups and a journal log set for a metadata group of the plurality of metadata groups, wherein the journal log set includes a plurality of journal logs respectively indicating update information for the plurality of metadata groups. The memory controller may include control circuitry configured to identify journal times taken to execute respective journal logs of the plurality of journal logs, identify a prediction time taken to update the metadata group based on the journal log set, and control a number of journal logs included in the journal log set based on the journal times and the prediction time.

Abstract: Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.