Patents Examined by Sitaramarao S Yechuri
  • Patent number: 12022742
    Abstract: Provided is a magnetic tunnel junction element including: a magnetization pinned layer having a fixed magnetization direction; a first insulating layer which is provided on the magnetization pinned layer and is formed of an insulating material; a magnetization free layer provided on the first insulating layer; an adjacent layer which is provided adjacent to the magnetization free layer and is formed of a non-magnetic transition metal; and a cap layer which is formed to have a multilayer structure including at least one barrier layer formed of a non-magnetic transition metal and is provided on the adjacent layer.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: June 25, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Eiji Kariyada, Hironobu Tanigawa, Tetsuhiro Suzuki
  • Patent number: 12021158
    Abstract: The present disclosure pertains to the field of back contact heterojunction cell technologies, and particularly relates to a mask-layer-free hybrid passivation back contact cell and a fabrication method thereof; the method includes: S101: providing a silicon wafer substrate; S102: sequentially forming a first semiconductor layer and a mask layer on a back surface of the silicon wafer substrate, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer; S103: performing first etching on the first semiconductor layer on the obtained back surface to form first opening regions W1; S104: forming a textured surface in the first opening region W1 on the back surface by texturing and cleaning; S105: removing the mask layer; S106: forming a second semiconductor layer on the obtained back surface; and S107: performing second etching on a polished region of the obtained back surface.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: June 25, 2024
    Assignee: Golden Solar (Quanzhou) New Energy Technology Co., Ltd.
    Inventor: Kairui Lin
  • Patent number: 12021175
    Abstract: A display device includes a light-emitting layer and a red converting layer, the red converting layer includes a binder resin, red luminescent bodies, and In nanoparticles, each of the In nanoparticles includes a core and a silica shell, and the silica shell includes blue luminescent bodies emitting light having a wavelength shorter than that of red luminescent bodies.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: June 25, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Koji Murata, Tokiyoshi Umeda, Yuto Tsukamoto
  • Patent number: 12022698
    Abstract: The present disclosure provides an array substrate, a display panel and a display device. The array substrate includes: a base substrate; a low temperature poly-silicon thin film transistor located on the base substrate and including a poly-silicon active layer and a first gate which are laminated on the base substrate; an oxide thin film transistor located on the base substrate and including an oxide active layer and a second gate which are laminated on the base substrate; and a light shielding layer, where an overlapping area of a projection of the light shielding layer on the base substrate and an orthographic projection of the oxide active layer on the base substrate is S1, an overlapping area of the projection of the light shielding layer on the base substrate and an orthographic projection of the poly-silicon active layer on the base substrate is S2, and S1 is greater than S2.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 25, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Benlian Wang, Yue Long, Lili Du, Yao Huang, Weiyun Huang, Tianyi Cheng
  • Patent number: 12015093
    Abstract: Photodetectors based on colloidal quantum dots and methods of making the photodetectors are provided. Also provided are methods for doping films of colloidal quantum dots via a solid-state cation exchange method. The photodetectors include multi-band photodetectors composed of two or more rectifying photodiodes stacked in aback-to-back configuration. The doping methods rely on a solid-state cation exchange that employs sacrificial semiconductor nanoparticles as a dopant source for a film of colloidal quantum dots.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: June 18, 2024
    Assignee: THE UNIVERSITY OF CHICAGO
    Inventors: Philippe Guyot-Sionnest, Xin Tang, Matthew M. Ackerman
  • Patent number: 12015099
    Abstract: A method and structure providing an optical sensor having an optimized Ge—Si interface includes providing a substrate having a pixel region and a logic region. In some embodiments, the method further includes forming a trench within the pixel region. In various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. In some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. In some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yin-Kai Liao, Jen-Cheng Liu, Kuan-Chieh Huang, Chih-Ming Hung, Yi-Shin Chu, Hsiang-Lin Chen, Sin-Yi Jiang
  • Patent number: 12009450
    Abstract: A first n-type contact layer, a second n-type contact layer, a multiplication layer, an electric field control layer, a light absorbing layer, and a p-type contact layer are layered in this order on a substrate. The second n-type contact layer is formed between the first n-type contact layer and the light absorbing layer, is made to have an area smaller than that of the light absorbing layer in a plan view, and is disposed inside the light absorbing layer in a plan view.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: June 11, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Yuki Yamada, Masahiro Nada
  • Patent number: 12002906
    Abstract: The present disclosure provides a semiconductor device and a semiconductor component. The semiconductor device includes an active structure, a ring-shaped semiconductor contact layer, a first electrode, and an insulating layer. The active structure has a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer located between the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer. The ring-shaped semiconductor contact layer is located on the second-conductivity-type semiconductor layer and having a first inner sidewall and a first outer sidewall. The first electrode has an upper surface and covers the ring-shaped semiconductor contact layer. The insulating layer covers the first electrode and the active structure and has a second inner sidewall and a second outer sidewall. The first inner sidewall is not flush with the second inner sidewall in a vertical direction.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: June 4, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Hao-Chun Liang, Wei-Shan Yeoh, Yao-Ning Chan, Yi-Ming Chen, Shih-Chang Lee
  • Patent number: 12002830
    Abstract: According to an aspect, a detection device includes: a substrate; a plurality of photodiodes arranged on a first principal surface of the substrate; a protective film that covers the photodiodes; a plurality of lenses provided for each of the photodiodes so as to face the photodiode with the protective film interposed between the lenses and the photodiodes; and a projection provided between the lenses. A top of the projection is located at a position higher than a top of each of the lenses when viewed from the first principal surface.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: June 4, 2024
    Assignee: Japan Display Inc.
    Inventors: Satoshi Chinen, Morikazu Nomura
  • Patent number: 11990550
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a S/D silicide layer formed on the S/D epitaxial layer, and the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width. The semiconductor structure includes a dielectric spacer between the gate structure and the S/D silicide layer, and a top surface of the dielectric spacer is lower than a top surface of the gate structure.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Patent number: 11978812
    Abstract: A waveguide photodetector includes a first contact layer of a first conductivity type, a waveguide layer, and a second contact layer of a second conductivity type that are sequentially formed on the semiconductor substrate. The waveguide layer includes a first cladding layer of the first conductivity type disposed on a side of the first contact layer, a second cladding layer of the second conductivity type disposed on a side of the second contact layer, and the core layer disposed between the first cladding layer and the second cladding layer. The core layer includes a light absorption layer and an impurity-doped light absorption layer that has a higher concentration of a p-type impurity than that of the light absorption layer and is disposed on a side of a light incident face.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: May 7, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Ryota Takemura
  • Patent number: 11973159
    Abstract: Provided is a photodetector which can be manufactured in a standard process of a mass-produced CMOS foundry. The photodetector includes a silicon (Si) substrate; a lower clad layer; a core layer including a waveguide layer configured to guide signal light, and including a first Si slab doped with first conductive impurity ions and a second Si slab doped with second conductive impurity ions; a germanium (Ge) layer configured to absorb light and including a Ge region doped with the first conductive impurity ions; an upper clad layer; and electrodes respectively connected to the first and second Si slabs and the Ge region. A region of the core layer sandwiched between the first Si slab and the second Si slab operates as an amplification layer.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 30, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Kotaro Takeda, Kiyofumi Kikuchi, Yoshiho Maeda, Tatsuro Hiraki
  • Patent number: 11961941
    Abstract: An LED array comprises a first mesa comprising a top surface, at least a first LED including a first p-type layer, a first n-type layer and a first color active region and a tunnel junction on the first LED, a second n-type layer on the tunnel junction, the second n-type layer comprising at least one n-type III-nitride layer with >10% Al mole fraction and at least one n-type III-nitride layer with <10% Al mole fraction. The LED array further comprises an adjacent mesa comprising a top surface, the first LED, a second LED including the second n-type layer, a second p-type layer and a second color active region. A first trench separates the first mesa and the adjacent mesa, cathode metallization in the first trench and in electrical contact with the first and the second color active regions of the adjacent mesa, and anode metallization contacts on the n-type layer of the first mesa and on the anode layer of the adjacent mesa.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: April 16, 2024
    Assignee: Lumileds LLC
    Inventors: Robert Armitage, Isaac Wildeson
  • Patent number: 11963457
    Abstract: A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jesmin Haq, Tom Zhong, Zhongjian Teng, Vinh Lam, Yi Yang
  • Patent number: 11961935
    Abstract: A detection base plate and a flat-panel detector. The detection base plate comprises multiple detection pixel units arranged in an array. Each detection pixel unit comprises: a thin-film transistor, a sacrificial layer and a photoelectric conversion part that are disposed on a substrate, wherein the sacrificial layer is located between the thin-film transistor and the photoelectric conversion part; the thin-film transistor comprises an active layer, a first electrode and a second electrode; at least part of an orthographic projection of the active layer on the substrate is located within an orthographic projection of the sacrificial layer on the substrate; and the photoelectric conversion part is electrically connected to the sacrificial layer and the first electrode. In the detection base plate, the sacrificial layers of the detection pixel units are mutually independent.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: April 16, 2024
    Assignees: BEIJING BOE SENSOR TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jianxing Shang, Xiangmi Zhan, Zhenwu Jiang, Huinan Xia, Xuecheng Hou
  • Patent number: 11955395
    Abstract: A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Lizabeth Keser, Bernd Waidhas, Thomas Ort, Thomas Wagner
  • Patent number: 11954275
    Abstract: A display panel and a display device are provided. By providing a winding structure with a hollow part on an electrode trace of a touch function layer, a parasitic capacitance between the touch function layer and a cathode layer at a pillar can be reduced. Furthermore, an overall consistency of the parasitic capacitance between the touch function layer and the cathode layer is balanced, noise caused by imbalance of the parasitic capacitance is avoided, and an overall touch report rate and sensitivity are improved.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: April 9, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Jian Ye
  • Patent number: 11949034
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodetector and methods of manufacture. The structure includes: a photodetector; and a semiconductor material on the photodetector, the semiconductor material comprising a first dopant type, a second dopant type and intrinsic semiconductor material separating the first dopant type from the second dopant type.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: April 2, 2024
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: John J. Ellis-Monaghan, Rajendran Krishnasamy, Siva P. Adusumilli, Ramsey Hazbun
  • Patent number: 11940271
    Abstract: A method of preparing a computer processor die includes determining a warpage shape of the computer processor die at a testing temperature. The method also includes selectively contouring a thickness of the computer processor die at a contouring temperature by physically removing material from a surface of the computer processor die such that the surface will be substantially flat at the testing temperature.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: March 26, 2024
    Assignee: International Business Machines Corporation
    Inventors: David J. Lewison, Jay A. Bunt, Frank L. Pompeo, Richard Walter Oldrey, John D. Sylvestri, Phong T. Tran
  • Patent number: 11935956
    Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Kevin P. O'Brien, Carl Naylor, Chelsey Dorow, Kirby Maxey, Tanay Gosavi, Ashish Verma Penumatcha, Shriram Shivaraman, Chia-Ching Lin, Sudarat Lee, Uygar E. Avci