Abstract: A display apparatus includes a circuit substrate with driving circuits and first bonding electrodes, and a pixel array having LED cells, each of the LED cells including first and second conductivity-type semiconductor layers with an active layer therebetween, second bonding electrodes on the first bonding electrodes, wavelength converters on the LED cells, an upper semiconductor layer on the LED cells and having a partition structure surrounding side snakes of the wavelength converters and separating the wavelength converters, a first reflective electrode on the side surfaces of the LED cells, spaced from the LED cells by a passivation layer, and extending between the LED cells, second reflective electrodes on the lower surfaces of the LED cells and connected to the second conductivity-type semiconductor layers, a common electrode on at least one side of the LED cells, and a pad electrode outside the LED cells and electrically connected to the driving circuits.

Abstract: A single-photon detection pixel includes a substrate, a first well provided in the substrate, a pair of heavily doped regions provided on the first well, and a contact provided between the pair of heavily doped regions, wherein the substrate and the pair of heavily doped regions have a first conductivity type, and the first well and the contact have a second conductivity type that is different from the first conductivity type.

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

Abstract: There is provided a display device comprising a substrate, a pixel electrode on the substrate, a light emitting element on the pixel electrode, and extending in a thickness direction of the substrate, a common electrode on the light emitting element, a wavelength conversion layer on the common electrode, including wavelength conversion particles for converting first light emitted from the light emitting element into second light, and a selective transmission film on an upper surface and on sides of the wavelength conversion layer, and configured to reflect the first light, and to transmit the second light.

Abstract: A ultraviolet detector includes a substrate; a first epitaxial layer that is a heavily doped epitaxial layer and located on the substrate, a second epitaxial layer located on the first epitaxial layer, where the second epitaxial layer is a lightly doped epitaxial layer, or a double-layer or multi-layer structure composed of at least one lightly doped epitaxial layer and at least one heavily doped epitaxial layer; an ohmic contact layer located on the second epitaxial layer or formed in the second epitaxial layer, where the ohmic contact layer is a graphical heavily doped layer; and a first metal electrode layer located on the ohmic contact layer.

Abstract: An object is to provide an infrared sensor with a quantum dot optimized. The present invention provides an infrared sensor (1) including a light absorption layer (5) that absorbs an infrared ray, wherein the light absorption layer includes a plurality of spherical quantum dots (21). Alternatively, the present invention provides an infrared sensor including a light absorption layer that absorbs an infrared ray, wherein the light absorption layer includes a plurality of quantum dots and the quantum dot includes at least one kind of PbS, PbSe, CdHgTe, Ag2S, Ag2Se, Ag2Te, AgInSe2, AgInTe2, CuInSe2, CuInTe2, and InAs.

Abstract: A memory device includes a gate stack structure, a channel pillar, a plurality of conductive pillars, and a charge storage structure. The gate stack structure is located over a dielectric substrate, and includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The channel pillar extends through the gate stack structure. Each of the conductive pillars includes a body portion and an extension portion. The body portion extends through the gate stack structure and is electrically connected to the channel pillar. The extension portion is below and is electrically isolated from the channel pillar. The charge storage structure is between the channel pillar and the plurality of gate layers.

Abstract: A semiconductor device includes a substrate including a first active fin and a second active fin respectively extending in a first direction, the substrate having a recess between the first and second active fins, a device isolation film on the substrate, first and second gate structures on the first and second active fins, respectively, and extending in a second direction, and a field separation layer having a first portion between the first and second active fin and in the recess, and a second portion extending from both sides of the first portion in the second direction to an upper surface of the device isolation film. The recess has a bottom surface lower in a third direction intersecting the first direction and the second direction than the upper surface of the device isolation film, and a region of the upper surface of the device isolation film has a flat surface.

Abstract: A superlattice phase-change thin film with a low density change, a phase-change memory and a preparation method. The superlattice phase-change thin film includes first phase-change layers (7) and second phase-change layers (8) that are alternately stacked to form a periodic structure; during crystallization, the first phase-change layer (7) has a conventional positive density change, and the second phase-change layer (8) has an abnormal negative density change, therefore, the abnormal density reduction and volume increase of the second phase-change layer (8) during crystallization can be used to offset the volume reduction of the first phase-change layer (7) during crystallization.

Abstract: A transparent display device includes a substrate provided with a display area on which subpixels are disposed, a first non-display area disposed on one side of the display area, and a second non-display area disposed on another side of the display area. Power shorting bars are in the first non-display area over the substrate and extend in parallel in a first direction. Power lines are positioned in the display area over the substrate, extend in a second direction and are coupled to the power shorting bars. A first transmissive area is positioned between the power lines, and a second transmissive area is positioned between the power shorting bars, both of which have substantially the same shape. The shorting bars are coupled together on at least one end.

Abstract: The present disclosure provides a transparent display device, a simulation method, and a manufacturing method. The transparent display device includes a base substrate and a plurality of pixels arranged in an array form on the base substrate. Each pixel includes a transparent region and a display region, and a scattering structure for scattering light is arranged along a boundary between the transparent region and the display region.

Abstract: Provided are an inverter including a first source and drain, an interlayer insulating film on the first source, a second source on the interlayer insulating film, a second drain on the first drain, a first channel between the first source and drain, a second channel over the first channel between the second source and drain, a gate insulating film covering outer surfaces of the first and second channel, a part of a surface of the first source in the direction to the first drain, a part of a surface of the second source in the direction to the second drain, a part of a surface of the first drain in the direction to the first source, and a part of a surface of the second drain in the direction to the second source, and a gate electrode between the first source and drain and between the second source and drain.

Abstract: A display device includes a pixel electrode, a wall layer, an emission layer, a touch electrode, and a light blocking member. The wall layer includes an opening exposing the pixel electrode. The emission layer overlaps the pixel electrode. The light blocking member overlaps the touch electrode and includes a first opening and a second opening each exposing the emission layer. A first perimeter section of the first opening is spaced from a first perimeter section of the opening by a first distance in a first direction in a plan view of the display device. A second perimeter section of the first opening is spaced from a second perimeter section of the opening by a second distance in a second direction in the plan view. The second distance is equal to the first distance. The second direction is at 45 degrees relative to the first direction.

Abstract: A semiconductor memory device, and a method of manufacturing the same, includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs passing through the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs passing through the upper stack and being in contact with an upper portion of the plurality of cell plugs, and a separation pattern separating adjacent drain select plugs among the plurality of drain select plugs, wherein the separation pattern is in contact with a sidewall of each of the adjacent drain select plugs.

Abstract: A non-volatile memory device, includes a source region and a drain region disposed in a channel length direction on a substrate; a flash cell, including a floating gate and a control gate, disposed between the source region and the drain region; a selection gate disposed between the source region and the flash cell; a selection line connecting the selection gate; a word line connecting the control gate; a common source line connected to the source region; and a bit line connected to the drain region.

Abstract: A display panel includes: a substrate on which pixels are disposed; a bank which defines a light emitting area of the pixels; a light emitting layer formed in the light emitting area, the bank includes: a hydrophilic bank which extends in a row direction and separates pixel rows; a first hydrophobic bank which is formed on the hydrophilic bank; and a second hydrophobic bank which extends in a column direction and separates pixel columns, and the first hydrophobic bank has a lower hydrophobic property than that of the second hydrophobic bank.

Abstract: A display device includes: a plurality of pixel electrodes; a plurality of pixel circuits below the plurality of pixel electrodes; some scan lines, each of the scan lines being connected to a corresponding one group of the plurality of pixel circuits; and a scan drive circuit configured to selectively send scanning signals to the scan lines. The plurality of pixel electrodes include effective pixel electrodes corresponding to respective pixels constituting a displayed image, and dummy pixel electrodes between the effective pixel electrodes and the scan drive circuit and corresponding to none of the respective pixels. Each of the effective pixel electrodes is connected to a corresponding one of the plurality of pixel circuits. Each of the scan lines is electrically connected to the scan drive circuit through a corresponding at least one of the dummy pixel electrodes.

Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.

Abstract: According to one embodiment, in a first concentration of an impurity element contained in a first impurity region, a second concentration of the impurity element contained in a second impurity region, a third concentration of the impurity element contained in a third impurity region, and a fourth concentration of the impurity element contained in a high-concentration impurity region, the third concentration is equal to the fourth concentration, the third concentration is higher than the first concentration, and the first concentration is higher than the second concentration.

Abstract: A device includes an active region, an isolation structure, a gate structure, an interlayer dielectric (ILD) layer, a reading contact, and a sensing contact. The isolation structure laterally surrounds the active region. The gate structure is across the active region. The ILD layer laterally surrounds the gate structure. The reading contact is in contact with the isolation structure and is separated from the gate structure by a first portion of the ILD layer. The sensing contact is in contact with the isolation structure and is separated from the gate structure by a second portion of the ILD layer.