Patents Examined by Sitaramarao S Yechuri
  • Patent number: 10381532
    Abstract: A wavelength conversion device includes a light source for emitting light having a predetermined wavelength in a wavelength region from ultraviolet light to visible light, a phosphor layer for performing wavelength conversion on light which is emitted from the light source and incident on an incidence face, and an optical member which is arranged between the light source and the phosphor layer, splits and separates light emitted from the light source and emits the split and separated light beams to the incidence face of phosphor layer.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: August 13, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Masahito Yamana, Noboru Iizawa, Jun Hirai, Yoshiyuki Nakano
  • Patent number: 10373946
    Abstract: Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a p-type substrate; a silicon-controlled rectifier (SCR) over the p-type substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode including a gate in the n-well region, the Schottky diode positioned to mitigate electrostatic discharge (ESD) across the negatively charged fin and the n-well region in response to application of a forward voltage across the gate.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chien-Hsin Lee, Mahadeva Iyer Natarajan, Manjunatha Prabhu
  • Patent number: 10374006
    Abstract: The present invention provides a magnetic random access memory (MRAM) structure, the MRAM structure includes a transistor including a gate, a source and a drain, and a magnetic tunnel junction (MTJ) device, the MTJ device includes at least one free layer, an insulating layer and a fixed layer, the insulating layer is disposed between the free layer and the fixed layer, and the free layer is located above the insulating layer. The free layer of the MTJ device is electrically connected to a bit line (BL). The fixed layer of the MTJ device is electrically connected to the source of the transistor, and the drain of the transistor is electrically connected to a sense line (SL). And a first conductive via, directly contacting the MTJ device, the material of the first conductive via comprises tungsten.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 6, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Yu-Ping Wang, Yu-Ruei Chen
  • Patent number: 10361140
    Abstract: A method of manufacturing integrated devices, and a stacked integrated device are disclosed. In an embodiment, the method comprises providing a substrate; mounting at least a first electronic component on the substrate; positioning a handle wafer above the first electronic component; attaching the first electronic component to the substrate via electrical connectors between the first electronic component and the substrate; and while attaching the first electronic component to the substrate, using the handle wafer to apply pressure, toward the substrate, to the first electronic component, to manage planarity of the first electronic component during the attaching. In an embodiment, a joining process is used to attach the first electronic component to the substrate via the electrical connectors. For example, thermal compression bonding may be used to attach the first electronic component to the substrate via the electrical connectors.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Qianwen Chen, Bing Dang, John Knickerbocker, Joana Sofia Branquinho Teresa Maria
  • Patent number: 10347543
    Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding rais
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Rick Carter, Vikrant Chauhan, George Jonathan Kluth, Anurag Mittal, David Pritchard, Mahbub Rashed
  • Patent number: 10347657
    Abstract: A complimentary metal-oxide-semiconductor (CMOS) device includes a wafer having a bulk semiconductor layer. A fin-type semiconductor device is formed on a first portion of the wafer. The CMOS devices also includes a nanosheet semiconductor device formed on a second portion of the wafer different from the first portion.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10347730
    Abstract: A trench gate structure and a manufacturing method therefor. The trench structure comprises a substrate (10), a trench on the surface of the substrate (10), an insulating spacer (20) on the substrate (10), a gate oxide layer (41) on the inner surface of the trench, and a polysilicon gate (40) on the gate oxide layer (41). The insulating spacer (20) abuts against the trench by means of a slope structure (21) of the insulating spacer; the polysilicon gate (40) extends onto the insulating spacer (20) along the slope structure (21) in the trench; the insulating spacer (20) comprises a polysilicon gate pull-up area (22) that is concave downwards with respect to other parts of the insulating spacer (20); the polysilicon gate (40) extending out of the trench is rested on the polysilicon gate pull-up area (22).
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 9, 2019
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Zheng Bian
  • Patent number: 10333036
    Abstract: A method is provided for fabricating an emissive display color conversion film. An emissive substrate top surface is conformally coated with an optically transparent carrier film, covering an array of emissive elements. A suspension, including a fluid and a color conversion material (e.g., QDs), is then selectively deposited in absorption regions overlying the emissive elements, for example, using inkjet patterning. After the suspension is absorbed into the absorption regions, the fluid is removed from the suspension, leaving the color conversion material in the absorption regions, and forming the color conversion film. The removal of the fluid encapsulates the color conversion material in the absorption regions. Typically, the conformal coating is thick enough to form a planar top surface. The conformally coating of carrier film may also act to encapsulate both properly aligned emissive elements, as well as misaligned emissive elements that may be located on the emissive substrate top surface.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: June 25, 2019
    Assignee: eLux Inc.
    Inventor: Kurt Ulmer
  • Patent number: 10333001
    Abstract: A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gin-Chen Huang, Ching-Hong Jiang, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 10330994
    Abstract: A drain electrode 25 of a TFT 21 overlaps with a gate electrode formed integrally with a gate line 23. A pixel electrode 22 has a main body part formed on a first side of the gate line 23, and an extension part extending in an extending direction of a data line 24 and covering an overlapping portion of the gate electrode and the drain electrode 25. The drain electrode 25 is not formed on a second side of the gate line 23, whereas the extension part of the pixel electrode 22 is formed also on the second side of the gate line 23. Even when a position of the pixel electrode 22 is shifted in the extending direction of the data line 24, a parasitic capacitance between a drain and a source of the TFT 21 is kept constant, because an area of a portion where the extension part of the pixel electrode 22 overlaps with the gate line 23 does not change. With this, degradation of display quality due to a variation in the parasitic capacitance between the gate and drain of the TFT 21 can be prevented.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: June 25, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Yoshida, Masakatsu Tominaga, Tomoo Furukawa, Junichi Morinaga
  • Patent number: 10319554
    Abstract: Example compact modular electron beam units are provided that can be used to generate electron beams using field emitter elements. A modular electron beam unit may comprise an electron beam source including a base portion, at least one field emitter element coupled to the base portion, the field emitter element including a field emitter tip, at least one gate electrode and a membrane window disposed over the at least one gate electrode.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: June 11, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Akintunde I. Akinwande, Stephen Angelo Guerrera
  • Patent number: 10319662
    Abstract: The present disclosure relates to a thermal management solution for ESD protection devices in advanced Fin- and/or Nanowire-based technology nodes, by employing localized nano heat sinks, which enable heat transport from local hot spots to surface of chip, which allows significant reduction in peak temperature for a given ESD current. In an aspect, the proposed semiconductor device can include at least one fin having a source and a drain disposed over a p-well or a n-well in a substrate; an electrically floating dummy metal gate disposed close to drain or hot spot over at least a portion of the at least one fin, and an electrical metal gate is disposed close to the source; and a nano-heat sink operatively coupled with the dummy metal gate and terminating at the surface of chip in which the semiconductor device is configured so as to enable transfer of heat received from the at least one fin through the dummy metal gate to the surface of the chip.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: June 11, 2019
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Mayank Shrivastava, Milova Paul, Christian Russ, Harald Gossner
  • Patent number: 10319787
    Abstract: Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: June 11, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Haruhiko Terada
  • Patent number: 10319878
    Abstract: A method is presented for fabricating a light emitting diode (LED) device with a stratified quantum dot (QD) structure. The method provides an LED and a stratified QD structure is formed as follows. A first liquid precursor is deposited overlying the LED emission surface to form a transparent first barrier layer. A second liquid precursor is deposited overlying the first barrier layer to form a first layer of discrete QDs. A third liquid precursor is deposited overlying the first layer of QDs to form a transparent second barrier layer. Subsequent to each barrier layer liquid precursor deposition, an annealing is performed to cure the deposited precursor. The first and second barrier layers act to encapsulate the first layer of QDs. The LED emits a first wavelength of light, and the first layer of QDs converts the first wavelength of light to a first color of light in the visible spectrum.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 11, 2019
    Assignee: eLux, Inc.
    Inventors: Kurt Ulmer, Alexey Koposov
  • Patent number: 10319713
    Abstract: An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 11, 2019
    Assignee: LEADTREND TECHNOLOGY CORPORATION
    Inventors: Kuo-Chin Chiu, Chia-Wei Hung
  • Patent number: 10312419
    Abstract: A white light emitting device may include a blue light emitting diode configured to emit blue light and a plurality of wavelength conversion materials configured to convert the blue light into light having different wavelengths based on being excited by the blue light, and emit white light based on the converting, wherein the emitted white light is associated with an Illuminating Engineering Society (IES) TM-30-15 Fidelity Index (Rf) in a range of 78 to 89, an IES TM-30-15 Chroma Change by Hue Index Rcs15 in a range of 7% to 16%, and an IES TM-30-15 Chroma Change by Hue Index Rcs16 in a range of 7% to 16%, and a color difference between a reflection spectrum of a white specimen of the emitted white light, and International Commission on Illumination (CIE) Standard illuminant D65, that is equal to or less than 106.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 4, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong Rok Oh, Jeong Eun Yun, Sung Woo Choi, Cho Hui Kim, Chul Soo Yoon
  • Patent number: 10304728
    Abstract: A system and method for fabricating metal patterns are described. Multiple mandrels are formed on a first polysilicon layer which is on top of a first oxide layer. Each mandrel uses a second polysilicon on top of a first nitride. A spacer oxide and a spacer nitride are formed on the sidewalls of the mandrels to create double spacers. A second oxide layer is deposited followed by removing layers until the first nitride in the mandrels is reached. Areas are etched based on a selected method of multiple available methods until the first oxide layer is etched providing trenches for the metal patterns. Remaining materials on the first oxide layer are removed followed by metal being deposited in the trenches in the first oxide layer.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: May 28, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 10304970
    Abstract: In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a reverse breakdown voltage that is greater, in absolute magnitude, than the forward breakover voltage, where the forward breakover voltage is greater than +400 volts. In a third embodiment, a string of series-connected breakover diode dice is provided, along with a resistor string, in a packaged circuit. The packaged circuit acts like a single breakover diode having a large forward breakover voltage and a comparably large reverse breakdown voltage, even though the packaged circuit includes no discrete high voltage reverse breakdown diode. The packaged circuit is usable to supply a triggering current to a thyristor in a voltage protection circuit.
    Type: Grant
    Filed: January 20, 2018
    Date of Patent: May 28, 2019
    Assignee: IXYS, LLC
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Patent number: 10304826
    Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu, Ding-Kang Shih, Hau-Yu Lin
  • Patent number: 10304819
    Abstract: A semiconductor device includes a cell region that includes a first active region and a second active region extending in a first direction and a separation region between the first active region and the second active region. The cell region has a first width. A first gate structure and a second gate structure are disposed on the cell region, are spaced apart from each other in the first direction, and extend in the second direction. A first metal line and a second metal line are disposed on the cell region, extend in the first direction, and are spaced apart from each other by a first pitch. Each of the first and second metal lines has a second width. A first gate contact electrically connects the first gate structure and the first metal line. At least a portion of the first gate contact overlaps the separation region. A second gate contact electrically connects the second gate structure and the second metal line. At least a portion of the second gate contact overlaps the separation region.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo Jin Kim, Kwan Young Chun