Patents Examined by Sitaramarao S Yechuri
  • Patent number: 10971620
    Abstract: A method includes partly removing a supporting layer arranged between a first semiconductor layer and a second semiconductor layer using an etching process to form at least one undercut between the first semiconductor layer and the second semiconductor layer, at least partly filling the at least one undercut with a first material having a higher thermal conductivity than the supporting layer, and forming a sensor device in or on the second semiconductor layer. Semiconductor arrangements and devices produced by the method are also described.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Joachim Weyers, Andreas Boehm, Anton Mauder, Patrick Schindler, Stefan Tegen, Armin Tilke, Uwe Wahl
  • Patent number: 10971428
    Abstract: A semiconductor baseplate is disclosed. Specific implementations of a baseplate may include a planar portion including a plurality of recesses therein, the planar portion may be made of a first material, and a plurality of pegs where each peg of the plurality of pegs may be configured to fit within each recess of the plurality of recesses, the plurality of pegs may be made of a second material, where the first material and the second material may be bonded together.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 6, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol Prajuckamol, Francis J. Carney, Chee Hiong Chew, Yushuang Yao
  • Patent number: 10957841
    Abstract: A method of fabricating an electrical contact junction that allows current to flow includes: providing a substrate including a first layer of superconductor material; removing a native oxide of the superconductor material of the first layer from a first region of the first layer; forming a capping layer in contact with the first region of the first layer, in which the capping layer prevents reformation of the native oxide of the superconductor material in the first region; forming, after forming the capping layer, a second layer of superconductor material that electrically connects to the first region of the first layer of superconductor material to provide the electrical contact junction that allows current to flow.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: March 23, 2021
    Assignee: Google LLC
    Inventor: Anthony Edward Megrant
  • Patent number: 10957663
    Abstract: A center pad or paddle that is shaped with three or more curved spires which are symmetrical in form about axis that radiate from the center of the integrated circuit package, which takes advantage of the surface tension of solder to produce increased rotational align forces and increased centering forces during package soldering when aligned to a matching shaped pad on the surface of a circuit board.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: March 23, 2021
    Inventor: Myron Walker
  • Patent number: 10957632
    Abstract: The disclosure relates to a lead frame assembly for a semiconductor device, the lead frame assembly including: a die attach structure and clip frame structure. The clip frame structure includes: a die connection portion configured to contact to one or more contact terminals on a top side of the semiconductor die; one or more electrical leads extending from the die connection portion at a first end, and a lead supporting member extending from a second end of the one or more leads; and a plurality of clip support members arranged orthogonally to the one or more electrical leads. The plurality of support members and the lead supporting member are configured to contact the die attach structure. The present disclosure also relates a die attach structure and clip frame structure for a semiconductor device, a semiconductor device including the same and a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 23, 2021
    Assignee: Nexperia B.V.
    Inventors: Ricardo Lagmay Yandoc, Adam Richard Brown, Arnel Biando Taduran
  • Patent number: 10957795
    Abstract: A vertical field effect transistor (VFET) including a first source/drain region, a channel structure upwardly protruding from the first source/drain region and configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side thereof, the channel structure including one or two first portions and one or more second portions, the one or two first portion extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or more first portions and extending in a second direction, the second direction being different from the first direction, a gate structure horizontally surrounding the channel structure, and a second source/drain region upwardly on the channel structure may be provided.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Hee Park, Myung Gil Kang, Young-Seok Song, Keon Yong Cheon
  • Patent number: 10950762
    Abstract: The present invention provides a round chip scale package comprising: a light emitting diode for providing blue light from a side surface and an upper surface thereof; and a three-dimensional fluorescent layer arranged to encompass the side surface and the upper surface of the light emitting diode, thereby converting the blue light emitted from the side surface and the upper surface of the light emitting diode into white light, wherein the three-dimensional fluorescent layer comprises a phosphor and silicon, and an edge region of the three-dimensional fluorescent layer is formed into a round shape.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: March 16, 2021
    Inventors: Jae-Sik Min, Jae-Yeop Lee, Byoung-Gu Cho, Byoung-Chul Cho, Byoung-Kwon Cho
  • Patent number: 10943828
    Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Yi Tsai, Yi-Hsuan Hsiao, Shu-Yuan Ku, Ryan Chia-Jen Chen, Ming-Ching Chang
  • Patent number: 10944049
    Abstract: A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jesmin Haq, Tom Zhong, Zhongjian Teng, Vinh Lam, Yi Yang
  • Patent number: 10937873
    Abstract: A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 2, 2021
    Assignee: Cree, Inc.
    Inventors: Kyoung-Keun Lee, Fabian Radulescu, Scott Sheppard
  • Patent number: 10937665
    Abstract: Methods and apparatus for gettering impurities in semiconductors are disclosed. A disclosed example multilayered die includes a substrate material, a component layer below the substrate material, and an impurity attractant region disposed in the substrate material.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Harold W. Kennel, Patrick Morrow, Rishabh Mehandru, Stephen M. Cea
  • Patent number: 10937910
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Patent number: 10923530
    Abstract: An optoelectronic device including a substrate with first and second opposite surfaces; and electrical insulation side elements extending from the first surface to the second surface and defining, within the substrate, first semi-conductive or conductive portions which are electrically insulated from each other. The optoelectronic device also includes, for each first portion a first conductive contact pad on the second surface in contact with the first portion and a set of light-emitting diodes resting on the first surface and electrically connected to the first portion. The optoelectronic device also includes a conductive, at least partially transparent electrode layer covering all the light-emitting diodes; an insulating, at least partially transparent encapsulation layer covering the electrode layer; and at least one second conductive contact pad electrically connected to the electrode layer.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: February 16, 2021
    Assignee: Aledia
    Inventors: Xavier Hugon, Ivan-Christophe Robin
  • Patent number: 10923535
    Abstract: An organic semiconductor detector for detecting radiation has an organic conducting active region, an output electrode and a field effect semiconductor device. The field effect semiconductor device has a biasing voltage electrode and a gate electrode. The organic conducting active region is connected on one side to the field effect semiconductor device and is connected on another side to the output electrode.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: February 16, 2021
    Inventor: Michael Bardash
  • Patent number: 10903275
    Abstract: A method for manufacturing a semiconductor memory device includes forming a plurality of doped semiconductor layers in a stacked configuration on a dielectric layer. The plurality of doped semiconductor layers each comprise a single crystalline semiconductor material. In the method, a memory stack layer is formed on an uppermost doped semiconductor layer of the plurality of doped semiconductor layers, and the memory stack layer and a plurality of doped semiconductor layers are patterned into a plurality of pillars spaced apart from each other. The patterned plurality of doped semiconductor layers in each pillar of the plurality of pillars are components of a bipolar junction transistor device, and the plurality of pillars are parts of a memory cell array having a cross-point structure.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Tak H. Ning, Alexander Reznicek
  • Patent number: 10903186
    Abstract: An assembly that includes a first substrate, a second substrate, and a pair of bonding layers disposed between and bonded to the first and second substrates. The assembly further includes a solder layer disposed between the pair of bonding layers such that the solder layer is isolated from contacting the first substrate and the second substrate. The solder layer has a low melting temperature relative to a high melting temperature of the bonding layers. A coating is disposed over at least the pair of bonding layers and the solder layer such that the coating encapsulates the solder layer between the pair of bonding layers. The solder layer melts into a liquid form when the assembly operates at a temperature above the low melting temperature of the solder layer and the coating maintains the liquid form of the solder layer between the pair of bonding layers.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: January 26, 2021
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shailesh N. Joshi, Naoya Take
  • Patent number: 10892279
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a gate dielectric located between the memory opening fill structures and the electrically conductive layers. Each of the memory opening fill structures includes a vertical semiconductor channel, a conductive core electrode, and a memory film located between the vertical semiconductor channel and the conductive core electrode. The memory film contains a layer stack including a first tunneling dielectric contacting the vertical semiconductor channel, a second tunneling dielectric contacting the conductive core electrode, and a charge storage layer located between the first tunneling dielectric and the second tunneling dielectric.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: January 12, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Yukihiro Sakotsubo
  • Patent number: 10886396
    Abstract: A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SiC) MOSFET device.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: January 5, 2021
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Brett Hull
  • Patent number: 10886229
    Abstract: This invention is a laminated structure and methods used for electrically connecting one or more semiconductor chips to various external electrical connections where stresses within the laminated structure due to thermal cycle are reduced by adding conductive material to selected subareas of upper and lower layers in the structure such that the volume of conductive material in corresponding subareas is equal in amount and orientation within a threshold. This reduces differential stresses between the layers as temperature changes and accordingly reduces failures of materials and/or connections in the structure during manufacturing and operation.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hien P Dang, Sri M Sri-Jayantha
  • Patent number: 10878908
    Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: December 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Da Woon Jeong, Sung-Hun Lee, Seokjung Yun, Hyunmog Park, JoongShik Shin, Young-Bae Yoon