Abstract: The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack. The device stack includes a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer. The damascene etching process forms the trench opening having a bottom on the first etch stop layer.

Abstract: Some embodiments relate to an integrated circuit, comprising: a pixel, comprising: a photodetection region; and a drain configured to discard charge carriers from within a semiconductor region of the pixel outside of the photodetection region. Some embodiments relate to an integrated circuit, comprising: a pixel, comprising: a photodetection region; and a drain configured to discard charge carriers from the photodetection region, wherein the drain comprises a semiconductor region and the semiconductor region is contacted by a metal contact. Some embodiments relate to an integrated circuit, comprising: a pixel, comprising: a photodetection region; and a drain configured to discard charge carriers from the photodetection region, wherein the drain comprises a semiconductor region that to which electrical contact is made through a conductive path that does not include a polysilicon electrode.

Abstract: A semiconductor light receiving element in which a photodiode is formed on the main surface side of a first semiconductor substrate, and a cone ave mirror reflecting an incident light toward the light receiving element. The concave mirror comprises a flat first surface of the second semiconductor substrate that is transparent to the incident light, a convex surface formed in a convex shape toward the side opposite to the first surface on the second surface side opposite to the first surface, and a reflective film formed on the convex surface, and the incident light entering from the first surfaceside is reflected by the reflective film to a condensing positionnear the first surface, and the light receiving element was fixed to the first surface so as to overlap the light focusing position of the concave mirror.

Abstract: A method for forming a composite substrate containing layers of dissimilar materials is provided. The method includes a step of disposing a release layer over a base substrate where the base substrate is composed of a first material. A template layer is attached to the release layer. Characteristically, the template layer is composed of a second material and adapted to form a compound semiconductor device thereon.

Abstract: A display device includes a light emitting area, a non-light emitting area surrounding the light emitting area, and a separation area spaced apart from the light emitting area, the non-light emitting area disposed between the light emitting area and the separation area; a bank disposed in the non-light emitting area; a first alignment electrode and a second alignment electrode that extend from the light emitting area through the non-light emitting area to the separation area; light emitting elements electrically connected to at least one of the first alignment electrode and the second alignment electrode; a first contact electrode disposed in the separation area and electrically connected to the first alignment electrode; and a second contact electrode disposed in the separation area and electrically connected to the second alignment electrode.

Abstract: The method includes: providing a substrate, the substrate including a first region and a second region; forming an insulating layer on the substrate; etching a portion of the insulating layer in the second region, the insulating layer in the first region being configured as a first insulating layer, a remaining portion of the insulating layer in the second region being configured as a second insulating layer; forming a first barrier layer covering the first insulating layer and a second barrier layer covering the second insulating layer; etching the first barrier layer, a portion of the second barrier layer and the first insulating layer to form a through hole in the first insulating layer, and to form a hole segment in the second barrier layer; and removing the first barrier layer and the second barrier layer.

Abstract: An optical sensing apparatus is provided. The optical sensing apparatus includes a substrate, one or more pixels supported by the substrate, where each of the one or more pixels includes an absorption region, a field control region, a first contact region, a second contact region and a carrier confining region. The field control region and the first contact region are doped with a dopant of a first conductivity type. The second contact region is doped with a dopant of a second conductivity type. The carrier confining region includes a first barrier region and a channel region, where the first barrier region is doped with a dopant of the second conductivity type and has a first peak doping concentration, and where the channel region is intrinsic or doped with a dopant of the second conductivity type and has a second peak doping concentration lower than the first peak doping concentration.

Abstract: A SPAD-type photodiode comprising a depletion area in a first portion of a semiconductor substrate of a first conductivity type and further comprising a gate electrically-insulated from the substrate, extending into the substrate from an upper surface of the substrate, and separating the first portion of the substrate from a second portion. The photodiode further comprises a first region of the second conductivity type extending from the upper surface of the substrate into the second portion.

Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.

Abstract: A sensor device provided in the disclosure includes a sensor substrate, a first transparent layer, a collimator layer, and a lens. The first transparent layer is disposed on the sensor substrate, wherein the first transparent layer defines an alignment structure. The collimator layer is disposed on the first transparent layer. The lens is disposed on the collimator layer.

Abstract: A semiconductor structure comprises a semiconductor substrate including a first silicon substrate component having a first crystalline orientation and a second silicon substrate component over the first silicon substrate and having a second crystalline orientation different from the first crystalline orientation. The semiconductor substrate defines a trench extending through the second silicon substrate component and at least partially within the first silicon substrate component. A gallium nitride structure is disposed within the trench of the semiconductor substrate.

Abstract: A short-wave infra-red, SWIR, radiation detection device comprises: a first metallic layer providing a first set of connections from a readout circuit to respective cells of a matrix, the metallic layer reflecting SWIR wavelength radiation. Each matrix cell comprises at least one stack of layers including: a first layer of doped semiconductor material formed on the first metallic layer; an at least partially microcrystalline semiconductor layer formed over the first doped layer; a second layer of semiconductor material formed on the microcrystalline semiconductor layer; at least one microcrystalline semiconductor layer; and in some embodiments a second metallic layer interfacing the microcrystalline semiconductor layer(s), the interface being responsive to incident SWIR radiation to generate carriers within the stack. The stack has a thickness T=?/2N between reflective surfaces of the first and second metallic layers.

Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure with first material layers and second material layers that are alternately stacked with each other, forming a first opening that passes through the stacked structure, forming second openings between the first material layers, forming first sacrificial layers in the second openings, forming first isolation layers that protrude into the first opening by oxidizing the first sacrificial layers, forming mold patterns on the first material layers between the protruding portions of the first isolation layers, forming third openings by etching portions of the first isolation layers that are exposed between the mold patterns, forming second sacrificial layers in the third openings, and forming second isolation layers that protrude farther toward the center of the first opening than the mold patterns by oxidizing the second sacrificial layers.

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. An epitaxial pillar of SiGe or Ge extends upward from the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric layer is arranged over an upper surface of the substrate and is disposed around the lower epitaxial region to extend over outer edges of the well region. The dielectric layer has inner sidewalls that contact outer sidewalls of the epitaxial pillar. A dielectric sidewall structure has a bottom surface that rests on an upper surface of the dielectric layer and has inner sidewalls that extend continuously from the upper surface of the dielectric layer to a top surface of the epitaxial pillar.

Abstract: An array substrate includes a substrate, a first metal layer and an active layer disposed on the substrate, an interlayer insulating layer, and a second metal layer. The first metal layer forms at least one first trace, the interlayer insulating layer is disposed on the first metal layer and the active layer, the second metal layer is disposed on the interlayer insulating layer, the interlayer insulating layer is formed with a first contact hole, and the second metal layer is connected to the first trace through the first contact hole. The first metal layer includes a conductive layer and a first protective layer stacked in sequence.

Abstract: A photodetector includes a first APD that is sensitive to incident light and a second APD through which a constant current flows regardless of the incident light. One terminal of the first APD is electrically connected to one terminal of the second APD, another terminal of the first APD and another terminal of the second APD are connected to different power supplies, respectively, and the one terminal of the first APD and the one terminal of the second APD are both anodes or cathodes.

Abstract: An optical apparatus comprising an integrated germanium photodetector associated with a silicon nitride launch waveguide, the integrated germanium photodetector comprising a silicon layer, a germanium layer disposed atop the silicon layer, a plurality of conductive vias, at least one conductive via of the plurality of conductive vias being disposed atop the germanium layer, and a plurality of metal contacts each interconnected to each of the plurality of conductive vias; wherein the silicon nitride launch waveguide extends over a length of the silicon layer, and such that to create a coupling region between the silicon nitride launch waveguide and the germanium layer; and wherein, when an optical signal is launched into the silicon nitride launch waveguide, the optical signal is caused to be coupled into the integrated germanium photodetector at the coupling region, such that to be absorbed by the germanium layer.

Abstract: This Application discloses methods for fabricating and packaging avalanche photodiodes (APDs), particularly useful for high sensitivity Geiger-mode APDs formed using an array of micro-cells. The photodetector is formed on a semiconductor wafer of indium phosphide (InP) having epitaxial layers, including indium gallium arsenide (InGaAs) as the photodetecting layer, with n-doped InP to one side, and layers of InP incorporating p-doped regions on the opposite side. The p-doped regions may be used to define the array of micro-cells. The photodetector is packaged by etching a well into the epitaxial structure on the semiconductor wafer, allowing an electrode to be patterned that contacts the n-doped InP layer and another that contacts the p-doped InP regions. Flip-chip bonding techniques can then attach the semiconductor wafer to a stronger support substrate, which may additionally be configured with electronic circuitry positioned to electrically contact the electrodes on the semiconductor wafer surface.

Abstract: A package includes: a bottom portion having a mounting surface; and a lateral wall portion having a top surface and including: a lateral wall having a rectangular outer shape in a top view and surrounding the mounting surface, and a stepped portion formed along the lateral wall below the top surface. In the top view, the stepped portion includes a wide portion and a narrow portion that are two regions having different widths. The narrow portion is formed on a portion along a one side of an entire circumference of the lateral wall.

Abstract: Disclosed are a crystallization process of an oxide semiconductor, a method of manufacturing a thin film transistor including the same, a thin film transistor, a display panel, and an electronic device. The crystallization process of an oxide semiconductor includes forming an amorphous oxide semiconductor layer on a substrate, forming a crystallization auxiliary layer including a light absorbing inorganic material on the amorphous oxide semiconductor layer, and annealing the crystallization auxiliary layer to crystallize the amorphous oxide semiconductor layer.