Abstract: According to the present disclosure, techniques related to manufacturing and applications of power photodiode structures and devices based on group-III metal nitride and gallium-based substrates are provided. More specifically, embodiments of the disclosure include techniques for fabricating photodiode devices comprising one or more of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, structures and devices. Such structures or devices can be used for a variety of applications including optoelectronic devices, photodiodes, power-over-fiber receivers, and others.

Abstract: There is provided an element structure of an avalanche photodiode that can operate in a high gain state while having high reliability and low noise property. There is produced an avalanche photodiode including at least a multiplication layer and a light absorbing layer between first and second semiconductor contact layers, in which an area of the first semiconductor contact layer is at least smaller than an area of the multiplication layer, the avalanche photodiode having an electric field relaxation layer configured to be depleted at an operating voltage between the first semiconductor contact layer and the multiplication layer.

Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.

Abstract: Provided is a semiconductor light receiving element which can achieve a high-speed operation without sacrificing light receiving sensitivity while increasing the margin of a manufacturing process. The semiconductor light receiving element according to the present invention is characterized by comprising: a semiconductor layer doped with a first impurity; a semiconductor light absorption layer in which a band gap energy is adjusted to absorb incident light on the semiconductor layer doped with the first impurity; a semiconductor layer on the semiconductor light absorption layer and doped with a second impurity; and a metal electrode contacting side surfaces of the semiconductor layer doped with the second impurity, wherein side surfaces of the metal electrode are surfaces parallel to a growth direction of the semiconductor layer doped with the second impurity.

Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

Abstract: According to the present disclosure, techniques related to manufacturing and applications of power photodiode structures and devices based on group-III metal nitride and gallium-based substrates are provided. More specifically, embodiments of the disclosure include techniques for fabricating photodiode devices comprising one or more of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, structures and devices. Such structures or devices can be used for a variety of applications including optoelectronic devices, photodiodes, power-over-fiber receivers, and others.

Abstract: The present disclosure relates to an imaging element, a fabrication method, and electronic equipment by which an image having higher picture quality can be imaged. The imaging element includes a first light absorbing film formed in an effective pixel peripheral region, the effective pixel peripheral region being provided so as to enclose an outer side of an effective pixel region in which a plurality of pixels is disposed in a matrix, so as to cover a semiconductor substrate, a microlens layer provided as an upper layer than the first light absorbing film and having a microlens formed so as to condense light for each of the pixels in the effective pixel region, and a second light absorbing film provided as an upper layer than the microlens layer and formed in the effective pixel peripheral region. The present technology can be applied, for example, to a CMOS image sensor.

Abstract: Provided is a magnetic tunnel junction element including: a magnetization pinned layer having a fixed magnetization direction; a first insulating layer which is provided on the magnetization pinned layer and is formed of an insulating material; a magnetization free layer provided on the first insulating layer; an adjacent layer which is provided adjacent to the magnetization free layer and is formed of a non-magnetic transition metal; and a cap layer which is formed to have a multilayer structure including at least one barrier layer formed of a non-magnetic transition metal and is provided on the adjacent layer.

Abstract: The present disclosure pertains to the field of back contact heterojunction cell technologies, and particularly relates to a mask-layer-free hybrid passivation back contact cell and a fabrication method thereof; the method includes: S101: providing a silicon wafer substrate; S102: sequentially forming a first semiconductor layer and a mask layer on a back surface of the silicon wafer substrate, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer; S103: performing first etching on the first semiconductor layer on the obtained back surface to form first opening regions W1; S104: forming a textured surface in the first opening region W1 on the back surface by texturing and cleaning; S105: removing the mask layer; S106: forming a second semiconductor layer on the obtained back surface; and S107: performing second etching on a polished region of the obtained back surface.

Abstract: A display device includes a light-emitting layer and a red converting layer, the red converting layer includes a binder resin, red luminescent bodies, and In nanoparticles, each of the In nanoparticles includes a core and a silica shell, and the silica shell includes blue luminescent bodies emitting light having a wavelength shorter than that of red luminescent bodies.

Abstract: The present disclosure provides an array substrate, a display panel and a display device. The array substrate includes: a base substrate; a low temperature poly-silicon thin film transistor located on the base substrate and including a poly-silicon active layer and a first gate which are laminated on the base substrate; an oxide thin film transistor located on the base substrate and including an oxide active layer and a second gate which are laminated on the base substrate; and a light shielding layer, where an overlapping area of a projection of the light shielding layer on the base substrate and an orthographic projection of the oxide active layer on the base substrate is S1, an overlapping area of the projection of the light shielding layer on the base substrate and an orthographic projection of the poly-silicon active layer on the base substrate is S2, and S1 is greater than S2.

Abstract: A method and structure providing an optical sensor having an optimized Ge—Si interface includes providing a substrate having a pixel region and a logic region. In some embodiments, the method further includes forming a trench within the pixel region. In various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. In some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. In some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.

Abstract: Photodetectors based on colloidal quantum dots and methods of making the photodetectors are provided. Also provided are methods for doping films of colloidal quantum dots via a solid-state cation exchange method. The photodetectors include multi-band photodetectors composed of two or more rectifying photodiodes stacked in aback-to-back configuration. The doping methods rely on a solid-state cation exchange that employs sacrificial semiconductor nanoparticles as a dopant source for a film of colloidal quantum dots.

Abstract: A first n-type contact layer, a second n-type contact layer, a multiplication layer, an electric field control layer, a light absorbing layer, and a p-type contact layer are layered in this order on a substrate. The second n-type contact layer is formed between the first n-type contact layer and the light absorbing layer, is made to have an area smaller than that of the light absorbing layer in a plan view, and is disposed inside the light absorbing layer in a plan view.

Abstract: According to an aspect, a detection device includes: a substrate; a plurality of photodiodes arranged on a first principal surface of the substrate; a protective film that covers the photodiodes; a plurality of lenses provided for each of the photodiodes so as to face the photodiode with the protective film interposed between the lenses and the photodiodes; and a projection provided between the lenses. A top of the projection is located at a position higher than a top of each of the lenses when viewed from the first principal surface.

Abstract: The present disclosure provides a semiconductor device and a semiconductor component. The semiconductor device includes an active structure, a ring-shaped semiconductor contact layer, a first electrode, and an insulating layer. The active structure has a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer located between the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer. The ring-shaped semiconductor contact layer is located on the second-conductivity-type semiconductor layer and having a first inner sidewall and a first outer sidewall. The first electrode has an upper surface and covers the ring-shaped semiconductor contact layer. The insulating layer covers the first electrode and the active structure and has a second inner sidewall and a second outer sidewall. The first inner sidewall is not flush with the second inner sidewall in a vertical direction.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a S/D silicide layer formed on the S/D epitaxial layer, and the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width. The semiconductor structure includes a dielectric spacer between the gate structure and the S/D silicide layer, and a top surface of the dielectric spacer is lower than a top surface of the gate structure.

Abstract: A waveguide photodetector includes a first contact layer of a first conductivity type, a waveguide layer, and a second contact layer of a second conductivity type that are sequentially formed on the semiconductor substrate. The waveguide layer includes a first cladding layer of the first conductivity type disposed on a side of the first contact layer, a second cladding layer of the second conductivity type disposed on a side of the second contact layer, and the core layer disposed between the first cladding layer and the second cladding layer. The core layer includes a light absorption layer and an impurity-doped light absorption layer that has a higher concentration of a p-type impurity than that of the light absorption layer and is disposed on a side of a light incident face.

Abstract: Provided is a photodetector which can be manufactured in a standard process of a mass-produced CMOS foundry. The photodetector includes a silicon (Si) substrate; a lower clad layer; a core layer including a waveguide layer configured to guide signal light, and including a first Si slab doped with first conductive impurity ions and a second Si slab doped with second conductive impurity ions; a germanium (Ge) layer configured to absorb light and including a Ge region doped with the first conductive impurity ions; an upper clad layer; and electrodes respectively connected to the first and second Si slabs and the Ge region. A region of the core layer sandwiched between the first Si slab and the second Si slab operates as an amplification layer.

Abstract: An LED array comprises a first mesa comprising a top surface, at least a first LED including a first p-type layer, a first n-type layer and a first color active region and a tunnel junction on the first LED, a second n-type layer on the tunnel junction, the second n-type layer comprising at least one n-type III-nitride layer with >10% Al mole fraction and at least one n-type III-nitride layer with <10% Al mole fraction. The LED array further comprises an adjacent mesa comprising a top surface, the first LED, a second LED including the second n-type layer, a second p-type layer and a second color active region. A first trench separates the first mesa and the adjacent mesa, cathode metallization in the first trench and in electrical contact with the first and the second color active regions of the adjacent mesa, and anode metallization contacts on the n-type layer of the first mesa and on the anode layer of the adjacent mesa.