Abstract: A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.

Abstract: A method for manufacturing a solid state device with a self-forming nanogap includes patterning a first metallic layer (M1) to form a first electrode on a substrate; depositing a self-assembling monolayer, SAM, layer over and around the first electrode; forming a second metallic layer (M2) in contact with the SAM layer and the substrate; and touchlessly removing parts of the second metallic layer (M2) that is formed directly above the SAM layer, to form a second electrode, and a nanogap between the first electrode and the second electrode.

Abstract: There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device including an active pattern extending in a first direction, a gate structure on the active pattern, the gate structure extending in a second direction different from the first direction and including a gate insulating layer and a gate filling layer, a gate spacer extending in the second direction, on a sidewall of the gate structure, a gate shield insulating pattern on a sidewall of the gate spacer, covering an upper surface of the gate insulating layer, and including an insulating material, and a gate capping pattern covering an upper surface of the gate filling layer, on the gate structure may be provided.

Abstract: A semiconductor light-emitting element includes: an n-type semiconductor layer made of an n-type AlGaN-based semiconductor material; an active layer provided on the n-type semiconductor layer and made of an AlGaN-based semiconductor material; a p-type semiconductor layer provided on the active layer; a p-side contact electrode that includes a Rh layer in contact with an upper surface of the p-type semiconductor layer; and a p-side current diffusion layer that is in contact with an upper surface and a side surface of the p-side contact electrode and includes a TiN layer, a Ti layer, a Rh layer, and a TiN layer stacked successively. A film density of the Rh layer included in the p-side contact electrode is larger than a film density of the Rh layer included in the p-side current diffusion layer.

Abstract: An organic electroluminescent display device includes an auxiliary common voltage supply line disposed in a display area, and an auxiliary connection line interconnecting the auxiliary common voltage supply line and a cathode, in order to uniformly supply a common voltage to the display area, and the auxiliary connection line having a structure connectable to the cathode at an upper end of a spacer.

Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

Abstract: A trench-gate transistor device includes a substrate and a transistor structure. The transistor structure includes a plurality of superjunctions arranged in a first direction, a rectifying area that has at least one Schottky-based diode, and at least one active unit that is located at a side of said rectifying area in a second direction that intersects with the first direction.

Abstract: A photodiode and a related method of manufacture are disclosed. The photodiode includes a transfer gate and a floating diffusion adjacent to the transfer gate. In addition, the photodiode includes an upper terminal; an intrinsic semiconductor region in contact with the upper terminal, the intrinsic semiconductor region in a trench in a substrate adjacent to the transfer gate; and a lower terminal in contact with the intrinsic semiconductor region. An insulator layer is along an entirety of a sidewall of the intrinsic semiconductor region and between the intrinsic semiconductor region and the transfer gate. A p-type well may also optionally be between the insulator layer and the transfer gate.

Abstract: A detection base plate and a flat-panel detector. The detection base plate comprises multiple detection pixel units arranged in an array. Each detection pixel unit comprises: a thin-film transistor, a sacrificial layer and a photoelectric conversion part that are disposed on a substrate, wherein the sacrificial layer is located between the thin-film transistor and the photoelectric conversion part; the thin-film transistor comprises an active layer, a first electrode and a second electrode; at least part of an orthographic projection of the active layer on the substrate is located within an orthographic projection of the sacrificial layer on the substrate; and the photoelectric conversion part is electrically connected to the sacrificial layer and the first electrode. In the detection base plate, the sacrificial layers of the detection pixel units are mutually independent.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic module devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: Semiconductor devices and methods of forming the same include forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets. A second stack of nanosheets is formed in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets. A lower gate cut structure is formed between the lower first nanosheets and the lower second nanosheets. A gate stack is formed on the first and second stack of nanosheets after forming the lower gate cut structure. An upper gate cut structure is formed after forming the gate stack.

Abstract: A memory device includes at least one alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the at least one alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. The memory opening fill structure includes a lateral protrusion having a tapered sidewall surface; and one of the electrically conductive layers is a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening fill structure.

Abstract: Provided is an ultraviolet light receiving device having photosensitivity effective to target wavelengths in the ultraviolet region. A Schottky junction ultraviolet light receiving device has the photosensitivity peak wavelength in an ultraviolet region of 230 nm or more and 320 nm or less, and exhibits a rejection ratio of 105 or more, the rejection ratio being the ratio of the responsivity Rp to the peak photosensitivity wavelength to the average of the responsivity Rv to a visible region of 400 nm or more and 680 nm or less (Rp/Rv).

Abstract: An integrated circuit structure includes a substrate, an interconnect stack, a first memory array, and a source line. The interconnect stack is over the substrate. The first memory array is over the interconnect stack and includes memory elements stacked in a vertical direction each comprising a conductive layer. The first memory array further includes a memory layer electrically connecting to the conductive layers of the memory elements and extending downwardly from a topmost one of the conductive layers to a lowermost one of the conductive layers; and a channel layer extending along a sidewall of the memory layer. The source line is in contact with a top end of the channel layer and laterally extends across the first memory array.

Abstract: Provided is a high-quality substrate including a silicon layer, a multilayer buffer layer on the silicon layer, and an indium phosphide (InP) layer on the multilayer buffer layer, wherein a crystal growth direction of the silicon layer is a direction inclined by 1° to 10° with respect to a vertical direction, and wherein the multilayer buffer layer includes a buffer layer in which a crystal growth direction is inclined with respect to the vertical direction.

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

Abstract: Semiconductor lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The semiconductor lighting device also includes an indentation extending from the second semiconductor material toward the active region and the first semiconductor material and an insulating material in the indentation of the solid state lighting structure.

Abstract: Disclosed herein are avalanche photodiodes (APDs) particularly useful for high-sensitivity Geiger-mode APDs formed using an array of micro-cells. The photodetector is formed on a semiconductor substrate of indium phosphide (InP) having epitaxial layers, including indium gallium arsenide (InGaAs) as the photodetecting layer, with n-doped InP to one side, and layers of InP incorporating p-doped regions on the opposite side. The p-doped regions may serve to define an array of micro-cells, which may be arranged in a hexagonal pattern. A well may be etched through the epitaxial structures, allowing an electrode that contacts the n-doped InP layer and another that contacts the p-doped InP regions to be patterned on the same side of the detector. Flip-chip bonding techniques can then attach the semiconductor wafer to a stronger support substrate, which may additionally be configured with electronic circuitry positioned to electrically contact the electrodes on the semiconductor wafer surface.

Abstract: A display apparatus includes a circuit substrate with driving circuits and first bonding electrodes, and a pixel array having LED cells, each of the LED cells including first and second conductivity-type semiconductor layers with an active layer therebetween, second bonding electrodes on the first bonding electrodes, wavelength converters on the LED cells, an upper semiconductor layer on the LED cells and having a partition structure surrounding side snakes of the wavelength converters and separating the wavelength converters, a first reflective electrode on the side surfaces of the LED cells, spaced from the LED cells by a passivation layer, and extending between the LED cells, second reflective electrodes on the lower surfaces of the LED cells and connected to the second conductivity-type semiconductor layers, a common electrode on at least one side of the LED cells, and a pad electrode outside the LED cells and electrically connected to the driving circuits.

Abstract: A single-photon detection pixel includes a substrate, a first well provided in the substrate, a pair of heavily doped regions provided on the first well, and a contact provided between the pair of heavily doped regions, wherein the substrate and the pair of heavily doped regions have a first conductivity type, and the first well and the contact have a second conductivity type that is different from the first conductivity type.