Abstract: In a photodetector using GePDs, a photodetector having small change in light sensitivity due to temperature is provided. A photodetector includes a plurality of photodiodes formed on a silicon substrate and having germanium or a germanium compound in a light absorption layer, and two chips of integrated circuits arranged parallel to two sides connected to one corner of the silicon substrate, respectively, the two integrated circuits are connected to photodiodes formed on the silicon substrate, two or more of the photodiodes are arranged equidistantly from the integrated circuit that is parallel to one side connected to the one corner, and the numbers of equidistantly arranged photodiodes are equal, when viewed from the integrated circuits.

Abstract: A semiconductor photodiode (600) comprises a top side (602) with an active surface area (604) for light entry, a bottom side (606), a bulk structure (610) made of a single semiconductor material, the bulk structure comprising a p-type layer (612a) and an n-type layer (612b), which together form the p-n junction (612) of the photodiode, wherein one of the two layers of the p-n junction is an upper p-n junction layer (612a) and the other one is a lower p-n junction layer (612b), wherein the upper p-n junction layer (612a) is located proximate to the active surface area (604), and a semiconductor light absorption layer (614), wherein the light absorption layer (612a), (614) defines the active surface area (604) and is arranged on top of the bulk structure (610), above the upper p-n junction layer (612a), and the semiconductor material of the light absorption layer (614) is different from the semiconductor material of the bulk structure (610), the light absorption layer (614) and the upper p-n junction layer (612

Abstract: A plasmonic field-enhanced photodetector is disclosed. The photodetector absorbs surface plasmon polaritons (SPPs) by using a light absorbing layer having a conduction band and a valence band in which an energy is split, the SPPs being generated by combining surface plasmons (SPs) with photons of a light wave, and generates photocurrent based on the absorbed SPPs.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic module devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: The present disclosure describes methods of forming a colored conductive ribbon for a solar module which includes combining a conductive ribbon with a channeled ribbon holder, applying a color coating to at least the conductive ribbon within the channel, curing the color coating on the conductive ribbon, and separating the conductive ribbon from the channeled holder.

Abstract: An electronic device includes a semiconductor nanoparticle, and a method of manufacturing the semiconductor nanoparticle is additionally provided. The semiconductor nanoparticle includes: a core including a first element; and a shell covering at least a portion of a surface of the core and including a second element and a third element, wherein the first element, the second element, and the third element are different from each other, and the first element and the second element are chemically bonded to each other on the at least a portion of the surface of the core.

Abstract: The present disclosure provides a pixel unit, wherein common signal lines connected to shared thin film transistors located in lens areas are constructed as first common signal lines, and common signal lines connected to shared thin film transistors located in lens splicing areas are constructed as second common signal lines. The pixel unit provided by the present disclosure can independently adjust partial voltages of the shared thin film transistors in the lens areas and the lens splicing areas, thereby relieving deterioration of Lens-Mura occurring in the lens splicing areas.

Abstract: An opto-electronic device includes a base portion, a first electrode and a second electrode formed on an upper surface of the base portion apart from each other, a quantum dot layer, and a bank structure. The quantum dot layer is between the first electrode and the second electrode on the base portion and includes a plurality of quantum dots. The bank structure covers at least partial regions of the first electrode and the second electrode, defines a region where the quantum dot layer is formed, and is formed of an inorganic material.

Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.

Abstract: A semiconductor light-receiving element (50) is a semiconductor light-receiving element in which a multi-plication layer (2), an electric-field control layer (3), a light absorption layer (4) and a window layer (5) are sequentially formed on a semiconductor substrate (1), and a p-type region (6) is formed in the window layer (5). The p-type region (6) has a first p-type portion (14) and a second p-type portion (15) whose current multiplication factor due to light incidence is larger than that of the first p-type portion (14). The first p-type portion (14) is formed as a central portion of the p-type region (6), the central portion including a central axis (21c) perpendicular to the semiconductor substrate (1), and the second p-type portion (15) is formed on an outer periphery of the central portion in a radial direction about the central axis (21c).

Abstract: A sensor includes a first electrode and a second electrode, and a photo-active layer between the first electrode and the second electrode. The photo-active layer includes a light absorbing semiconductor configured to form a Schottky junction with the first electrode. The photo-active layer has a charge carrier trapping site configured to capture photo-generated charge carriers generated based on the light absorbing semiconductor absorbing incident light that enters at least the photo-active layer at a position adjacent to the first electrode. The sensor is configured to have an external quantum efficiency (EQE) that is adjusted based on a voltage bias being applied between the first electrode and the second electrode.

Abstract: At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.

Abstract: A display device includes a substrate including a first surface, and a second surface positioned at a side opposite to the first surface; a first light-emitting element located at a lateral side of the substrate; a plurality of light-receiving elements located at a second surface side of the substrate; a plurality of second light-emitting elements located on the first surface of the substrate; and a first drive element controlling driving of the second light-emitting elements based on output of the light-receiving elements. A light-emitting surface of the first light-emitting element is oriented in a first direction. The first direction is parallel to a direction from the first surface toward the second surface. Light-emitting surfaces of the second light-emitting elements are oriented in a second direction. The second direction is from the second surface toward the first surface.

Abstract: A device includes a semiconductor fin, an isolation structure, a gate structure, source/drain structures, a sensing contact, a sensing pad structure, and a reading contact. The semiconductor fin includes a channel region and source/drain regions on opposite sides of the channel region. The isolation structure laterally surrounds the semiconductor fin. The gate structure is over the channel region of the semiconductor fin. The source/drain structures are respectively over the source/drain regions of the semiconductor fin. The sensing contact is directly on the isolation structure and adjacent to the gate structure. The sensing pad structure is connected to the sensing contact. The reading contact is directly on the isolation structure and adjacent to the gate structure.

Abstract: A coplanar waveguide structure includes a dielectric layer disposed over at least a portion of a substrate and a planar transmission line disposed within the dielectric layer. In some instances, the planar transmission line can include a conductive signal line and one or more ground lines. In other instances, the planar transmission line may include a conductive stacked signal line and one or more stacked ground lines.

Abstract: The present disclosure provides an integrated infrared circular polarization detector with a high extinction ratio and a design method thereof. The detector structurally includes a metal reflective layer, a bottom electrode layer, a quantum well layer, a top electrode layer, and a two-dimensional chiral metamaterial layer. Under circularly polarized light with the selected handedness, surface plasmon polariton waves are generated at the interface between the two-dimensional chiral metamaterial layer and the semiconductor, and has a main electric field component aligned with the absorption direction of the quantum wells, thereby enhancing the absorption of the quantum wells. Under circularly polarized light with the opposite handedness, since most of the optical power is reflected, surface plasmon polariton waves cannot be effectively excited, and the absorption of the quantum wells is extremely low, thus realizing the capability of infrared circular polarization detection with a high extinction ratio.

Abstract: A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N×analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.

Abstract: The invention relates to an infrared-transmitting high-sensitivity visible light detector and its preparation method. The detector is composed of passivation layer (14), upper electrode (13), heterojunction (15), lower electrode (3), and intrinsic monocrystalline silicon substrate (2). The upper electrode (13) is the material that is electrically conductive and transparent to visible light and infrared light. The heterojunction (15) is divided into heterojunction upper layer (5) and heterojunction lower layer (4), wherein the upper heterojunction layer (5) is a nano film sensitive to visible light and capable of transmitting infrared ray, and the lower heterojunction layer (4) is intrinsic monocrystalline silicon.

Abstract: Various embodiments relate to a superlattice photodetector and a method of manufacturing the same. The superlattice photodetector includes an absorption layer for absorbing incident light and a waveguide layer coupled with the absorption layer and enabling the incident light to be waveguided within the absorption layer. The waveguide layer may include a periodic structure in which a plurality of metal patterns and a plurality of dielectric patterns are repeatedly arranged. According to various embodiments, the superlattice photodetector can be thinned while having improved performance.