Abstract: An avalanche photodiode (APD) device, in particular, a lateral separate absorption charge multiplication (SACM) APD device, and a method for its fabrication is provided. The APD device comprises a first contact region and a second contact region formed in a semiconductor layer. Further, the APD device comprises an absorption region formed on the semiconductor layer, wherein the absorption region is at least partly formed on a first region of the semiconductor layer, wherein the first region is arranged between the first contact region and the second contact region. The APD device further includes a charge region formed in the semiconductor layer between the first region and the second contact region, and an amplification region formed in the semiconductor layer between the charge region and the second contact region. At least the absorption region is curved on the semiconductor layer.

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

Abstract: This invention provides a light-concentrating structure with photosensitivity enhancing effect, including the substrate, buried layer, first electrode layer, second electrode layer, dielectric layer and interconnection structure. The substrate is equipped with a housing space; the buried layer is arranged above the substrate with the housing space; the first electrode layer is arranged above the buried layer; the second electrode layer is arranged in the middle of the first electrode layer; the dielectric layer is arranged above the second electrode layer; the interconnection structure is arranged above the substrate and the first electrode layer surrounding the dielectric layer, which forms an opening and a light-concentrating recess groove.

Abstract: A semiconductor device includes a semiconductor substrate, a pair of source/drain regions on the semiconductor substrate, and a gate structure on the semiconductor substrate and between the pair of source/drain regions. The gate structure includes a first metal layer and a second metal layer in contact with the first metal layer. A sidewall of the first metal layer and a top surface of the semiconductor substrate form a first included angle, a sidewall of the second metal layer and the top surface of the semiconductor substrate form a second included angle. The second included angle is different from the first included angle.

Abstract: A photo detector having a substrate and a first structure formed on the substrate. The first structure includes an emitter layer formed on the substrate and a base layer formed on the emitter layer. Further, the first structure includes a collector layer formed on the base layer. The collector layer has a plasmonic structure. The plasmonic structure includes a first plurality of mesa structures. Each of the mesa structures of the first plurality of mesa structures includes a second plurality of mesa structures having ridges arranged in a regularly repeating pattern.

Abstract: An IC structure includes a semiconductor fin, first and second gate structures, and an isolation structure. The semiconductor fin extends from a substrate. The first gate structure extends above a top surface of the semiconductor fin by a first gate height. The second gate structure is over the semiconductor fin. The isolation structure is between the first and second gate structures, and has a lower dielectric portion embedded in the semiconductor fin and an upper dielectric portion extending above the top surface of the semiconductor fin by a height that is the same as the first gate height. When viewed in a cross section taken along a longitudinal direction of the semiconductor fin, the upper dielectric portion of the isolation structure has a rectangular profile with a width greater than a bottom width of the lower dielectric portion of the isolation structure.

Abstract: A single photon avalanche diode (SPAD) device comprises: a silicon layer; an active region in said silicon layer for detecting incident light; and a blocking structure overlapping said active region for blocking incident light having a wavelength at least in the range of 200 nm to 400 nm, so that light having said wavelength can only be detected by said SPAD device when incident upon a region of said silicon layer outside of said active region.

Abstract: According to the present disclosure, techniques related to manufacturing and applications of power photodiode structures and devices based on group-III metal nitride and gallium-based substrates are provided. More specifically, embodiments of the disclosure include techniques for fabricating photodiode devices comprising one or more of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, structures and devices. Such structures or devices can be used for a variety of applications including optoelectronic devices, photodiodes, power-over-fiber receivers, and others.

Abstract: According to the present disclosure, techniques related to manufacturing and applications of power photodiode structures and devices based on group-III metal nitride and gallium-based substrates are provided. More specifically, embodiments of the disclosure include techniques for fabricating photodiode devices comprising one or more of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, structures and devices. Such structures or devices can be used for a variety of applications including optoelectronic devices, photodiodes, power-over-fiber receivers, and others.

Abstract: A combination structure includes a hybrid nanostructure array and a light-absorbing layer adjacent to the hybrid nanostructure array. The hybrid nanostructure array includes a plurality of hybrid nanostructures, each hybrid nanostructure includes a stack of a first nanostructure and a second nanostructure. The first nanostructure includes a first material. The second nanostructure includes a second material. The second material has a refractive index that is higher than a refractive index of the first material. The light-absorbing layer includes a near-infrared absorbing material configured to absorb light of at least a portion of a near-infrared wavelength spectrum.

Abstract: An image sensor with embedded wells for accommodating light emitters includes a semiconductor substrate including an array of doped sensing regions respectively corresponding to an array of photosensitive pixels of the image sensor. The semiconductor substrate forms an array of wells. Each well is aligned with a respective doped sensing region to facilitate detection, by the photosensitive pixel that includes said respective doped sensing region, of light emitted to the photosensitive pixel by a light emitter disposed in the well. The image sensor further includes, between adjacent doped sensing regions, a light-blocking barrier to reduce propagation of light to the doped sensing-region of each photosensitive pixel from wells not aligned therewith.

Abstract: A sensor includes a first electrode and a second electrode, and a photo-active layer between the first electrode and the second electrode. The photo-active layer includes a light absorbing semiconductor configured to form a Schottky junction with the first electrode. The photo-active layer has a charge carrier trapping site configured to capture photo-generated charge carriers generated based on the light absorbing semiconductor absorbing incident light that enters at least the photo-active layer at a position adjacent to the first electrode. The sensor is configured to have an external quantum efficiency (EQE) that is adjusted based on a voltage bias being applied between the first electrode and the second electrode.

Abstract: An apparatus for light detection includes a light, or photon, detector assembly and a dielectric resonator layer coupled to the detector assembly. The dielectric resonator layer is configured to receive transmission of incident light that is directed into the detector assembly by the dielectric resonator layer. The dielectric resonator layer resonates with a range of wavelengths of the incident light.

Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic module devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.

Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The S/D epitaxial layer includes a first S/D epitaxial layer and a second epitaxial layer. The semiconductor structure includes a gate spacer formed on a sidewall surface of the gate structure, and the gate spacer is directly over the first S/D epitaxial layer. The semiconductor structure includes a dielectric spacer formed adjacent to the gate spacer, and the dielectric spacer is directly over the second epitaxial layer.

Abstract: A diode device may be provided, including a semiconductor substrate including a well region arranged therein, a first doped region and a second doped region arranged within the well region, a first contact region arranged within the first doped region, and an isolation structure arranged within the first doped region, where an oxide layer may line a surface of the isolation structure. The first doped region and the first contact region may have a first conductivity type, and the well region and the second doped region may have a second conductivity type different from the first conductivity type. A doping concentration of the first contact region may be higher than a doping concentration of the first doped region, and a part of the first doped region may be arranged between the first contact region and the well region.

Abstract: A sealing structure (200) seals a light emitting unit (140) and includes a first inorganic film (210), a second inorganic film (220), a first resin-containing film (230), and a second resin-containing film (240). The film thickness of the first inorganic film (210) is equal to or greater than 1 nm and equal to or less than 300 nm. The first resin-containing film (230) is in contact with the first inorganic film (210) and includes a first resin. The second inorganic film (220) is positioned on an opposite side of the first inorganic film (210) with the first resin-containing film (230) interposed between the first and second inorganic films. The second resin-containing film (240) is positioned between the first resin-containing film (230) and the second inorganic film (220) and is in contact with the second inorganic film (220). The second resin-containing film (240) includes a second resin.