Abstract: A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.

Abstract: A semiconductor device for infrared detection comprises a stack of a first semiconductor layer, a second semiconductor layer and an optical coupling layer. The first semiconductor layer has a first type of conductivity and the second semiconductor layer has a second type of conductivity. The optical coupling layer comprises an optical coupler and at least a first lateral absorber region. The optical coupler is configured to deflect incident light towards the first lateral absorber region. The first lateral absorber region comprises an absorber material with a bandgap Eg in the infrared, IR.

Abstract: An avalanche diode including a gain region and a readout structure including an n-type (p-type) region having electrically isolated segments each including implanted regions; a p-type (n-type) region; and a first electrode on each of the segments. The gain region includes a p-n junction buried between the n-type region and the p-type region: an n+-type region having a higher n-type dopant density than the n-type region; a p+-type region having a higher p-type dopant density than the p-type region; and the p-n junction between the n+-type region and the p+-type region. A bias between the first electrodes and a second electrode (ohmically contacting the p-type (n-type) region) reverse biases the p-n junction. Electrons generated in response to electromagnetic radiation or charged particles generate additional electrons m the gain region through impact ionization but the segmented region comprises a low field region isolating the gain region from the first electrodes.

Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

Abstract: A semiconductor package includes a semiconductor chip structure that includes an image sensor chip and a logic chip that contact each other, a transparent substrate disposed on the semiconductor chip structure, and an adhesive structure disposed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate. The adhesive structure includes a first adhesive segment disposed on a top surface of the semiconductor chip structure and a second adhesive segment disposed on a bottom surface of the transparent substrate. The second adhesive segment covers top and lateral surfaces of the first adhesive segment. The image sensor chip is closer to the transparent substrate than the logic chip.

Abstract: A problem to be solved is to prevent deterioration of a signal-to-noise ratio. A photodetector according to the present invention is a germanium photodetector (Ge PD) that uses germanium or a germanium compound in a light absorption layer, the photodetector including a resistor connected in series with a cathode or an anode of the Ge PD; and a capacitor connected at one end to a connection point between the resistor and a cathode or anode of the Ge PD and grounded at another end, another connection point of the resistor being connected to a bias power supply, wherein to withstand maximum operating optical input power, the value of the resistor is determined such that electric power applied to the Ge PD will be lower than a breakdown threshold.

Abstract: The optical sensor includes a substrate, a first transistor for functioning as a light-receiving element and a second transistor for writing/reading in a pixel region provided on the substrate. The first transistor is formed by a transistor using polycrystalline silicon, the second transistor is formed by a transistor using an oxide semiconductor. A light-shielding layer is provided on the back side of the oxide semiconductor of the second transistor. Thus, it is possible to irradiate light to the optical sensor fora long time, and in addition to increasing the amount of light received by the first transistor, it is possible to suppress variations in the characteristics of the second transistor.

Abstract: A plasmonic field-enhanced photodetector is disclosed. The photodetector absorbs surface plasmon polaritons (SPPs) by using a light absorbing layer having a conduction band and a valence band in which an energy is split, the SPPs being generated by combining surface plasmons (SPs) with photons of a light wave, and generates photocurrent based on the absorbed SPPs.

Abstract: In a photodetector using GePDs, a photodetector having small change in light sensitivity due to temperature is provided. A photodetector includes a plurality of photodiodes formed on a silicon substrate and having germanium or a germanium compound in a light absorption layer, and two chips of integrated circuits arranged parallel to two sides connected to one corner of the silicon substrate, respectively, the two integrated circuits are connected to photodiodes formed on the silicon substrate, two or more of the photodiodes are arranged equidistantly from the integrated circuit that is parallel to one side connected to the one corner, and the numbers of equidistantly arranged photodiodes are equal, when viewed from the integrated circuits.

Abstract: A semiconductor photodiode (600) comprises a top side (602) with an active surface area (604) for light entry, a bottom side (606), a bulk structure (610) made of a single semiconductor material, the bulk structure comprising a p-type layer (612a) and an n-type layer (612b), which together form the p-n junction (612) of the photodiode, wherein one of the two layers of the p-n junction is an upper p-n junction layer (612a) and the other one is a lower p-n junction layer (612b), wherein the upper p-n junction layer (612a) is located proximate to the active surface area (604), and a semiconductor light absorption layer (614), wherein the light absorption layer (612a), (614) defines the active surface area (604) and is arranged on top of the bulk structure (610), above the upper p-n junction layer (612a), and the semiconductor material of the light absorption layer (614) is different from the semiconductor material of the bulk structure (610), the light absorption layer (614) and the upper p-n junction layer (612

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: Techniques for realizing compound semiconductor (CS) optoelectronic devices on silicon (Si) substrates are disclosed. The integration platform is based on heteroepitaxy of CS materials and device structures on Si by direct heteroepitaxy on planar Si substrates or by selective area heteroepitaxy on dielectric patterned Si substrates. Following deposition of the CS device structures, device fabrication steps can be carried out using Si complimentary metal-oxide semiconductor (CMOS) fabrication techniques to enable large-volume manufacturing. The integration platform can enable manufacturing of optoelectronic module devices including photodetector arrays for image sensors and vertical cavity surface emitting laser arrays.

Abstract: The present disclosure describes methods of forming a colored conductive ribbon for a solar module which includes combining a conductive ribbon with a channeled ribbon holder, applying a color coating to at least the conductive ribbon within the channel, curing the color coating on the conductive ribbon, and separating the conductive ribbon from the channeled holder.

Abstract: An electronic device includes a semiconductor nanoparticle, and a method of manufacturing the semiconductor nanoparticle is additionally provided. The semiconductor nanoparticle includes: a core including a first element; and a shell covering at least a portion of a surface of the core and including a second element and a third element, wherein the first element, the second element, and the third element are different from each other, and the first element and the second element are chemically bonded to each other on the at least a portion of the surface of the core.

Abstract: An opto-electronic device includes a base portion, a first electrode and a second electrode formed on an upper surface of the base portion apart from each other, a quantum dot layer, and a bank structure. The quantum dot layer is between the first electrode and the second electrode on the base portion and includes a plurality of quantum dots. The bank structure covers at least partial regions of the first electrode and the second electrode, defines a region where the quantum dot layer is formed, and is formed of an inorganic material.

Abstract: A semiconductor light-receiving element (50) is a semiconductor light-receiving element in which a multi-plication layer (2), an electric-field control layer (3), a light absorption layer (4) and a window layer (5) are sequentially formed on a semiconductor substrate (1), and a p-type region (6) is formed in the window layer (5). The p-type region (6) has a first p-type portion (14) and a second p-type portion (15) whose current multiplication factor due to light incidence is larger than that of the first p-type portion (14). The first p-type portion (14) is formed as a central portion of the p-type region (6), the central portion including a central axis (21c) perpendicular to the semiconductor substrate (1), and the second p-type portion (15) is formed on an outer periphery of the central portion in a radial direction about the central axis (21c).

Abstract: The present disclosure provides a pixel unit, wherein common signal lines connected to shared thin film transistors located in lens areas are constructed as first common signal lines, and common signal lines connected to shared thin film transistors located in lens splicing areas are constructed as second common signal lines. The pixel unit provided by the present disclosure can independently adjust partial voltages of the shared thin film transistors in the lens areas and the lens splicing areas, thereby relieving deterioration of Lens-Mura occurring in the lens splicing areas.

Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.

Abstract: A sensor includes a first electrode and a second electrode, and a photo-active layer between the first electrode and the second electrode. The photo-active layer includes a light absorbing semiconductor configured to form a Schottky junction with the first electrode. The photo-active layer has a charge carrier trapping site configured to capture photo-generated charge carriers generated based on the light absorbing semiconductor absorbing incident light that enters at least the photo-active layer at a position adjacent to the first electrode. The sensor is configured to have an external quantum efficiency (EQE) that is adjusted based on a voltage bias being applied between the first electrode and the second electrode.

Abstract: At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.