Patents Examined by Son Dinh
  • Memory system and writing method
    Patent number: 9830983
    Abstract: A nonvolatile memory device includes memory cells, bit lines, a word line, and a control unit performing a write operation in first and second stages. During the first stage, the control unit applies voltages to the word line and the bit lines based on first page of data to maintain threshold voltages for a first group of memory cells and shift the threshold voltages for a second group of memory cells above a first threshold. During the second stage, the control unit applies voltages to the word line and the bit lines based on second and third pages of data to shift the threshold voltages of memory cells in the first group to threshold voltages in one of first, second, and third threshold voltage ranges and the threshold voltages of memory cells in the second group to threshold voltages in one of fourth, fifth, sixth, and seventh threshold voltage ranges.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: November 28, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Memory macro and method of operating the same
    Patent number: 9824729
    Abstract: A memory macro includes a first memory cell array, a first tracking circuit and a first pre-charge circuit. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line coupled to the first set of memory cells and the second set of memory cells. The first set of pull-down cells and the first set of loading cells are configured to track a memory cell of the first memory cell array. The first pre-charge circuit is coupled to the first tracking bit line, and is configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third set of control signals.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Pankaj Aggarwal, Jhon Jhy Liaw
  • Memory device with combined non-volatile memory (NVM) and volatile memory
    Patent number: 9823874
    Abstract: The present disclosure provides embodiments for methods and memory devices. One embodiment of a memory device includes a first volatile memory cell having a first volatile access transistor with a current electrode coupled with a first volatile bit line; a first non-volatile memory cell having a first non-volatile access transistor with a current electrode coupled with a first non-volatile bit line; and a transfer circuit coupled between the first volatile bit line and the first non-volatile bit line. The transfer circuit is configured to: couple data latched from the first volatile bit line with the first non-volatile bit line during a store operation, and couple the first volatile bit line with the first non-volatile bit line during a restore operation.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: November 21, 2017
    Assignee: NXP USA, Inc.
    Inventors: Michael A. Sadd, Anirban Roy
  • Methods and apparatus to reduce threshold voltage drift
    Patent number: 9824767
    Abstract: A disclosed example to reduce a threshold voltage drift of a selector device of a memory cell includes providing an applied voltage to the selector device of the memory cell, the applied voltage being less than a threshold voltage of the selector device, and reducing the threshold voltage drift of the memory cell by maintaining the applied voltage at the selector device for a thresholding duration to activate the selector device.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Davide Mantegazza, Feng Pan, Prashant S. Damle, Hanmant Pramod Belgal, Kiran Pangal
  • Semiconductor memory device and method for driving the same
    Patent number: 9825042
    Abstract: In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m_1 or the like). Further, each cell includes selection transistors STr1_n_m and STr2_n_m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2_n_m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Self-referenced memory device and method using spin-orbit torque for reduced size
    Patent number: 9818465
    Abstract: A self-referenced MRAM cell comprises a first portion of a magnetic tunnel junction including a storage layer; a second portion of the magnetic tunnel junction portion including a tunnel barrier layer, a sense layer and a seed layer; the seed layer comprising a material having high spin-orbit coupling such that passing a sense current along the plane of the sense layer and/or seed layer exerts a spin-orbit torque adapted for switching a sense magnetization of the sense layer. A memory device comprising a plurality of the MRAM cells and a method for operating the memory device are also disclosed.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: November 14, 2017
    Assignee: CROCUS TECHNOLOGY SA
    Inventor: Sebastien Bandiera
  • Block management in non-volatile memory system with non-blocking control sync system
    Patent number: 9817593
    Abstract: In a non-volatile memory system, the controller maintains in its volatile memory two free block lists for the assignment of memory circuit blocks when writing user and system data. Copies of the free block lists are maintained in the non-volatile memory. While allocating blocks from a first of the free block lists, the controller can update a second of the free block lists as part of a control sync operation preparing control data stored in non-volatile memory. This allows the memory system to operate in a non-blocking manner during the control sync. Once the second free block lists is prepared and the control sync completed, the second block can subsequently be used for block allocations and a control sync operation can be done to update the first block.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: November 14, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Karin Inbar, Einat Lev, Michael Yonin
  • Achieving consistent read times in multi-level non-volatile memory
    Patent number: 9811269
    Abstract: Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventors: Anand S. Ramalingam, Pranav Kalavade
  • Cell structure of 4T random access memory, random access memory and operation methods
    Patent number: 9812190
    Abstract: The present disclosure provides a cell structure, a random access memory and operation methods. The cell structure with four transistors, including a first N-type transistor, a first P-type transistor, a second N-type transistor and a second P-type transistor, in which an absolute value of a threshold voltage of the first N-type transistor is greater than an absolute value of a threshold voltage of the second N-type transistor, and an absolute value of a threshold voltage of the first P-type transistor is greater than an absolute value of a threshold voltage of the second P-type transistor. The random access memory, including: two identical memory cell arrays including the cell structure with four transistors, a data write circuit and a data read circuit, by using Two Modular Redundancy harden method, and thus reading correctly and avoiding the mistake reversal caused by the single event upset effect.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: November 7, 2017
    Assignees: TSINGHUA UNIVERSITY, GRADUATE SCHOOL AT SHENZHEN, TSINGHUA UNIVERSITY
    Inventors: Liyang Pan, Xinhong Hong, Dong Wu
  • Memory apparatus with post package repair
    Patent number: 9805828
    Abstract: Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. The control circuit, in a second repair mode, receives second repair address information and provides the second repair address information to the storage latch circuit and disables storing the second address information into the non-volatile storage element.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 31, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Hideyuki Yoko
  • Memory module set having offset memory module units facilitating pin connections to main IC, and semiconductor memory device and system including the same
    Patent number: 9799411
    Abstract: A memory module set includes a main integrated circuit (IC) for transmitting and receiving an electrical signal, a first group of memory modules including at least one memory module having a first pin unit connected to the main IC, and a second group of memory modules including at least one memory module having a second pin unit connected to the main IC. The groups of memory modules and the main IC are arrayed in a first direction on a substrate, and the second group of memory modules is offset with respect to the first group of memory modules in a second direction that is perpendicular to the first direction so as to have a position relative to the main IC in the second direction that is different from that of the first group of memory modules.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: October 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Cheol Hong, Young-Jin Cho, Dong-Gi Lee, Hee-Chang Cho
  • Multi-bit MRAM cell and method for writing and reading to such MRAM cell
    Patent number: 9799384
    Abstract: A multi-bit magnetic random access memory (MRAM) cell including a magnetic tunnel junction including: a first magnetic storage layer, a second magnetic storage layer, a magnetic sense layer, a first spacer layer between the first magnetic storage layer and the magnetic sense layer, and a second spacer layer between the second magnetic storage layer and the sense layer. The first and second storage magnetization are switchable between m directions to store data corresponding to one of m2 logic states, with m>2. The present disclosure further concerns a method for writing and reading to the MRAM cell and to memory devices including multi-bit MRAM cells.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: October 24, 2017
    Assignee: CROCUS TECHNOLOGY SA
    Inventor: Quentin Stainer
  • Double-polarity memory read
    Patent number: 9799381
    Abstract: Circuits, systems, and methods for double-polarity reading of double-polarity stored data information are described. In one embodiment, a method involves applying a first voltage with a first polarity to a plurality of the memory cells. The method involves applying a second voltage with a second polarity to one or more of the plurality of memory cells. The method involves detecting electrical responses of the one or more memory cells to the first voltage and the second voltage. The method also involves determining a logic state of the one or more memory cells based on the electrical responses of the one or more memory cells to the first voltage and the second voltage.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: October 24, 2017
    Assignee: Intel Corporation
    Inventors: Innocenzo Tortorelli, Federico Pio
  • Sense amplifier in low power and high performance SRAM
    Patent number: 9799395
    Abstract: A static random access memory (SRAM) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns. The rows correspond to word lines and the columns correspond to bit lines. The first sense amplifier includes a first transistor and a second transistor. The first sense amplifier is configured to provide a first read of a first storage cell of the array of storage cells. Based on the first read of the first storage cell failing to correctly read data stored in the first storage cell, the first sense amplifier is configured to increment a body bias of the first transistor a first time. In response to the body bias of the first transistor being incremented, the first sense amplifier is configured to provide a second read of the first storage cell.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 24, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Vinod Menezes
  • Active boundary quilt architecture memory
    Patent number: 9792958
    Abstract: Methods, systems, and apparatus that increase available memory or storage using active boundary areas in quilt architecture are described. A memory array may include memory cells overlying each portion of a substrate layer that includes certain types of support circuitry, such as decoders and sense amplifiers. Active boundary portions, which may be elements of the memory array having a different configuration from other portions of the memory array, may be positioned on two sides of the memory array and may increase available data in a quilt architecture memory. The active boundary portions may include support components to access both memory cells of neighboring memory portions and memory cells overlying the active boundary portions. Address scrambling may produce a uniform increase in number of available data in conjunction with the active boundary portions.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: October 17, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Christophe Vincent Antoine Laurent
  • Phase change memory current
    Patent number: 9792986
    Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: October 17, 2017
    Assignee: INTEL CORPORATION
    Inventors: Mase J. Taub, Sandeep K. Guliani, Kiran Pangal, Raymond W. Zeng
  • Semiconductor memory device that determines a deterioration level of memory cells and an operation method thereof
    Patent number: 9786381
    Abstract: A semiconductor memory device includes a memory cell unit including a plurality of blocks, each of the blocks including a plurality of pages, and a circuit configured to count a number of activated or non-activated memory cells in one or more pages when a first voltage is applied to gates of memory cells of said one or more pages to read data therefrom, count a number of activated or non-activated memory cells in said one or more pages when a second voltage different from the first voltage is applied to the gates of the memory cells of said one or more pages to read data therefrom, compare the counted numbers, and store, in a register, data about deterioration of the memory cells of said one or more pages depending on a comparison result.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: October 10, 2017
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshiki Terabayashi
  • Semiconductor memory device
    Patent number: 9786670
    Abstract: To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band gap of 2.5 eV or higher is used for a DRAM, so that a retention period of potentials in a capacitor can be extended. Further, a memory cell has n capacitors with different capacitances and the n capacitors are each connected to a corresponding one of n data lines, so that a variety of the storage capacitances can be obtained and multilevel data can be stored. The capacitors may be stacked for reducing the area of the memory cell.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: October 10, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toshihiko Saito
  • Semiconductor storage device and processor system
    Patent number: 9779024
    Abstract: A semiconductor storage device has a non-volatile memory, a memory controller to carry out write processing to the non-volatile memory using a write pulse, and a write pulse controller to select one of a first write mode for writing to the non-volatile memory and a second write mode for writing to the non-volatile memory with higher electric power consumption than the first write mode at higher speed than the first write mode and, when the first write mode is selected, set a pulse width of the write pulse such that the pulse width is shorter than one cycle of a clock signal used to control access to the non-volatile memory,
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: October 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazutaka Ikegami, Hiroki Noguchi
  • Layout pattern for static random access memory
    Patent number: 9780099
    Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: October 3, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Wei Yeh, Tsung-Hsun Wu, Chih-Ming Su, Zhi-Xian Chou