Abstract: A semiconductor device includes a data input circuit suitable for receiving a training clock to provide first data signals and a strobe signal according to a plurality of input control signals in a training mode; a delay circuit suitable for outputting second data signals by delaying the first data signals according to delay values corresponding to respective setting codes; a data alignment circuit suitable for outputting third data signals by aligning the second data signals according to the strobe signal; a code generation circuit suitable for generating a preliminary code corresponding to the third data signals according to the training clock, and sequentially storing the preliminary code as the setting codes according to a code-lock signal; and a lock-detection circuit suitable for activating the code-lock signal based on the training clock and the preliminary code.

Abstract: In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

Abstract: A volatile memory device may include; a first sense amplifier, a second sense amplifier spaced apart from the first sense amplifier in a first direction, a first mat disposed between the first sense amplifier and the second sense amplifier and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier, a third sense amplifier spaced apart from the second sense amplifier in a second direction, a fourth sense amplifier spaced apart from the third sense amplifier in the first direction, and a second mat disposed between the third sense amplifier and the fourth sense amplifier and including a first complementary bit line connected to the first sense amplifier.

Abstract: Components of sense amplifiers may share contacts that couple the components to a global line via a local line. In some examples, the components may be pull-down circuits of a same sense amplifier or pull-down circuits of adjacent sense amplifiers. The shared contact may include a transistor or a resistance between the local line and the global line. In some examples, the global line may be an RNL line. The transistor or resistance may reduce the impact of voltage across the components from affecting the global line and/or reduce the impact of voltage changes on the global line on the individual components.

Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.

Abstract: Methods, systems, and devices for a dynamic row hammering threshold for memory are described. A memory device may implement a dynamic threshold, such as a threshold quantity of activate operations or a row hammering threshold, for a set of multiple rows of the memory device. For example, the memory device may determine a quantity of rows which exceed a row hammering threshold during a refresh duration and a total quantity of activate operations performed across the set of rows during the refresh duration, and may alter the dynamic threshold based on the quantity of rows, the quantity of activate operations, or both. By altering the dynamic threshold, the memory device may decrease a likelihood that a relatively large quantity of refresh operations for rows that are close to being hammered occur within a short time span.

Abstract: A signal processing circuit includes a first signal latch circuit, a second signal latch circuit, and a decoder. The first signal latch circuit receives a command address signal and is driven by an even clock; the second signal latch circuit receives the command address signal and is driven by an odd clock; and the decoder is connected to the first signal latch circuit and the second signal latch circuit, and outputs a control signal. Both the even clock and the odd clock have a frequency equal to that of a reference clock, and both the even clock and the odd clock have a rising edge aligned with a rising edge of the reference clock.

Abstract: Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.

Abstract: A row hammer control method and a memory device are provided. The memory device monitors the row hammer address(es) having the number of accesses equal to or more than a predetermined number of times or having a higher number of accesses as compared with other access addresses during the first row hammer monitoring time frame and malicious row hammer address(es) accessed at random sampling time points during the second row hammer monitoring time frame and being the same as the row hammer address(es), notifies a memory controller of the malicious row hammer address(es) when the number of malicious row hammer addresses exceeds a threshold value, and causes a target refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address(es) to be performed.

Abstract: A data storage device may include a storage including a plurality of storage regions each composed of a plurality of pages; and a controller. The controller is configured to select a plurality of target open regions from open regions among the storage regions on the basis of health information of the open regions, in each of which a programmed page and an unprogrammed page coexist, and perform control so that refresh operations for the respective target open regions are performed in a time-distributed manner.

Abstract: According to some embodiments, a memory controller may be provided. A compute-in-memory array may be connected to a plurality of word lines of the memory controller, with multiple word lines per word being associated with different temperature coefficients, to facilitate temperature compensation of the compute-in-memory array. In some embodiments, the compute-in-memory array may be associated with parameter floating-gate transistors. Moreover, a plurality of compute-in-memory arrays may be individually programmed to several orders of parameter magnitude.

Abstract: A memory system includes semiconductor memory devices and a control device. Each of the semiconductor memory devices includes a first pad to which a first signal is input, a second pad to which a second signal is input, a third pad to which a third signal is input, a memory cell array, a sense amplifier, and a data register. In a first mode, after the first signal is switched, a command set instructing a data out operation is input via the second pad. In a second mode, after the first signal is switched, the command is input via at least the third pad. The control device executes a first operation assigning different addresses to the respective semiconductor memory devices and a second operation causing the modes of the respective semiconductor memory devices to be switched from the first to the second mode.

Abstract: The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.

Abstract: An apparatus for controlling access to a memory device comprising rows of memory units is provided. The apparatus comprises: an operation monitor configured to track memory operations to the rows of memory units of the memory device; a row hammer counter configured to determining, for each of the rows of memory units, row hammer effects experienced by the row of memory units due to the memory operations to the other rows of memory units of the memory device; a mitigation module configured to initiate, for each of the rows of memory units, row hammer mitigation in case that accumulated row hammer effects experienced by the row of memory units reach a predetermined threshold; and a virtual host module configured to perform the row hammer mitigation targeting a row of memory units in response to the initiation of row hammer mitigation for the row of memory units by the mitigation module.

Abstract: A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.

Abstract: Systems, apparatuses and methods may provide for technology that resumes a program operation with respect to NAND memory during a first tier in response to a suspension counter reaching a first threshold and resumes the program operation with respect to the NAND memory during a second tier in response to the suspension counter reaching a second threshold. The technology may also resume the program operation with respect to the NAND memory during a third tier in response to the suspension counter reaching a third threshold. Additionally, the technology may service one or more read operations with respect to the NAND memory until the suspension counter reaches the first threshold during the first tier, until the suspension counter reaches the second threshold during the second tier, and until the suspension counter reaches the third threshold during the third tier.

Abstract: A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is performed on the particular memory segment. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment.

Abstract: The present disclosure includes apparatuses and methods related to memory topologies. An apparatus may include a first plurality of clam-shell paired memory devices arranged in a star connection topology, each clam-shelled pair of the first plurality of memory devices being coupled by a respective matched branch to a first common command address signal trace. The apparatus may include a second plurality of memory devices coupled to a second common command address signal trace.

Abstract: Methods, systems, and devices for voltage detection for managed memory systems are described. In some cases, a memory system may include circuitry to monitor one or more supply voltages to the memory system or voltages generated by the memory system to determine whether a voltage rises above an operational range. In some cases, an overvoltage detector may include an undervoltage detector that has been tuned or manufactured to have a higher threshold than an undervoltage detector used to determine whether a voltage has fallen below the operational range. Accordingly, the memory system may monitor a voltage using an undervoltage detector having a threshold corresponding to a lower bound or lower operation point of the operational range of the monitored voltage and an overvoltage detectors having a threshold corresponding to the upper bound or upper operational point of the operational range.

Abstract: An apparatus is provided that includes a memory die having a first memory cell, and a controller connected to the memory die. The controller is configured to apply a plurality of programming pulses to the first memory cell, apply a plurality of first verify pulses to the first memory cell, determine from the first verify pulses that the first memory cell has been programmed to a first programmed memory state, apply a single second verify pulse to the first memory cell after determining that the first memory cell has been programmed to the first programmed memory state, determine from the single second verify pulse that the first memory cell is no longer programmed to the first programmed memory state, and apply an additional programming pulse to the first memory cell.