Patents Examined by Son L. Mai
  • Patent number: 11031402
    Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Cezar Bogdan Zota, Clarissa Convertino, Lukas Czornomaz, Siegfried Friedrich Karg
  • Patent number: 11017879
    Abstract: Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventors: James S. Rehmeyer, Christopher G. Wieduwilt, George Raad, Seth Eichmeyer, Dean Gans
  • Patent number: 11017844
    Abstract: A semiconductor memory device includes a cache latch group including a plurality of even latch stages and a plurality of odd latch stages arranged alternately with each other; and a sense amplifier group coupled to the cache latch group through a plurality of first bit out lines respectively corresponding to the plurality of even latch stages and through a plurality of second bit out lines respectively corresponding to the plurality of odd latch stages.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 25, 2021
    Assignee: SK hynix Inc.
    Inventor: Wan Seob Lee
  • Patent number: 11004525
    Abstract: Systems and methods for increasing cycling endurance and minimizing over programming of non-volatile memory cells by modulating the programming voltage applied to the non-volatile memory cells over time as the number of program/erase cycles increases are described. A bit count ratio based on bit counts within two threshold voltage zones may be used to determine the amount of voltage reduction in the programming voltage applied during subsequent programming operations. For example, if the bit count ratio is between 0.02 and 0.05, then the reduction in the programming voltage may be 100 mV; if the bit count ratio is between 0.05 and 0.10, then the reduction in the programming voltage may be 200 mV. The modulation (e.g., the reduction) of the programming voltage may be performed at varying cycle intervals depending on the total number of program/erase cycles for a memory block and/or the bit count ratio.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: May 11, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rajdeep Gautam, Ken Oowada
  • Patent number: 10998049
    Abstract: In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: May 4, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Wenzhe Wei, Hongtao Liu, Kaikai You, Da Li, Ying Huang, Yali Song, Dejia Huang
  • Patent number: 10998065
    Abstract: A memory device includes a memory cell block including a plurality of memory cells. The memory device also includes peripheral circuits configured to perform an erase operation by a gate induce drain leakage (GIDL) method by applying a first erase voltage and a second erase voltage to a source line of the memory cell block. The memory device further includes control logic configured to control the peripheral circuits to sequentially perform an operation of applying the first erase voltage and an operation of applying the second erase voltage during the erase operation, wherein memory cells having a plurality of program states, among the plurality of memory cells, are erased to have a pre-erase state during the operation of applying the first erase voltage.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventor: Hae Soon Oh
  • Patent number: 10998906
    Abstract: A logic function device according to an embodiment of the present invention includes one or more function reconfiguring units having magnetization in one direction set by spin torque caused due to an function reconfiguring current, and an output terminal formed at an end thereof; and one or more input units formed on the function reconfiguring unit and having magnetization in the one direction set by spin torque caused due to an input current, wherein an output voltage of the output terminal is determined on the basis of whether a magnetization direction of the function reconfiguring unit and a magnetization direction of the input unit are parallel or anti-parallel.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: May 4, 2021
    Inventors: Kyoung Whan Kim, Dong Soo Han, Byoung Chul Min, Seok Min Hong, Hyun Cheol Koo, Hyung Jun Kim, Tae Eon Park, Ouk Jae Lee
  • Patent number: 10991756
    Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chih Lai, Chung-Te Lin, Min Cao, Randy Osborne
  • Patent number: 10991444
    Abstract: Calibrating read reference voltages is disclosed. In an aspect, a control die calibrates read reference voltages for reading the non-volatile memory cells. The control die is bonded to a memory die that contains memory cells. In one aspect, a tiered approach to calibrating read reference voltages is taken. For example, first the control die may attempt to determine new values for read reference voltages. If the new read reference voltages are satisfactory, then the control die may use the new read reference voltages. The control die could use one or more different techniques to determine new read reference voltages. If the new read reference voltages determined by the control die are unsatisfactory, then a memory controller in communication with the control die may calibrate the read reference voltages. By the control die determining the new read reference voltages, the memory controller is substantially less burdened with such tasks.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 27, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alexander Bazarsky, Eran Sharon, Idan Alrod
  • Patent number: 10991430
    Abstract: A non-volatile memory cell includes a storage transistor having a first terminal, a second terminal, and a gate terminal. During a program operation, the first terminal of the storage transistor receives a data voltage according to a weighting to be stored in the non-volatile memory cell, the second terminal of the storage transistor is floating, and the gate terminal of the storage transistor is coupled to a program voltage. The program voltage is greater than the data voltage.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 27, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Chih-Hsin Chen, Chun-Fu Lin
  • Patent number: 10984866
    Abstract: A non-volatile memory device includes a plurality of memory blocks grouped into pages, page buffer regions corresponding to the pages of the plurality of memory blocks; and a peripheral circuit region for supporting operations of the pages of the plurality of memory blocks. The peripheral circuit region comprises a plurality of pool capacitors. At least one of the memory blocks is a dummy block. The dummy block is configured to form a supplementary pool capacitor for suppressing power noise.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: April 20, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Jin Yong Oh
  • Patent number: 10984872
    Abstract: A non-volatile memory device determines the bit-line location of a memory cell selected for memory operation relative to a nearest source line, generates a modified bit-line bias voltage based on the bit-line location and applies the modified bit-line bias voltage to the selected memory cell. In some embodiments, the memory cell is selected to be programmed. In this manner, the non-volatile memory device compensates for source line resistance at the memory cells.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 20, 2021
    Assignee: INTEGRATED SILICON SOLUTION, (CAYMAN) INC.
    Inventor: Kyoung Chon Jin
  • Patent number: 10978139
    Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: April 13, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Hoan Huu Nguyen, Francois Ibrahim Atallah, Keith Alan Bowman, Daniel Yingling, Jihoon Jeong, Yu Pu
  • Patent number: 10971209
    Abstract: A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: April 6, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Ohwon Kwon, Kou Tei, VSNK Chaitanya G
  • Patent number: 10971210
    Abstract: A nonvolatile memory device includes a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory cell region includes a first memory stack comprising first memory cells vertically stacked on each other, and a second memory stack comprising second memory cells vertically stacked on each other. The peripheral circuit region includes a control logic for setting a voltage level of a second voltage applied for a second memory operation to a second memory cell of the second memory cells based on a first voltage applied to a first memory cell of the first memory cells in a first memory operation. Cell characteristics of the first memory cell are determined using the first voltage.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-chul Park, Youn-yeol Lee, Seul-bee Lee, Kyung-sub Lim
  • Patent number: 10971234
    Abstract: Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Jung Hwan Lee, Jung Mi Ko, Ji Hwan Kim, Kwang Ho Baek, Young Don Jung
  • Patent number: 10964366
    Abstract: There is provided a magnetic memory that can suppress the increase in manufacturing costs while recording multivalued information in one memory cell, the memory including first and second tunnel junction elements each having a laminated structure including a reference layer with a fixed magnetization direction, a recording layer with a reversible magnetization direction, and an insulating layer sandwiched between the reference layer and the recording layer, a first selection transistor electrically connected to first ends of the first and second tunnel junction elements, a first wire electrically connected to a second end of the first tunnel junction element, and a second wire electrically connected to a second end of the second tunnel junction element.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: March 30, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Yutaka Higo, Hiroyuki Uchida, Naoki Hase, Yo Sato
  • Patent number: 10964701
    Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek Anil Sharma, Van H. Le, Gilbert William Dewey, Rafael Rios, Jack T. Kavalieros, Yih Wang, Shriram Shivaraman
  • Patent number: 10957404
    Abstract: According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akio Sugahara, Takaya Handa, Ryosuke Isomura, Kazuto Uehara, Junichi Sato, Norichika Asaoka, Masashi Yamaoka, Bushnaq Sanad, Yuzuru Shibazaki, Noriyasu Kumazaki, Yuri Terada
  • Patent number: 10957378
    Abstract: A control circuit and a control method thereof adapted to a pseudo static random access memory are provided. The control circuit includes a write data determining circuit and a clock generating circuit. The write data determining circuit counts and compares data input times and actual data write times of the pseudo static random access memory to generate a write matching signal, and generates a write counting clock signal according to counting operation of the data input times of the pseudo static random access memory. The clock generating circuit generates a preamble signal according to the write matching signal and the write counting clock signal, and generates a column address strobe clock signal and a control signal according to the preamble signal. The clock generating circuit determines whether to dynamically delay the preamble signal to delay or omit a pulse of a column selection line signal.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 23, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Kaoru Mori