Patents Examined by Son L. Mai
  • Patent number: 11990173
    Abstract: Methods, systems, and devices for a dynamic row hammering threshold for memory are described. A memory device may implement a dynamic threshold, such as a threshold quantity of activate operations or a row hammering threshold, for a set of multiple rows of the memory device. For example, the memory device may determine a quantity of rows which exceed a row hammering threshold during a refresh duration and a total quantity of activate operations performed across the set of rows during the refresh duration, and may alter the dynamic threshold based on the quantity of rows, the quantity of activate operations, or both. By altering the dynamic threshold, the memory device may decrease a likelihood that a relatively large quantity of refresh operations for rows that are close to being hammered occur within a short time span.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: May 21, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Sujeet V. Ayyapureddi
  • Patent number: 11972838
    Abstract: A signal processing circuit includes a first signal latch circuit, a second signal latch circuit, and a decoder. The first signal latch circuit receives a command address signal and is driven by an even clock; the second signal latch circuit receives the command address signal and is driven by an odd clock; and the decoder is connected to the first signal latch circuit and the second signal latch circuit, and outputs a control signal. Both the even clock and the odd clock have a frequency equal to that of a reference clock, and both the even clock and the odd clock have a rising edge aligned with a rising edge of the reference clock.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: April 30, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zequn Huang
  • Patent number: 11967353
    Abstract: Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: April 23, 2024
    Inventors: Vaughn N. Johnson, Debra M. Bell, Miles S. Wiscombe, Brian T. Pecha, Kyle Alexander
  • Patent number: 11961549
    Abstract: A data storage device may include a storage including a plurality of storage regions each composed of a plurality of pages; and a controller. The controller is configured to select a plurality of target open regions from open regions among the storage regions on the basis of health information of the open regions, in each of which a programmed page and an unprogrammed page coexist, and perform control so that refresh operations for the respective target open regions are performed in a time-distributed manner.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: April 16, 2024
    Assignee: SK hynix Inc.
    Inventors: Seon Ju Lee, Da Seul Lee
  • Patent number: 11961548
    Abstract: A row hammer control method and a memory device are provided. The memory device monitors the row hammer address(es) having the number of accesses equal to or more than a predetermined number of times or having a higher number of accesses as compared with other access addresses during the first row hammer monitoring time frame and malicious row hammer address(es) accessed at random sampling time points during the second row hammer monitoring time frame and being the same as the row hammer address(es), notifies a memory controller of the malicious row hammer address(es) when the number of malicious row hammer addresses exceeds a threshold value, and causes a target refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address(es) to be performed.
    Type: Grant
    Filed: July 23, 2022
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ho-Youn Kim
  • Patent number: 11955193
    Abstract: According to some embodiments, a memory controller may be provided. A compute-in-memory array may be connected to a plurality of word lines of the memory controller, with multiple word lines per word being associated with different temperature coefficients, to facilitate temperature compensation of the compute-in-memory array. In some embodiments, the compute-in-memory array may be associated with parameter floating-gate transistors. Moreover, a plurality of compute-in-memory arrays may be individually programmed to several orders of parameter magnitude.
    Type: Grant
    Filed: December 5, 2023
    Date of Patent: April 9, 2024
    Assignee: ASPINITY, INC.
    Inventors: Brandon David Rumberg, Steven Andryzcik
  • Patent number: 11942132
    Abstract: The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Shunpei Yamazaki
  • Patent number: 11942180
    Abstract: A memory system includes semiconductor memory devices and a control device. Each of the semiconductor memory devices includes a first pad to which a first signal is input, a second pad to which a second signal is input, a third pad to which a third signal is input, a memory cell array, a sense amplifier, and a data register. In a first mode, after the first signal is switched, a command set instructing a data out operation is input via the second pad. In a second mode, after the first signal is switched, the command is input via at least the third pad. The control device executes a first operation assigning different addresses to the respective semiconductor memory devices and a second operation causing the modes of the respective semiconductor memory devices to be switched from the first to the second mode.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: March 26, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Zhao Lyu, Akio Sugahara, Takehisa Kurosawa, Yuji Nagai, Hisashi Fujikawa
  • Patent number: 11935623
    Abstract: An apparatus for controlling access to a memory device comprising rows of memory units is provided. The apparatus comprises: an operation monitor configured to track memory operations to the rows of memory units of the memory device; a row hammer counter configured to determining, for each of the rows of memory units, row hammer effects experienced by the row of memory units due to the memory operations to the other rows of memory units of the memory device; a mitigation module configured to initiate, for each of the rows of memory units, row hammer mitigation in case that accumulated row hammer effects experienced by the row of memory units reach a predetermined threshold; and a virtual host module configured to perform the row hammer mitigation targeting a row of memory units in response to the initiation of row hammer mitigation for the row of memory units by the mitigation module.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: March 19, 2024
    Assignee: MONTAGE TECHNOLOGY (KUNSHAN) CO.
    Inventors: Yibo Jiang, Leechung Yiu, Christopher Cox, Robert Xi Jin, Lizhi Jin, Leonard Datus
  • Patent number: 11923016
    Abstract: Systems, apparatuses and methods may provide for technology that resumes a program operation with respect to NAND memory during a first tier in response to a suspension counter reaching a first threshold and resumes the program operation with respect to the NAND memory during a second tier in response to the suspension counter reaching a second threshold. The technology may also resume the program operation with respect to the NAND memory during a third tier in response to the suspension counter reaching a third threshold. Additionally, the technology may service one or more read operations with respect to the NAND memory until the suspension counter reaches the first threshold during the first tier, until the suspension counter reaches the second threshold during the second tier, and until the suspension counter reaches the third threshold during the third tier.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Aliasgar S. Madraswala, Sagar Upadhyay, Jiantao Zhou
  • Patent number: 11922989
    Abstract: A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: March 5, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jungmin You, Seongjin Cho
  • Patent number: 11915771
    Abstract: Methods, systems, and devices for voltage detection for managed memory systems are described. In some cases, a memory system may include circuitry to monitor one or more supply voltages to the memory system or voltages generated by the memory system to determine whether a voltage rises above an operational range. In some cases, an overvoltage detector may include an undervoltage detector that has been tuned or manufactured to have a higher threshold than an undervoltage detector used to determine whether a voltage has fallen below the operational range. Accordingly, the memory system may monitor a voltage using an undervoltage detector having a threshold corresponding to a lower bound or lower operation point of the operational range of the monitored voltage and an overvoltage detectors having a threshold corresponding to the upper bound or upper operational point of the operational range.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yoav Weinberg, Evgeni Bassin
  • Patent number: 11915791
    Abstract: The present disclosure includes apparatuses and methods related to memory topologies. An apparatus may include a first plurality of clam-shell paired memory devices arranged in a star connection topology, each clam-shelled pair of the first plurality of memory devices being coupled by a respective matched branch to a first common command address signal trace. The apparatus may include a second plurality of memory devices coupled to a second common command address signal trace.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Matthew B. Leslie
  • Patent number: 11915785
    Abstract: A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is performed on the particular memory segment. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jiangang Wu, Lei Zhou, Jung Sheng Hoei, Kishore Kumar Muchherla, Qisong Lin
  • Patent number: 11908524
    Abstract: An apparatus is provided that includes a memory die having a first memory cell, and a controller connected to the memory die. The controller is configured to apply a plurality of programming pulses to the first memory cell, apply a plurality of first verify pulses to the first memory cell, determine from the first verify pulses that the first memory cell has been programmed to a first programmed memory state, apply a single second verify pulse to the first memory cell after determining that the first memory cell has been programmed to the first programmed memory state, determine from the single second verify pulse that the first memory cell is no longer programmed to the first programmed memory state, and apply an additional programming pulse to the first memory cell.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: February 20, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ming Wang, Liang Li, Ke Zhang
  • Patent number: 11908526
    Abstract: According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventors: Naoto Kumano, Kenji Sakurada
  • Patent number: 11894059
    Abstract: A memory device includes a memory structure including at least one non-volatile memory cell capable of storing multi-bit data, and a control device configured to perform a program verification after a first program pulse is applied to the at least one non-volatile memory cell, determine a program mode for the at least one non-volatile memory cell based on a result of the program verification, and change a level of a pass voltage, applied to another non-volatile memory cell coupled to the at least one non-volatile memory cell, from a first level to a second level which is higher than the first level, or a setup time for changing a potential of a bit line coupled to the at least one non-volatile memory cell, according to the program mode.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: February 6, 2024
    Assignee: SK hynix Inc.
    Inventors: Tae Hun Park, Dong Hun Kwak
  • Patent number: 11894099
    Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Hyun Yoo Lee, Timothy M. Hollis, Dong Soon Lim
  • Patent number: 11887642
    Abstract: A state of a reference cell in a storage device is appropriately managed. A first memory cell array includes a first reference cell that generates reference potential of a sense amplifier. A second memory cell array includes a second reference cell that generates reference potential of a sense amplifier. A state storage unit stores, regarding each of the first and second reference cells, a state indicating certainty of a held value. When write to either one of the first and second reference cells is instructed, the write control unit controls the instructed write on the basis of the state regarding the first and second reference cells stored in the state storage unit.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: January 30, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Atsuo Mangyo
  • Patent number: 11881285
    Abstract: According to an aspect, there are provided an apparatus and a method for providing an access to a memory circuit. A read enable input initializing a wait state counter configured to count a predetermined number of clock cycles is received (200) and the wait state counter output is monitored. A memory ready signal output is received (202) from the memory circuit at a synchronizer input and the output signal of the synchronizer is monitored. An ON-state data ready signal is provided (204) when either the wait state counter has elapsed, or the output signal of the synchronizer is in ON-state.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: January 23, 2024
    Assignee: Nordic Semiconductor ASA
    Inventor: Jussi Takkala