Patents Examined by Son L. Mai
  • Patent number: 11462255
    Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: October 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngcheon Kwon, Jaeyoun Youn, Namsung Kim, Kyomin Sohn, Seongil O, Sukhan Lee
  • Patent number: 11462280
    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including receiving a read command to perform a read operation on a block of the memory device, determining a pass-through voltage for the block based on a metadata table, and performing the read operation by applying a read reference voltage to a selected wordline of the block and applying the pass-through voltage to a plurality of unselected wordlines of the block.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: October 4, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy
  • Patent number: 11462254
    Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: October 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Gary L. Howe, Miles S. Wiscombe, James S. Rehmeyer, Eric J. Stave
  • Patent number: 11455521
    Abstract: A neuromorphic semiconductor device includes a copper-based intercalation channel disposed on an insulative layer, a source contact and a drain contact of a substrate. A copper-based electrolyte layer is disposed on the copper-based intercalation channel and a copper-based gate electrode is disposed on the copper-based electrolyte layer.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 27, 2022
    Assignee: International Business Machines Corporation
    Inventors: Teodor K. Todorov, Douglas M. Bishop, Jianshi Tang, John Rozen
  • Patent number: 11450396
    Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungryun Kim, Yoonna Oh, Hohyun Shin, Jaeho Lee
  • Patent number: 11443786
    Abstract: A memory circuit includes: memory cells each including a storage transistor corresponding to a predetermined configuration; and a tracking circuit configured to elapse a variable waiting period during which a voltage on a first node decreases from a first level to a second level, the tracking circuit including a first finger circuit coupled between a first node of a tracking bit line and a reference voltage node, the first finger circuit including a first set of first tracking cells, each first tracking cell including a first shadow transistor corresponding to the predetermined configuration, gate terminals of the first shadow transistors being coupled with a tracking word line; and a second finger circuit coupled between the first node and the reference voltage node; and a first switch configured to adjust the variable waiting period by selectively coupling the second finger circuit in parallel with the first finger circuit.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuoyuan (Peter) Hsu, Jacklyn Chang
  • Patent number: 11430494
    Abstract: A controller for data strobe signal (DQS) position adjustment includes, when the controller obtains margin effective widths of all data signals in a transmission bus, it determines a left boundary and a right boundary based on the margin effective widths, where the left boundary is a largest value in minimum values of the margin effective widths of all the DQs, and the right boundary is a smallest value in maximum values of the corresponding margin effective widths when all the DQs are aligned with the left boundary. The controller calculates a first central position based on the left boundary and the right boundary, where the first central position is a center of a smallest margin effective width obtained after all the DQs are aligned during read data training, and adjusts a delay line (DL) of the DQS to the first central position.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 30, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yongyao Li, Jun Yu, Guoyu Wang, Jiankang Li, You Li, Ruihui Hong
  • Patent number: 11423980
    Abstract: A semiconductor storage device includes a first plane storing user data and system information, a second plane storing the user data and the system information, a first latch circuit storing even-numbered bit data of the system information read from the first plane, a second latch circuit storing odd-numbered bit data of the system information read from the second plane, and a sequencer. The sequencer executes in parallel a first process of reading out the even-numbered bit data of the system information from the first plane and storing the read data in the first latch circuit and a second process of reading out the odd-numbered bit data of the system information from the second plane and storing the read data in the second latch circuit.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: August 23, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yuki Shimizu, Kosuke Yanagidaira
  • Patent number: 11417386
    Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: August 16, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehyung Lee, JungSik Kim, Youngdae Lee, Duyeul Kim, Sungmin Yim, Kwangil Park, Chulsung Park
  • Patent number: 11409676
    Abstract: Provided is a SoC, a memory device, an electronic device and a method for storing data in an electronic device. The electronic device comprises a host configured to output data, and a memory device including a memory storage configured to receive the data and to store the data. The host is configured to generate data bus inversion (DBI) information on the data to be provided to the memory device in accordance with a data parallelizing system, the data parallelizing system being inside the memory device, and to provide the DBI information to the memory device. The memory device is configured to provide the data to the memory storage, the data output from the host, the data encoded in accordance with the DBI information, the providing the data being in accordance with the data parallelizing system.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: August 9, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji Hyun Choi, Hyun-Joong Kim, Joon Sik Sohn, Woong-Jae Song, Soo-Woong Ahn, Seung-Hyun Cho
  • Patent number: 11404476
    Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chih Lai, Chung-Te Lin, Min Cao, Randy Osborne
  • Patent number: 11393525
    Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tomoki Nakagawa, Koji Kato, Toshifumi Hashimoto
  • Patent number: 11393511
    Abstract: Methods, systems, and devices for limiting regulator overshoot during power up are described. In some examples, a memory device may generate a first voltage at a first input node of an amplifier of a memory device based on an application, by an external supply, of a second voltage to a terminal of the memory device. The memory device may generate a third voltage at a second node of the amplifier at an amplifier at an offset to the first voltage, where the second node is coupled with a first gate of a first cascode transistor and a second gate of a second cascode transistor. The memory device may activate the amplifier based on generating the third voltage at the second node of the amplifier.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Fei Xu, Dong Pan, Wei Lu Chu
  • Patent number: 11386974
    Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: July 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sehwan Park, Jinyoung Kim, Ilhan Park, Kyoman Kang, Sangwan Nam
  • Patent number: 11380372
    Abstract: Methods and devices related to transferring data between DRAM and SRAM. One method includes activating a first portion of a dynamic random access memory (DRAM), reading data from the first portion of the DRAM, latching the data from the first portion of the DRAM in one or more sense amplifiers, and writing the data from the one or more sense amplifiers to a first portion of a static random access memory (SRAM).
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Timothy P. Finkbeiner, Troy A. Manning, Troy D. Larsen, Glen E. Hush
  • Patent number: 11378603
    Abstract: The present disclosure relates to a detector comprising a comparator receiving on a voltage input a voltage value to be detected; a digital to analog converter coupled to a reference voltage potential having an output connected to another input of the comparator; and a Finite State Machine receiving an output of the comparator and producing digital outputs for inputs of a memory controller.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Alberto Troia, Antonino Mondello
  • Patent number: 11373728
    Abstract: Logic (apparatus and/or software) is provided that separates read and restore operations. When a read is completed, the read data is stored in a restore buffer allowing other latency critical operations such as reads to be serviced before the restore. Deferring restore operations minimizes latency and burst bandwidth for reads and minimizes the performance impact of the non-critical restore operations.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: June 28, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Christopher B. Wilkerson, Rajeev Kumar Dokania, Sasikanth Manipatruni, Amrita Mathuriya
  • Patent number: 11373721
    Abstract: Embodiments of the present disclosure provide a signal verification system, including: a memory controller, a memory, and a first transmission path and a second transmission path connected between the memory controller and the memory, where the memory controller sends one or more to-be-check signals through the first transmission path, and sends a check signal through the second transmission path, where the second transmission path is a single-port channel, and the check signal is a multi-bit signal; and a comparison module, connected to an output end of a first conversion component and an output end of the second transmission path, and configured to obtain and compare an output signal of the first conversion component and an output signal of the second transmission path.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: June 28, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Pengzhou Su
  • Patent number: 11373727
    Abstract: Logic (apparatus and/or software) is provided that separates read and restore operations. When a read is completed, the read data is stored in a restore buffer allowing other latency critical operations such as reads to be serviced before the restore. Deferring restore operations minimizes latency and burst bandwidth for reads and minimizes the performance impact of the non-critical restore operations.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: June 28, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Christopher B. Wilkerson, Rajeev Kumar Dokania, Sasikanth Manipatruni, Amrita Mathuriya
  • Patent number: 11373694
    Abstract: A generic physical layer providing a unified architecture for interfacing with an external memory device. The physical layer comprises a transmit data path for transmitting a parallel data to the external memory device and a receive data path for receiving a serial data from the external memory device. The generic physical layer is characterized by a receive enable logic for masking strobe of the serial data, wherein the transmit data path and the receive data path each comprising a FIFO circuit, a data rotator and an adjustable-delay logic for delay tuning and a per-bit-deskew for multi-lane support.
    Type: Grant
    Filed: February 6, 2021
    Date of Patent: June 28, 2022
    Assignee: SKYECHIP SDN BHD
    Inventors: Soon Chieh Lim, Chee Hak Teh, Tat Hin Tan