Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.

Abstract: To provide a semiconductor device capable of retaining data for a long period. The semiconductor device includes a memory circuit and a retention circuit. The memory circuit includes a first transistor, and the retention circuit includes a second transistor. The memory circuit is configured to write data by turning on the first transistor and to retain the data by turning off the first transistor. The retention circuit is configured to supply a first potential at which the first transistor is turned off to a back gate of the first transistor by turning on the second transistor and to retain the first potential by turning off the second transistor. Transistors having different electrical characteristics are used as the first transistor and the second transistor.

Abstract: A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.

Abstract: A semiconductor device includes a SRAM circuit. The SRAM circuit includes: a memory array having a plurality of memory cells arranged in a matrix; a ground interconnection commonly connected to each of the memory cells; and a first potential control circuit for controlling a potential of the ground interconnection depending on an operation mode. The first potential control circuit includes a first NMOS transistor and a first PMOS transistor connected in parallel to each other between a ground node providing a ground potential and the ground interconnection.

Abstract: The invention provides a flash memory device, which comprises a controller, a plurality of flash memories, a switcher, a power supply module, and a voltage detection circuit. When the system voltage is higher than a voltage threshold, the voltage detection circuit outputs an enable signal to the switcher to turn on the switcher, the system voltage is provided to the power supply module, the power supply module executes a charging process by the system voltage, and generates an output voltage based on the system voltage. The output voltage is an operating voltage of the controller and the flash memories. When the system voltage is lower than the voltage threshold, the voltage detection circuit outputs a disable signal to the switcher to turn off the switcher, the system voltage is inhibited to provide to the power supply module, the power module generates the output voltage by executing a discharging process.

Abstract: Techniques for writing magnetic random access memory (MRAM) using the spin hall effect with a self-reference read are provided. In one aspect, an MRAM device is provided. The MRAM device includes: a plurality of first spin hall wires oriented orthogonal to a plurality of second spin hall wires; a plurality of magnetic memory cells configured in an array between the first spin hall wires and the second spin hall wires; and a plurality of transistors connected to the magnetic memory cells by the first spin hall wires. Methods of operating an MRAM device are also provided.

Abstract: A data storage device includes a nonvolatile memory device; a voltage detector suitable for detecting an operating voltage of the nonvolatile memory device; and a control unit suitable for making a first determination whether the operating voltage is dropped intentionally or unintentionally based on a first reference time and an elapsed time for which the operating voltage decreases from a first reference voltage to a second reference voltage.

Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.

Abstract: Systems and methods are disclosed for reducing memory power consumption via pre-filled dynamic random access memory (DRAM) values. One embodiment is a method for providing DRAM values. A fill request is received from an executing program to fill an allocated portion of the DRAM with a predetermined pattern of values. The predetermined pattern of values is stored in a fill value memory residing in the DRAM. A fill command is sent to the DRAM. In response to the fill command, a plurality of sense amp latches are connected to the fill value memory to update the corresponding sense amp latch bits with the predetermined pattern of values stored in the fill value memory.

Abstract: A device includes a circuit cell, a voltage regulator, and an auxiliary signal generator. The voltage regulator is configured to output a write voltage. The auxiliary signal generator is configured to generate an auxiliary signal according to a reference voltage and a reference current, and to transmit the auxiliary signal and the write voltage to the circuit cell according to select signals.

Abstract: A field device for determining or monitoring a process variable in automation technology. The field device meets a safety standard, which is required in a predetermined safety-critical application, comprising: a sensor, which works according to a defined measuring principle; and a control/evaluation unit, which processes and evaluates measurement data delivered by the sensor along at least three redundant and/or diversely designed measurement channels, wherein a redundant analog electrical current interface is provided, via which an electrical current representing the process variable is settable in a two-wire line.

Abstract: Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up are described in the present disclosure. An example apparatus includes a first circuit configured to receive a supply voltage and further configured to provide an active first signal responsive to the supply voltage exceeding a threshold voltage. The example apparatus further includes a second circuit coupled to the first circuit and activated by the active first signal, the second circuit configured to provide an active second signal when a third circuit is ready for operation.

Abstract: Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function.

Abstract: An erase operation includes one or more erase depth checks to detect the occurrence of shallow erased memory cells at the end of an erase process. Memory cells are subjected to erase and erase verification until erase verification success is achieved. At the end of successful erase verification, a subset of memory cells is read to detect an erase depth or level of the memory cells. If the erase depth check indicates that the subset memory cells are in a shallow erased condition, additional erasing and verification is performed.

Abstract: Example implementations relate to post package repair (PPR) data in non-volatile memory. In example implementations, PPR data may be stored in non-volatile memory on a memory module. PPR data may indicate how many PPRs have been performed on the memory module.

Abstract: A semiconductor memory device includes a cell array including memory cells. A potential generation circuit applies a first potential to the memory cells. A control signal output circuit outputs a control signal based on the first potential. A pulse width adjustment circuit adjusts a pulse width of a word line voltage of the cell array based on the control signal. An amplitude of a voltage applied to bit lines connected to the memory cells is controlled with the pulse width.

Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Abstract: The present disclosure includes apparatuses and methods for partitioned parallel data movement. An example apparatus includes a memory device that includes a plurality of partitions, where each partition of the plurality of partitions includes a subset of a plurality of subarrays of memory cells. The memory device also includes sensing circuitry coupled to the plurality of sub arrays, the sensing circuitry including a sense amplifier. A controller for the memory device is configured to direct a first data movement within a first partition of the plurality of partitions in parallel with a second data movement within a second partition of the plurality of partitions.

Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.

Abstract: Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in series may be placed in complementary memory states any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device.