Abstract: A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.

Abstract: Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.

Abstract: Example implementations relate to post package repair (PPR) data in non-volatile memory. In example implementations, PPR data may be stored in non-volatile memory on a memory module. PPR data may indicate how many PPRs have been performed on the memory module.

Abstract: A memory circuit includes a plurality of bit-cells organized in a column. Each bit-cell of the plurality is coupled to first and second voltage supply terminals, and first and second bit-lines. A word-line is coupled to a bit-cell of the plurality and configured to receive a first voltage during a first write operation. A first voltage generation circuit is coupled to the first voltage supply terminal and is configured to provide a first reduced voltage during the first write operation. A second voltage generation circuit is coupled to the second voltage supply terminal and is configured to provide a second reduced voltage during the first write operation.

Abstract: A memory controller includes a voltage driver and a voltage comparator. The voltage driver applies a variable voltage to a selected line of a crossbar array to determine a first measured voltage that drives a first read current through a selected memory cell of the crossbar array. The voltage driver applies the variable voltage to the selected line to determine a second measured voltage that drives a second read current through the selected memory cell. The voltage comparator then determines a voltage difference between the first measured voltage and the second measured voltage and to compare the voltage difference with a reference voltage difference to determine a state of the selected memory cell. The crossbar array comprises a plurality of row lines, a plurality of column lines, and a plurality of memory cells. Each memory cell is coupled between a unique combination of one row line and one column line.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.

Abstract: A memory macro includes a plurality of columns and a plurality of switching circuits. A column of the plurality of columns has a plurality of voltage supply nodes corresponding to a plurality of memory cells in the column. A switching circuit of the plurality of switching circuits corresponds to a column of the plurality of columns and is configured to selectively provide a first voltage value of a first voltage source or a second voltage value of a second voltage source to the voltage supply nodes. The first voltage value and the second voltage value differ by a predetermined voltage value.

Abstract: Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.

Abstract: In some embodiments, a memory device includes a memory bank, a global data line, a first tri-state unit, a latch, a second tri-state unit and a pre-charge unit. The first tri-state unit is configured between the memory bank and the global data line. The latch is configured to provide a state signal based on a data signal from the memory bank. The second tri-state unit is configured between the global data line and the latch. The pre-charge unit pre-charges the global data line to a first intermediate level or a second intermediate level depending on the state signal during the global data line is caused to be electrically isolated from the memory bank by the first tri-state unit and electrically isolated from the latch by the second tri-state unit.

Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.

Abstract: In some aspects, a calibration method includes performing a write/read test for each one of multiple combinations of write/read delay settings, wherein each one of the multiple combinations of write/read delay settings includes one of a plurality of write delay settings of a first delay device and one of a plurality of read delay settings of a second delay device. The method also includes obtaining test results for the write/read tests, determining a pass region based on the test results, determining a center of the pass region, and selecting one of the multiple combinations of write/read settings based on the center of the pass region.

Abstract: A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies a column voltage to a column line coupled to the target memristor, applies a first row voltage to all row lines not coupled to the target memristor and a second row voltage to a row line coupled to the target memristor, and senses a current through the target memristor to determine a state of the target memristor. The memory crossbar array includes a plurality of column lines, a plurality of row lines, a plurality of memristors, and a plurality of shorting switches. Each memristor is coupled between a unique combination of one column line and one row line. Each shorting switch has a high impedance resistor and a low impedance transistor, and each shorting switch is coupled to an end of a unique row line.

Abstract: A self-referenced MRAM cell including a reference layer having a fixed reference magnetization, a sense layer having a free sense magnetization, a tunnel barrier, a biasing layer having bias magnetization and a biasing antiferromagnetic layer pinning the bias magnetization in a bias direction when MRAM cell is at temperature equal or below a bias threshold temperature. The bias magnetization is arranged for inducing a bias field adapted for biasing the sense magnetization in a direction opposed to the bias direction, such that the biased sense magnetization varies linearly in the presence of the external magnetic field, when the external magnetic field is oriented in a direction substantially perpendicular to the one of the reference magnetization. The present disclosure further concerns a magnetic field sensor including a plurality of the self-referenced MRAM cell and a method for programming the magnetic field sensor.

Abstract: A cheap and high performance 1.5 transistor-type flash memory highly compatible externally of a memory region has a sacrifice film formed on a substrate. A U-shaped groove is formed on the sacrifice film, where multiple insulating films are laminated. The multiple insulating films includes a silicon nitride film as a charge storage layer. Low resistive material is disposed on the multiple insulating films to form a control gate. The select gate is formed on the insulating film on a side of the control gate in a self-aligned manner. Semiconductor regions opposite in conductivity to the substrate on both sides of the adjoining control gate and the select gate form a source and a drain, respectively. Thus, a 1.5 transistor-type flash memory is formed with the adjoining control gate and the select gate between the source and the drain.

Abstract: Provided is an electric-current-controllable magnetic unit, including: a substrate, an electric-current channel disposed on the substrate, the electric-current channel including a composite heavy-metal multilayer comprising at least one heavy-metal; a capping layer disposed over the electric-current channel; and at least one ferromagnetic layer disposed between the electric-current channel and the capping layer.

Abstract: The present disclosure provides control methods and control apparatus thereof and reference current modules of memory decoding systems. An exemplary control method of a memory decoding system comprising a decoder having at least a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a fourth NMOS transistor, a memory cell, and at least a first bit line and a second bit line, includes applying a first control signal, being at a logic low level during a first read operation stage of a read operation and at a logic high level during a second read operation stage after the first read operation stage of the read operation, to a gate of the first PMOS transistor; applying a second control signal to a gate of the second PMOS transistor; and applying a fourth control signal to a gate of the first NMOS transistor.

Abstract: A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.