Patents Examined by Sonya D. McCall-Shepard
  • Patent number: 10411094
    Abstract: A method of a forming a plurality of semiconductor fin structures that includes forming a sacrificial gate structure on a hardmask overlying a channel region portion of the plurality of sacrificial fins of a first semiconductor material and forming source and drain regions on opposing sides of the channel region. The sacrificial gate structure and the sacrificial fin structure are removed. A second semiconductor material is formed in an opening provided by removing the sacrificial gate structure and the sacrificial fin structure. The second semiconductor material is etched selective to the hardmask to provide a plurality of second semiconductor material fin structures. A function gate structure is formed on the channel region.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Xu, Kangguo Cheng, Juntao Li, Heng Wu
  • Patent number: 10403711
    Abstract: In one embodiment, a method of manufacturing a silicon-carbide (SiC) device includes receiving a selection of a specific terrestrial cosmic ray (TCR) rating at a specific applied voltage, determining a breakdown voltage for the SiC device based at least on the specific TCR rating at the specific applied voltage, determining drift layer design parameters based at least on the breakdown voltage. The drift layer design parameters include doping concentration and thickness of the drift layer. The method also includes fabricating the SiC device having a drift layer with the determined drift layer design parameters. The SiC device has the specific TCR rating at the specific applied voltage.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: September 3, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Alexander Viktorovich Bolotnikov, Ljubisa Dragoljub Stevanovic, Peter Almern Losee
  • Patent number: 10403796
    Abstract: A light emitting device and a method of fabricating the same. The light emitting device includes: a light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, an active layer, and a partially exposed region of an upper surface of the first conductive type semiconductor layer; a transparent electrode disposed on the second conductive type semiconductor layer; a first insulation layer including a first opening and a second opening; a metal layer at least partially covering the first insulation layer; a first electrode electrically connected to the first conductive type semiconductor layer; and a second electrode electrically connected to the transparent electrode.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: September 3, 2019
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Chang Yeon Kim, Ju Yong Park, Sung Su Son
  • Patent number: 10396105
    Abstract: A display substrate includes a base substrate comprising a plurality of sub-pixels, a first switching element disposed on the base substrate and electrically connected to a gate line extending in a first direction and a data line extending in a second direction crossing the first direction, a color filter layer disposed on the switching element and comprising a red color filter, a green color filter, a blue color filter and a white color filter alternately disposed on the plurality of sub-pixels, respectively, a column spacer disposed on the color filter and comprising the same material as that of the white color filter, an insulation layer disposed on the color filter and the column spacer and a pixel electrode disposed on the insulation layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyoung-Cheol Lee, Hyung-June Kim, Wan-Soon Im, Tae-Kyung Yim, Joon-Gun Chong, Jong-Hak Hwang
  • Patent number: 10396042
    Abstract: An interconnect level is provided on a surface of a substrate that has improved crack stop capability. The interconnect level includes at least one wiring region including an electrically conductive structure embedded in an interconnect dielectric material having a dielectric constant of less than 4.0, and a crack stop region laterally surrounding the wiring region. The crack stop region includes a crack stop dielectric material having a dielectric constant greater than the dielectric constant of the interconnect dielectric material. The crack stop region may be devoid of any metallic structure, or it may contain a metallic structure. The metallic structure in the crack stop region, which is embedded in the crack stop dielectric material, may be composed of a same, or different, electrically conductive metal or metal alloy as the electrically conductive structure embedded in the interconnect dielectric material.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Chih-Chao Yang, Griselda Bonilla
  • Patent number: 10388529
    Abstract: A method for preparing a substrate with an insulating buried layer includes: providing a substrate, the substrate having a supporting layer and an insulating layer arranged on a surface of the supporting layer; performing first ion implantation, implanting modified ions into the substrate, wherein a distance from an interface between the insulating layer and the supporting layer to a Gaussian distribution peak of modified ion concentration is less than 50 nm, such that the modified ions form a nano cluster in the insulating layer; and performing a second ion implantation, continuing to implant the modified ions into the insulating layer, wherein the ions are implanted in the same way as the first ion implantation, and a distance from a Gaussian distribution peak of modified ion concentration in this step to the Gaussian distribution peak of modified ion concentration in the first ion implantation is less than 80 nm.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 20, 2019
    Assignee: SHANGHAI SIMGUI TECHNOLOGY CO., LTD.
    Inventors: Xing Wei, Yongwei Chang, Meng Chen, Guoxing Chen, Lu Fei, Xi Wang
  • Patent number: 10390145
    Abstract: A micro electro mechanical system (MEMS) microphone includes a substrate, having a substrate opening. A supporting dielectric layer is disposed on the substrate surrounding the substrate opening. A diaphragm is supported by the supporting dielectric layer above the substrate opening, wherein the diaphragm has a bowl-like structure being convex toward the substrate opening when the diaphragm is at an operation off state. A backplate is disposed on the supporting dielectric layer over the diaphragm, wherein the backplate includes a plurality of venting holes at a region corresponding to the substrate opening.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: August 20, 2019
    Assignee: Solid State System Co., Ltd.
    Inventors: Tsung-Min Hsieh, Cheng-Wei Tsai, Chien-Hsing Lee
  • Patent number: 10381220
    Abstract: The present application relates to a method for forming an active zone of metal oxide for an electronic component including the formation of a stack of IXZO layers produced by liquid phase deposition on a substrate, the layers of said stack having different atomic fractions to each other in order to make it possible to reduce the annealing temperature enabling them to be made functional.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 13, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Mohammed Benwadih, Christine Revenant-Brizard
  • Patent number: 10381367
    Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Dimitrios Pavlopoulos, Kunal Shrotri, Anish A. Khandekar
  • Patent number: 10373929
    Abstract: A method of manufacturing a semiconductor device includes forming an insulation layer on a support body, selectively forming openings through the insulation layer, forming a conductor pattern in the openings, and above selected portions of, the insulation layer, mounting a first semiconductor element on the insulation layer and electrically connecting the first semiconductor element to the conductor pattern, forming a resin over the first semiconductor element and the insulation layer, removing the support body after the resin is formed to expose a surface of a portion of the conductor pattern, etching the exposed surface of the portion of the conductor pattern to form a recess over the portion of the conductor pattern, and forming a pad containing a metal different than the metal of the conductor pattern in the recess in contact with the conductor pattern.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 6, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoichiro Kurita
  • Patent number: 10366914
    Abstract: In a manufacturing method for a semiconductor device formed over an SOI substrate, a first epitaxial layer is partially formed over an outer circumference end of a first semiconductor layer in a wide active region. Then, a second epitaxial layer is formed over each of the first semiconductor layers in a narrow active region and the wide active region. Thereby, a second semiconductor layer configured by a laminated body of the first semiconductor layer and the first and second epitaxial layers is formed in the wide active region and a third semiconductor layer configured by a laminated body of the first semiconductor layer and the second epitaxial layer is formed in the narrow active region.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: July 30, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideki Makiyama
  • Patent number: 10367128
    Abstract: The present application discloses a pixel structure and method for the fabrication thereof including: providing a substrate; forming a black photoresist layer having a receiving cavity and an isolation region on the substrate; coating a polyelectrolyte solution on the surface of the black photoresist layer except the isolation region, and air-dried to form a polyelectrolyte layer; coating a metal nanoparticle solution on the surface of the polyelectrolyte layer, and air-dried to form a metal particle layer; and aligning and transferring a micro light emitting diodes to the black photoresist layer. In the above-described manner, the present disclosure can improve the light utilization efficiency of the micro light emitting diode.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: July 30, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Dongze Li, Lixuan Chen
  • Patent number: 10361245
    Abstract: Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment, a solid state transducer device includes a solid state emitter, and an electrostatic discharge device carried by the solid state emitter. In some embodiments, the electrostatic discharge device and the solid state emitter share a common first contact and a common second contact. In further embodiments, the solid state lighting device and the electrostatic discharge device share a common epitaxial substrate. In still further embodiments, the electrostatic discharge device is positioned between the solid state lighting device and a support substrate.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Odnoblyudov, Martin F. Schubert
  • Patent number: 10361193
    Abstract: The present invention provides an integrated circuit formed of tunneling field-effect transistors that includes a first tunneling field-effect transistor in which one of a first P-type region and a first N-type region operates as a source region and the other one operates as a drain region; and a second tunneling field-effect transistor in which one of a second P-type region and a second N-type region operates as a source region and the other one operates as a drain region, the first and second tunneling field-effect transistors being formed in one active region to have the same polarity, the first P-type region and the second N-type region being formed adjacently, the adjacent first P-type region and second N-type region being electrically connected through metal semiconductor alloy film.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: July 23, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventor: Takahiro Mori
  • Patent number: 10361308
    Abstract: A method of forming a semiconductor device that includes forming a gate structure over a plurality of fin structures, wherein the gate structure provides a first fill pinch off between the fin structures separated by a first pitch; and forming a material stack of a silicon containing layer, and a dielectric layer over the plurality of fin structures, wherein the dielectric provides a second fill pinch off between fin structures separated by a second pitch. The silicon containing layer is converted into an oxide material layer. The second dielectric that provides the second fill pinch off is removed, and an opening is etched in a remaining silicon containing layer exposed by removing the second fill pinch off. An underlying gate cut region is etched in the gate structure using the opening in the remaining portion of the silicon containing layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10361114
    Abstract: The present disclosure provides a method for preparing a substrate with a carrier trapping center. The method includes: implanting bubbling ions into the semiconductor substrate to form a splitting layer, and implanting modified ions into the insulating layer to form a nano cluster; providing a supporting substrate; bonding the supporting substrate to the semiconductor substrate by using the insulating layer as an intermediate layer; performing a first heat treatment for the bonded substrate such that a splitting layer is formed at the position where the bubbling ions are implanted, and causing the semiconductor substrate to split at the position of the splitting layer; performing rapid thermal annealing for the substrate; and performing a second heat treatment for the rapidly thermally annealed semiconductor substrate to consolidate the bonding interface and form the nano cluster at the position where the modified ions are implanted.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 23, 2019
    Assignee: SHANGHAI SIMGUI TECHNOLOGY CO., LTD.
    Inventors: Xing Wei, Yongwei Chang, Meng Chen, Guoxing Chen, Lu Fei, Xi Wang
  • Patent number: 10354863
    Abstract: In one instance, the seed crystal of this invention provides a nitrogen-polar c-plane surface of a GaN layer supported by a metallic plate. The coefficient of thermal expansion of the metallic plate matches that of GaN layer. The GaN layer is bonded to the metallic plate with bonding metal. The bonding metal not only bonds the GaN layer to the metallic plate but also covers the entire surface of the metallic plate to prevent corrosion of the metallic plate and optionally spontaneous nucleation of GaN on the metallic plate during the bulk GaN growth in supercritical ammonia. The bonding metal is compatible with the corrosive environment of ammonothermal growth.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 16, 2019
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Edward Letts, Daryl Key
  • Patent number: 10347827
    Abstract: A method of making a spin-torque transfer magnetic random access memory device (STT MRAM) device includes forming a tunnel barrier layer on a reference layer; forming a free layer on the tunnel barrier layer, the free layer comprising a cobalt iron boron (CoFeB) alloy layer and an iron (Fe) layer; and performing a sputtering process to form a metal oxide layer on the Fe layer.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Guohan Hu
  • Patent number: 10347744
    Abstract: Various methods and structures for fabricating a contact for a semiconductor FET or FinFET device. A semiconductor FET structure includes a substrate, a source/drain region layer and source/drain contact. First and second gate spacers are adjacent respective first and second opposing sides of the source/drain contact. The source/drain contact is disposed directly on and contacting the entire source/drain region layer, and at a vertical level thereabove, the source/drain contact being recessed to a limited horizontal area continuing vertically upwards from the vertical level. The limited horizontal area horizontally extending along less than a full horizontal length of a vertical sidewall of the first and second gate spacers, and less than fully covering the source/drain region layer. A method uses a reverse contact mask to form a shape of the source/drain contact into an inverted “T” shape.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10340394
    Abstract: A stacked III-V semiconductor diode having an n+-layer with a dopant concentration of at least 1019 N/cm3, an n?-layer with a dopant concentration of 1012-1016 N/cm3, a layer thickness of 10-300 microns, a p+-layer with a dopant concentration of 5×1018-5×1020 cm3, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n+-layer or the p+-layer is formed as the substrate and a lower side of the n?-layer is materially bonded with an upper side of the n+-layer, and a doped intermediate layer is arranged between the n?-layer and the p+-layer and materially bonded with an upper side and a lower side.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: July 2, 2019
    Assignee: 3-5 Power Electronics GmbH
    Inventor: Volker Dudek