Patents Examined by Sonya D. McCall-Shepard
  • Patent number: 10777419
    Abstract: A fin strip is formed over a substrate using a hardmask. The fin strip includes a first portion and a second portion laterally adjoining the first portion. A BARC layer is formed to cover the fin strip over the substrate. A first etching operation is performed to remove a first portion of the BARC layer, so as to expose a portion of the hardmask where the first portion of the fin strip underlies. A coating layer is deposited over the portion of the hardmask and the BARC layer. A second etching operation is performed to remove a portion of the coating layer, the portion of the hardmask and a second portion of the BARC layer. A third etching operation is performed to remove the first portion of the fin strip and a remaining BARC layer, such that the second portion of the fin strip forms a plurality of semiconductor fins.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10763116
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Ying Lin, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sheng-Yung Lo, C. W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • Patent number: 10748884
    Abstract: An electronic device is disclosed which includes: a substrate; a plurality of active elements disposed on the substrate; a common electrode disposed on the active elements and including a plurality of openings; and a plurality of light-emitting elements, at least one of the light-emitting elements disposed on the common electrode partially, wherein the light-emitting elements each include a first pad and a second pad, and the first pad and the second pad are disposed on a same side of each said light-emitting element, wherein the first pad of one of the light-emitting elements is disposed corresponding to one of the openings of the common electrode and the first pad of the one of the light-emitting elements electrically connects to one of the active elements, and the second pad electrically connects to the common electrode.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: August 18, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Hong-Pin Ko, Chien-Chih Chen
  • Patent number: 10734474
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes a semiconductor substrate and a bottom conductive layer above the semiconductor substrate. The bottom conductive layer has a slanted sidewall with respect to a top surface of the semiconductor substrate. The MIM capacitor structure further includes a top conductive layer above the bottom conductive layer. The top conductive layer has a vertical sidewall with respect to the top surface of the semiconductor substrate. The MIM capacitor structure further includes an insulating layer interposed between the bottom conductive layer and the top conductive layer. The insulating layer covers the slanted sidewall of the bottom conductive layer.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 10734532
    Abstract: A stacked III-V semiconductor diode having an n+-layer with a dopant concentration of at least 1019 N/cm3, an n?-layer with a dopant concentration of 1012-1016 N/cm3, a layer thickness of 10-300 microns, a p+-layer with a dopant concentration of 5×1018-5×1020 cm3, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n+-layer or the p+-layer is formed as the substrate and a lower side of the n?-layer is materially bonded with an upper side of the n+-layer, and a doped intermediate layer is arranged between the n?-layer and the p+-layer and materially bonded with an upper side and a lower side.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: August 4, 2020
    Assignee: 3-5 Power Electronics GmbH
    Inventor: Volker Dudek
  • Patent number: 10734383
    Abstract: An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: August 4, 2020
    Assignee: Tela Innovations, Inc.
    Inventors: Michael C. Smayling, Scott T. Becker
  • Patent number: 10727016
    Abstract: A electromechanical relay device (100) comprising a source electrode (102), a beam (104) mounted on the source electrode at a first end and electrically coupled to the source electrode; a first drain electrode (112) located adjacent a second end of the beam, wherein a first contact (110) on the beam is arranged to be separated from a second contact (112) on the first drain electrode when the relay device is in a first condition; a first gate electrode (106 arranged to cause the beam to deflect, to electrically couple the first contact and the second contact such that the device is in a second condition; and wherein the first and second contacts are each coated with a layer of nanocrystalline graphite.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: July 28, 2020
    Assignee: The University of Bristol
    Inventors: Sunil Rana, Dinesh Pamunuwa, Liam Anand Boodhoo, Harold Meng Hoon Chong
  • Patent number: 10720486
    Abstract: A display apparatus includes a substrate, a display unit disposed on the substrate, an insulating layer disposed on the substrate, a power supply wire disposed on the insulating layer outside the display unit, and a cladding layer. The display unit includes a pixel circuit and a display element electrically connected to the pixel circuit. The insulating layer extends from the display unit to an edge of the substrate. The power supply wire is electrically connected to the display element and includes an alignment pattern that exposes at least a portion of the insulating layer. The cladding layer covers an inner surface of the alignment pattern and contacts the at least a portion of the insulating layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Zail Lhee, Keunsoo Lee
  • Patent number: 10720416
    Abstract: A semiconductor device includes a bottom package, a top package, and a heat dissipating structure. The bottom package includes a redistribution structure, and a die disposed on a first surface of the redistribution structure and electrically connected to the redistribution structure. The top package is disposed on a second surface of the redistribution structure opposite to the first surface. The heat dissipating structure is disposed over the bottom package, and includes a thermal relaxation block. The thermal relaxation block contacts the redistribution structure and is disposed beside the top package.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Patent number: 10707296
    Abstract: An integrated circuit (IC) includes a first capacitor, a second capacitor, and functional circuitry configured together with the capacitors for realizing at least one circuit function in a semiconductor surface layer on a substrate. The capacitors include a top plate over a LOCal Oxidation of Silicon (LOCOS) oxide, wherein a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. There is a contact for the top plate and a contact for a bottom plate for the first and second capacitors.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: July 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Henry Litzmann Edwards
  • Patent number: 10707155
    Abstract: A semiconductor device includes a semiconductor layer that has a main surface including a defined region defined by a trench, a trench insulation layer formed in the trench, a field insulation layer that covers the defined region away from the trench, and a bridge insulation layer that is formed in a region between the trench and the field insulation layer in the defined region and that is connected to the trench insulation layer and to the field insulation layer.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: July 7, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Hajime Okuda, Yoshinori Fukuda
  • Patent number: 10700056
    Abstract: A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: June 30, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventors: James Zhao, Javier Alejandro Salcedo, Srivatsan Parthasarathy
  • Patent number: 10700269
    Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Wang, Dongna Shen, Vignesh Sundar, Sahil Patel
  • Patent number: 10692894
    Abstract: An object is to control composition and a defect of an oxide semiconductor, another object is to increase a field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with a reduced off current. A solution is to employ an oxide semiconductor whose composition is represented by InMO3(ZnO)m, where M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al, and m is preferably a non-integer number of greater than 0 and less than 1. The concentration of Zn is lower than the concentrations of In and M. The oxide semiconductor has an amorphous structure. Oxide and nitride layers can be provided to prevent pollution and degradation of the oxide semiconductor.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: June 23, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunichi Ito, Toshinari Sasaki, Miyuki Hosoba, Junichiro Sakata
  • Patent number: 10692804
    Abstract: A semiconductor device package includes an interposer and a semiconductor device. The interposer has a sidewall defining a space. The semiconductor device is disposed within the space and in contact with the sidewall. An interposer includes a first surface, a second surface and a third surface. The first surface has a first crystal orientation. The second surface is opposite the first surface and has the first crystal orientation. The third surface connects the first surface to the second surface, and defines a space. An angle defined by the third surface and the first surface ranges from about 90° to about 120°.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: June 23, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10692822
    Abstract: In some examples, an electrostatic discharge (ESD) device includes a substrate layer, a transition layer positioned on the substrate layer, a plurality of superlattice layers on the transition layer and including at least two doped superlattice layers. The ESD device further includes a plurality of doped contact structures extending from the transition layer to a surface of an outermost layer of the plurality of superlattice layers, where a first of the plurality of doped contact structures comprises an anode and a second of the plurality of doped contact structures comprises a cathode, where the plurality of doped contact structures are to generate a zero capacitance ESD device.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: June 23, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: He Lin
  • Patent number: 10685899
    Abstract: A conductive lid includes a body including a first portion extended from the body and bent toward a first direction; a second portion extended from the body and bent toward the first direction; and a third portion extended from the second portion and bent toward a second direction different from the first direction.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: June 16, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsin-En Chen
  • Patent number: 10680063
    Abstract: Stacked SiGe nanotubes and techniques for the fabrication thereof are provided. In one aspect, a method of forming a SiGe nanotube stack includes: forming Si and SiGe layers on a wafer, one on top of another, in an alternating manner; patterning at least one fin in the Si and SiGe layers; depositing an oxide material onto the at least one fin; and annealing the at least one fin under conditions sufficient to diffuse Ge atoms from the SiGe layers along an interface between the oxide material and the Si and SiGe layers to form at least one vertical stack of SiGe nanotubes surrounding Si cores. A SiGe nanotube device and method for formation thereof are also provided.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Choonghyun Lee
  • Patent number: 10672625
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a recess, an electronic component disposed in the recess and electrically coupled to the substrate, and an underfill material disposed in the recess between the electronic component and the substrate. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Sergio A. Chan Arguedas, Joshua D. Heppner, Jimin Yao
  • Patent number: 10672607
    Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 2, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gordon M. Grivna, Stephen St. Germain