Abstract: A semiconductor package has a semiconductor chip on a wiring board, sealed with a sealant. A semiconductor package substrate is formed with V grooves along division lines from a resin layer side by use of a V blade. The wiring board is divided along the V grooves into individual semiconductor packages, while forming an inclined surface and a vertical surface at each package side surface. A shield layer is formed on the package upper surface and the package side surfaces. In this instance, the aspect ratio at the vertical surface side of the package interval is controlled, whereby an appropriate shield layer is formed on the package upper surface and the package inclined surfaces, thereby securing a shielding effect, and the shield layer is formed in a thin form on the package vertical surfaces and on the groove bottom between the packages, thereby restraining generation of burs.

Abstract: A method of manufacturing an oxidation layer for a solar cell is disclosed. The method includes exposing a substrate to a wet oxidation atmosphere and forming an oxidation layer on the substrate by maintaining a concentration of an oxidizing agent in the wet oxidation atmosphere for a process time.

Abstract: Methods and apparatuses for selectively depositing silicon nitride on silicon surfaces relative to silicon oxide surfaces and selectively depositing silicon nitride on silicon oxide surfaces relative to silicon surfaces are provided herein. Methods involve blocking one surface while leaving another surface unblocked and selectively depositing silicon nitride on the unblocked surface. The blocked surface may include an organic moiety having an Si—C bond. The method may include blocking one of an exposed hydroxyl-terminated silicon-containing surface and an exposed hydrogen-terminated silicon-containing surface of the substrate. Apparatuses include a process chamber having a pedestal, an outlet, and a controller for providing instructions for causing delivery of a semiconductor substrate to the pedestal, causing introduction of a silicon-containing precursor and causing introduction of a nitrogen-containing reactant without igniting a plasma.

Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.

Abstract: An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.

Abstract: An image sensor may include an array of imaging pixels. Each imaging pixel may have a photosensitive area that is covered by a respective multipart diffractive lens to focus light onto the photosensitive area. The multipart diffractive lenses may have multiple portions with different indices of refraction. The portions of the diffractive lenses closer to the center of the diffractive lenses may have higher indices of refraction to focus light. Alternatively, the portions of the diffractive lenses closer to the center of the diffractive lenses may have lower indices of refraction to defocus light. The multipart diffractive lenses may have stacked layers with the same refractive indices but different widths.

Abstract: A semiconductor memory device includes a first electrode layer extending in a first direction, a second electrode layer above the first electrode layer and extending in the first direction, a third electrode layer above the first electrode layer and extending in the first direction, an insulating member between the second and third electrode layers and extending in the first direction, first semiconductor members extending in the second direction through the first and second electrodes, second semiconductor members extending in the second direction through the first and third electrode layers, and third semiconductor members extending in the second direction, each having a first portion between the second and third electrode layers and in contact with the insulating member, and a second portion extending through the first electrode layer. In the first direction, an arrangement density of the third semiconductor members is lower than that of the first or second semiconductor member.

Abstract: The present invention provides a TFT substrate manufacturing method and a TFT substrate. In the TFT substrate manufacturing method of the present invention, a pattern of the gate metal layer has been designed such that reflective blocks are included in a gate metal layer at locations corresponding to areas in which connection holes are to be formed so that in a process of forming the connection holes, light is reflected by the reflective blocks to enhance intensity of exposure on locations where the connection holes are formed. Thus, even under the condition that limit exposure size of an existing exposure machine is constrained, it is still possible to ensure full exposure in forming the connection holes in a high PPI display panel device to thereby realize production of high display panel products.

Abstract: A microelectronic device on a semiconductor substrate comprises: a gate electrode; and a spacer adjacent to the gate electrode, the spacer comprising: a the low-k dielectric film comprising one or more species of vanadium oxide, which is optionally doped, and an optional silicon nitride or oxide film. Methods comprise depositing a low-k dielectric film optionally sandwiched by a silicon nitride or oxide film to form a spacer adjacent to a gate electrode of a microelectronic device on a semiconductor substrate, wherein the low-k dielectric film comprises a vanadium-containing film.

Abstract: A silicon-on-insulator (SOI) substrate includes a semiconductor substrate and a multi-layered polycrystalline silicon structure. The multi-layered polycrystalline silicon structure is disposed over the semiconductor substrate. The multi-layered polycrystalline silicon structure includes a plurality of polycrystalline silicon layers stacked over one another, and a native oxide layer between each adjacent pair of polycrystalline silicon layers.

Abstract: Provided is a semiconductor device according to an embodiment including a plate-shaped first metal terminal, a plate-shaped second metal terminal provided to face the first metal terminal, a resin layer provided between the first metal terminal and the second metal terminal, and a semiconductor chip having a first upper electrode electrically connected to the first metal terminal and a first lower electrode electrically connected to the second metal terminal, wherein a first distance between the first metal terminal and the second metal terminal at the end portion of the first metal terminal is larger than a second distance between the first metal terminal and the second metal terminal at a portion inside the end portion of the first metal terminal.

Abstract: There is provided a solid state imaging apparatus, including: an optical film layer on which a solid state image sensor is mounted; a multifunctional chip laminated at a periphery of the solid state image sensor in the optical film layer being electrically contacted with the optical film layer via a metal body; a sealing resin layer for sealing the periphery where the multifunctional chip is laminated on the optical film layer; and a concave structure for blocking a flow of the sealing resin in a liquid state when the sealing resin layer is formed at the periphery of the sealing resin layer. Also, a method of producing the solid state imaging apparatus is also provided.

Abstract: A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.

Abstract: The present disclosure relates to a chemical vapor deposition apparatus and associated methods. In some embodiments, the CVD apparatus has a vacuum chamber and a gas import having a gas import axis through which a process gas is imported into the vacuum chamber and being arranged near an upper region of the vacuum chamber. At least one exhaust port is arranged near a bottom region of the vacuum chamber. The CVD apparatus also has a shower head arranged under the gas import having a plurality of holes formed there through with at least two different diameters or densities. The shower head redistributes the process gas to form a precursor material with an uneven thickness that matches a remove profile of a subsequent CMP process. As a result, planarity of the formed layer after the CMP process is improved.

Abstract: The purpose is providing a vapor deposition mask with high rigidity which can evaporate a uniform thickness film. A vapor deposition mask including a mask body having a main opening, a side surface of the main opening, an upper surface intersecting the side surface, and a lower surface opposing the upper surface, a first insulator contacting the lower surface, and a second insulator contacting the upper and side surfaces, wherein the first insulator includes a first region inside the main opening, and a first opening in the first region, the second insulator includes a second region inside the main opening, and a second opening in the second region, the mask body is sandwiched between the first and second insulators, and one of the first and second insulators includes a region located inside the main opening more centrally than the other and not overlapping with the other and the mask body.

Abstract: An epitaxial substrate and a method for forming the same are disclosed. The epitaxial substrate includes a substrate, a deposition layer, a buffer layer and an epitaxial layer. The deposition layer is directly formed on the substrate, wherein the deposition layer includes a gradient doping concentration, and has a first surface and a second surface which are opposite to each other; the gradient doping concentration has a minimum value at the first surface. The buffer layer is formed on the deposition layer, and an epitaxial layer is formed on the buffer layer. The epitaxial layer is mainly formed of group III-V nitride. The substrate and the deposition layer are formed of homogeneous material. Since the deposition layer is directly formed on the substrate, and the deposition layer and the substrate are formed of a homogeneous material, the epitaxial substrate includes a good heat dissipation efficiency and low leakage current.

Abstract: A magnetic device for magnetic random access memory (MRAM), spin torque MRAM, or spin torque oscillator technology is disclosed wherein a magnetic tunnel junction (MTJ) with a sidewall is formed between a bottom electrode and a top electrode. A passivation layer that is a single layer or multilayer comprising one of B, C, or Ge, or an alloy thereof wherein the B, C, and Ge content, respectively, is at least 10 atomic % is formed on the MTJ sidewall to protect the MTJ from reactive species during subsequent processing including deposition of a dielectric layer that electrically isolates the MTJ from adjacent MTJs, and during annealing steps around 400° C. in CMOS fabrication. The single layer is about 3 to 10 Angstroms thick and may be an oxide or nitride of B, C, or Ge. The passivation layer is preferably amorphous to prevent diffusion of reactive oxygen or nitrogen species.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

Abstract: A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.

Abstract: An inverse diode die is “fast” (i.e., has a small peak reverse recovery current) due to the presence of a novel topside P+ type charge carrier extraction region and a lightly-doped bottomside transparent anode. During forward conduction, the number of charge carriers in the N? type drift region is reduced due to holes being continuously extracted by an electric field set up by the P+ type charge carrier extraction region. Electrons are extracted by the transparent anode. When the voltage across the device is then reversed, the magnitude of the peak reverse recovery current is reduced due to there being a smaller number of charge carriers that need to be removed before the diode can begin reverse blocking mode operation. Advantageously, the diode is fast without having to include lifetime killers or otherwise introduce recombination centers. The inverse diode therefore has a desirably small reverse leakage current.