Abstract: The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

Abstract: A method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed, wherein the drain electrode is separated from a first location of the plate structure by a first distance along a central axis of an active area of the semiconductor device in a direction of a current flow between a source and a drain of the semiconductor device, the drain electrode is separated from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

Abstract: A method includes, through a backside of a substrate, removing a portion of a gate structure to form a trench that isolates the gate structure in two portions. The method further includes depositing a sacrificial material within the trench and conformally along sidewalls of the trench, filling a remainder of the trench with a first dielectric material, partially removing the sacrificial material to leave an opening between the first dielectric material and the gate structure, and filling the opening with a work-function metal.

Abstract: A transistor includes a bulk semiconductor substrate, and a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region. A first air gap is defined in the bulk semiconductor substrate under the first source/drain region, and a second air gap is defined in the bulk semiconductor substrate under the second source/drain region. A gate is over the channel region. A spacing between the first air gap and the second air gap is greater than or equal to a length of the channel region such that the first and second air gaps are not under the channel region. The air gaps may have a rectangular cross-sectional shape. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.

Abstract: A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a semiconductor device structure is provided. The semiconductor device structure a first source/drain region, a second source/drain region, and a gate stack disposed between the first source/drain region and the second source/drain region. The semiconductor device structure also includes a conductive feature disposed below the first source/drain region. The semiconductor device structure also includes a power rail disposed below and in contact with the conductive feature. semiconductor device structure also includes a dielectric layer enclosing the conductive feature, wherein an air gap is formed between the dielectric layer and the conductive feature.

Abstract: An object is to control composition and a defect of an oxide semiconductor, another object is to increase a field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with a reduced off current. A solution is to employ an oxide semiconductor whose composition is represented by InMO3(ZnO)m, where M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al, and m is preferably a non-integer number of greater than 0 and less than 1. The concentration of Zn is lower than the concentrations of In and M. The oxide semiconductor has an amorphous structure. Oxide and nitride layers can be provided to prevent pollution and degradation of the oxide semiconductor.

Abstract: A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.

Abstract: A semiconductor device includes a first device fin and a second device fin. A first source/drain component is epitaxially grown over the first device fin. A second source/drain component is epitaxially grown over the second device fin. A first dummy fin structure is disposed between the first device fin and the second device fin. A gate structure partially wraps around the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is disposed between the first source/drain component and the second source/drain component and outside the gate structure. A second portion of the first dummy fin structure is disposed underneath the gate structure. The first portion of the first dummy fin structure and the second portion of the first dummy fin structure have different physical characteristics.

Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width.

Abstract: A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer.

Abstract: A semiconductor device includes a substrate including first and second active regions extending in a first direction and isolated from direct contact with each other in the first direction; a device isolation layer between the first and second active regions in the substrate; and first and second gate structures extending in a second direction on the substrate while respectively intersecting end portions of the first and second active regions. The first gate structure includes a first gate electrode. The second gate structure includes a second gate electrode. The first gate structure protrudes further toward the device isolation layer, as compared to the second gate structure, in a vertical direction that is perpendicular to the first and second directions, and a lower end of the first gate electrode is located on a lower height level than a lower end of the second gate electrode.

Abstract: There is provided a method of manufacturing a semiconductor device, including forming a metal nitride film substantially not containing a silicon atom on a substrate by sequentially repeating: (a) supplying a metal-containing gas and a reducing gas, which contains silicon and hydrogen and does not contain a halogen, to the substrate in a process chamber by setting an internal pressure of the process chamber to a value which falls within a range of 130 Pa to less than 3,990 Pa during at least the supply of the reducing gas, wherein (a) includes a timing of simultaneously supplying the metal-containing gas and the reducing gas; (b) removing the metal-containing gas and the reducing gas that remain in the process chamber; (c) supplying a nitrogen-containing gas to the substrate; and (d) removing the nitrogen-containing gas remaining in the process chamber.

Abstract: A method for etching back a hard mask layer on top of dummy polysilicon gates in a gate last process comprises: step 1: forming a plurality of dummy gate structures; step 2: depositing a spin-on carbon (SOC) layer to fill the space regions between the sidewalls of the dummy gate structures to a level above the top surface of each of the plurality of dummy gate structures; step 3: performing a first etching-back to the spin-on carbon layer to remove the SOC layer outside the space regions and keep the SOC layer in the space regions below the top surfaces of each of dummy polysilicon gate; step 4: performing a second etching-back by using the remaining spin-on carbon layer as a mask to remove the hard mask layer and the sidewalls of the dummy polysilicon gates on both sides of the hard mask layer at the same time; step 5: removing the SOC layer. This technique saves one photomask and improves the process window.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a substrate having an isolation structure therein and a capacitor structure located on an upper top surface of the isolation structure. The capacitor structure comprises a first semiconductor structure and a second semiconductor structure respectively disposed on the upper surface of the isolation structure and separated by an insulator pattern.

Abstract: A system, method and device for use as a reflector for a light emitting diode (LED) are disclosed. The system, method and device include a first layer designed to reflect transverse-electric (TE) radiation emitted by the LED, a second layer designed to block transverse-magnetic (TM) radiation emitted from the LED, and a plurality of ITO layers designed to operate as a transparent conducting oxide layer. The first layer may be a one-dimension (1D) distributed Bragg reflective (DBR) layer. The second layer may be a two-dimension (2D) photonic crystal (PhC), a three-dimension (3D) PhC, and/or a hyperbolic metamaterial (HMM). The 2D PhC may include horizontal cylinder bars, vertical cylinder bars, or both. The system, method and device may include a bottom metal reflector that may be Ag free and may act as a bonding layer.

Abstract: Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

Abstract: In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.