Abstract: A power semiconductor device, including a terminal base, is provided. The terminal base has a first end and a second end opposite to each other. The first end has a first flange expanding outward. The first flange is welded to a pad of a substrate by a solder. An included angle between an extension direction of the first flange and a length direction of the terminal base is greater than 90 degrees.

Abstract: A bonding film for bonding a semiconductor element and a substrate. The bonding film has an electroconductive bonding layer formed by molding an electroconductive paste including metal fine particles (P) into a film form, and a tack layer having tackiness and laminated on the electroconductive bonding layer. The tack layer includes 0.1% to 1.0% by mass of metal fine particles (M) with respect to the metal fine particles (P) in the electroconductive bonding layer, and the metal fine particles (M) have a melting point of 250° C. or lower.

Abstract: A semiconductor device includes a semiconductor substrate, a channel region, a gate structure, two epitaxial structures, and two silicide structures. The channel region is disposed on the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and over the channel region. The epitaxial structures are connected at opposite ends of the channel region and are disposed opposite to each other relative to the gate structure. The silicide structures respectively surround the epitaxial structures. A method of manufacturing a semiconductor device is also provided.

Abstract: A semiconductor manufacturing apparatus includes a thrust-up unit having a plurality of blocks in contact with a dicing tape, a head having a collet absorbing the die and capable of being moved up and down, and a control section controlling the operation of the thrust-up unit and the head. The thrust-up unit can operate each of the plurality of blocks independently. The control section configures the thrust-up sequences of the plurality of blocks in a plurality of steps, and controls the operation of the plurality of blocks on the basis of a time chart recipe capable of setting the height and the speed of the plurality of blocks for each block and in each step.

Abstract: A light emitting apparatus according to an aspect of the present disclosure includes a substrate, a first light emitting section, a second light emitting section, a first electrode, a second electrode, a first protective layer, and a second protective layer. The area of the first electrode is greater than the area of the second electrode, the first protective layer has a first through hole, and the second protective layer has a second through hole. The first through hole has a first hole and a second hole, and the second through hole has a third hole and a fourth hole. A first opening area is greater than a second opening area, and a third opening area is greater than a fourth opening area of an opening of the fourth hole that is the opening closest to the substrate, the outer edge of the second opening overlaps with the first electrode, and the outer edge of the fourth opening overlaps with the second electrode. The second opening area is greater than the fourth opening area.

Abstract: A semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, and an insulating adhesive layer between the first semiconductor chip, and each of the plurality of second semiconductor chips, each of the plurality second conductor chips, and the insulating adhesive layer including an adhesive fillet protruding from between at least the first semiconductor chip and each of the plurality of second semiconductor chips, wherein a grooving recess is defined by the first semiconductor chip, the plurality of second semiconductor chips, and the insulating adhesive layer, the grooving recess including a first recess and a second recess adjacent to the first recess, an uppermost surface of the adhesive fillet and the first semiconductor chip defines the first recess, and an uppermost surface of the first semiconductor chip to a surface inside the first semiconductor chip defines the second recess.

Abstract: A light-emitting diode (LED) includes a transmissible substrate, an epitaxial layered structure, a distributed Bragg reflector (DBR) structure, a first electrode, and a second electrode. The epitaxial layered structure is disposed on the transmissible substrate. The DBR structure is disposed on the epitaxial layered structure opposite to the transmissible substrate. The DBR structure has at least one first through hole and at least one second through hole, and is formed with a plurality of voids. The first electrode and the second electrode are electrically connected to the first semiconductor layer and the second semiconductor layer, respectively. An LED packaged module including the LED is also disclosed.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor structure including a substrate, a gallium nitride layer, semiconductor device units, and a scribe line region is provided. The gallium nitride layer is disposed on a first surface of the substrate. The semiconductor device units and the scribe line region are disposed on the gallium nitride layer. The scribe line region is located between the semiconductor device units. A trench is formed at a second surface of the substrate. The trench is formed corresponding to the scribe line region in a vertical direction. The trench penetrates through at least a part of the substrate in the vertical direction. A metal layer is formed on the substrate after the trench is formed. A cutting process is performed to the semiconductor structure after the metal layer is formed for separating the semiconductor device units from one another.

Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.

Abstract: An organic light-emitting display apparatus and a manufacturing method thereof have improved process stability and reliability by reducing damage to the organic light-emitting display apparatus during a manufacturing process. The organic light-emitting display apparatus includes: a substrate, a plurality of pixel electrodes, a pixel defining film, a plurality of hole control layers respectively arranged on the pixel electrodes, a plurality of emission layers respectively arranged on the hole control layers, a plurality of buffer layers respectively arranged on the emission layers, each of the buffer layers having a highest occupied molecular orbital (HOMO) energy level greater than the HOMO energy level of each of the plurality of emission layers, and an opposite electrode integrally provided over the buffer layers.

Abstract: An organic light emitting display device includes: a display panel configured to display an image on a first surface of the display panel, and including: a first display area including a first sub-pixel area, and having a first resolution; and a second display area including a second sub-pixel area and a first transmission area, and having a second resolution that is lower than the first resolution; and a first optical sensor on a second surface of the display panel opposite to the first surface to overlap with the second display area. Accordingly, an image may be displayed at a portion where the first optical module is disposed.

Abstract: Discussed is a plurality of semiconductor light-emitting devices, wherein at least one of the semiconductor light-emitting devices includes: a first conductive electrode and a second conductive electrode; a first conductive semiconductor layer having the first conductive electrode arranged thereon; a second conductive semiconductor layer overlapping the first conductive semiconductor layer and having the second conductive electrode arranged thereon; an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer; an intermediate layer arranged on the second conductive semiconductor layer; a protrusion, made of an electro-polishable porous material, on the intermediate layer; and an undoped semiconductor layer arranged between the intermediate layer and the protrusion.

Abstract: A semiconductor structure that includes at least one lateral diffusion field effect transistor is described. The structure includes a source contact and a gate shield that enables the line width of an ohmic region that electrically connects the source/body region to the gate shield to be smaller than the minimum contact feature size. The gate shield defines a bottom recess for forming a narrower bottom portion of the source contact, and a section that flares outward with distance from the ohmic region to extend above and laterally beyond the ohmic region. By providing a wider area for the source contact, the flared portion of the gate shield allows the portion of the gate shield that contacts the ohmic region to be narrower than the minimum contact feature size. As a result, the cell pitch of the lateral diffusion field effect transistor can be reduced.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first fin structure and a second fin structure formed over the substrate. In addition, the second fin structure is higher than the first fin structure. The semiconductor structure further includes an isolation structure formed around the second fin structure and covering a top surface of the first fin structure and a gate structure formed over the first fin structure and the second fin structure. In addition, the top surface of the first fin structure is not flat.

Abstract: A method, includes: in a strap cell disposed between a memory cell and a logic cell, arranging a first gate across an active region; arranging a second gate next to and in parallel with the first gate and at an end of the active region; and when at least one conductive segment has a first length, arranging the at least one conductive segment across the first gate, the second gate, and no dummy gate in the strap cell. A semiconductor device is also disclosed herein.

Abstract: A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.

Abstract: Overmolded microelectronic packages containing knurled base flanges are provided, as are methods for producing the same. In various embodiments, the overmolded microelectronic package includes a molded package body, at least one microelectronic device contained in the molded package body, and a base flange to which the molded package body is bonded. The base flange includes, in turn, a flange frontside contacted by the molded package body, a device attachment region located on the flange frontside and to which the at least one microelectronic is mounted, and a knurled surface region. The knurled surface region includes a first plurality of trenches formed in the base flange and arranged in a first repeating geometric pattern. The molded package body extends or projects into the first plurality of trenches to decrease the likelihood of delamination of the molded package body from the base flange.

Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.

Abstract: A bonded body is provided including: a bonding layer containing Cu; and a semiconductor element bonded to the bonding layer. The bonding layer includes an extending portion laterally extending from a peripheral edge of the semiconductor element. In a cross-sectional view in a thickness direction, the extending portion rises from a peripheral edge of a bottom of the semiconductor element or from the vicinity of the peripheral edge of the bottom of the semiconductor element, and includes a side wall substantially spaced apart from a side of the semiconductor element. Preferably, the extending portion does not include any portion where the side wall and the side of the semiconductor element are in contact with each other. A method for manufacturing a bonded body is also provided.

Abstract: A method for depositing, patterning and removing a layer of aluminum oxide as a masking material layer for performing a deep, high-aspect ratio etches into a substrate. The method comprising deposing a photoresist onto the substrate, performing lithography processing on the photoresist, developing the photoresist to pattern the photoresist into a mask design, depositing a thin-film layer of aluminum oxide; immersing the substrate into a solution to lift-off the aluminum oxide in regions where the aluminum oxide is deposited on top of the photoresist thereby leaving the patterned aluminum oxide layer on the substrate where no photoresist was present, performing deep reactive ion etching on the substrate wherein the hard masking material layer composed of aluminum oxide functions as a protective masking layer on the substrate to prevent etching from occurring where the aluminum oxide is present, and removing the aluminum oxide masking layer by immersion in a solution.