Patents Examined by Stanetta D Isaac
  • Patent number: 11031383
    Abstract: A memory device is disclosed that includes memory cell, e strap cell, conductive segment, and logic cell. The strap cell is arranged abutting the memory cell. The strap cell includes an active region, a first gate, and a second gate. The first gate is arranged across the active region. The second gate is arranged across the active region and disposed at the end of active region. The conductive segment is disposed over the first gate and the second gate. The strap cell is disposed between the memory cell and the logic cell, and the logic cell includes a third gate. The conductive segment is spaced apart from the third gate, and the length of the conductive segment is smaller than five times of a gate pitch between the first gate and the second gate.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jacklyn Chang, Derek C. Tao, Kuo-Yuan Hsu
  • Patent number: 11011654
    Abstract: A photodiode with a lens cap is provided, having a header with a photodiode active surface area where the photodiode active surface area has a diameter dF. Further included is a cap having a fused-in lens, the fused-in lens having a diameter dL shown in a top plan view of the cap. The ratio of the diameter of the fused-in lens to the diameter of the photodiode active surface area, dL/dF, is greater than 30.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 18, 2021
    Assignee: Schott AG
    Inventors: Robert Hettler, René Nauthe, Georg Mittermeier
  • Patent number: 10998531
    Abstract: Implementations of the disclosed subject matter provide a print bar for organic vapor jet (OVJP) deposition is provided that includes a plurality of n print head segments, where each of the plurality of print head segments may have an OVJP print head. The print bar may include a plurality of distance sensors, where each of the plurality of distance sensors may be configured to measure a distance between a substrate disposed below the print bar and a portion of at least one of the print head segments. The print bar may include a plurality of not more than n+1 actuators configured to adjust at least one of a position and an orientation of one or more of the plurality of print head segments based upon one or more distances between the substrate and the print bar measured by one or more of the plurality of distance sensors.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: May 4, 2021
    Assignee: Universal Display Corporation
    Inventors: William E. Quinn, Gregory McGraw
  • Patent number: 10998255
    Abstract: Overmolded microelectronic packages containing knurled base flanges are provided, as are methods for producing the same. In various embodiments, the overmolded microelectronic package includes a molded package body, at least one microelectronic device contained in the molded package body, and a base flange to which the molded package body is bonded. The base flange includes, in turn, a flange frontside contacted by the molded package body, a device attachment region located on the flange frontside and to which the at least one microelectronic is mounted, and a knurled surface region. The knurled surface region includes a first plurality of trenches formed in the base flange and arranged in a first repeating geometric pattern. The molded package body extends or projects into the first plurality of trenches to decrease the likelihood of delamination of the molded package body from the base flange.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 4, 2021
    Assignee: NXP USA, Inc.
    Inventors: Audel Sanchez, Jerry Lynn White, Hamdan Ismail, Frank Danaher, David James Dougherty, Aruna Manoharan
  • Patent number: 10991760
    Abstract: A memory device includes first and second peripheral regions in which peripheral circuits related to data input/output are disposed, a normal cell region which is disposed on the first peripheral region, and in which a plurality of memory cells storing data are formed, and a dummy cell region which is disposed on the second peripheral region, and in which a plurality of dummy cells forming a plurality of capacitors are formed.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: April 27, 2021
    Assignee: SK hynix Inc.
    Inventor: Ji-Hoon Hong
  • Patent number: 10991695
    Abstract: Disclosed is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes forming a p-channel over a semiconductor substrate. A gate dielectric layer is formed over the p-channel. The gate dielectric layer is doped with a dopant. A first metal gate is formed over the gate dielectric layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yuan Chang, Xiong-Fei Yu, Hui-Cheng Chang
  • Patent number: 10991694
    Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: April 27, 2021
    Inventors: Sung-Dae Suk, Jongho Lee, Geumjong Bae
  • Patent number: 10978556
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: April 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wanxun He, Su Xing
  • Patent number: 10971577
    Abstract: According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn. The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh Li, Hao-chieh Chan
  • Patent number: 10964512
    Abstract: Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include a mixing manifold coupled between the remote plasma unit and the processing chamber. The mixing manifold may be characterized by a first end and a second end opposite the first end, and may be coupled with the processing chamber at the second end. The mixing manifold may define a central channel through the mixing manifold, and may define a port along an exterior of the mixing manifold. The port may be fluidly coupled with a first trench defined within the first end of the mixing manifold. The first trench may be characterized by an inner radius at a first inner sidewall and an outer radius, and the first trench may provide fluid access to the central channel through the first inner sidewall.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: March 30, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Mehmet Tugrul Samir, Dongqing Yang, Dmitry Lubomirsky
  • Patent number: 10957735
    Abstract: An LED display includes a wafer-level substrate, a first adhesive layer, a plurality of first light-emitting assemblies, and a first conductive structure. The wafer-level substrate includes a plurality of control circuits, each of which has a conductive contact. The first adhesive layer is disposed on the wafer-level substrate. Each first light-emitting assembly includes a plurality of first LED structures disposed on the first adhesive layer. The first conductive structure is electrically connected between the corresponding first LED structure and the control circuit. Thereby, each first light-emitting assembly including a plurality of first LED structures and a wafer-level substrate having a plurality of control circuits can be connected to each other through a first adhesive layer.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: March 23, 2021
    Assignee: ASTI GLOBAL INC., TAIWAN
    Inventor: Chien-Shou Liao
  • Patent number: 10950461
    Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5 exp(5.4×103tN?)??expression 1 ?: the lifetime of carriers in the drift layer tN?: the layer thickness of the drift layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 16, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 10930511
    Abstract: In one example, an electroplating system comprises a first bath reservoir, a second bath reservoir, a clamp, a first anode in the first bath reservoir, a second anode in the second bath reservoir, and a direct current power supply. The first bath reservoir contains a first electrolyte solution that includes an alkaline copper-complexed solution. The second bath reservoir contains a second electrolyte solution that includes an acidic copper plating solution. The direct current power supply generates a first direct current between the clamp and the first anode to electroplate a first copper layer on the cobalt layer of the wafer submerged in the first electrolyte solution. The direct current power supply then generates a second direct current between the clamp and the second anode to electroplate a second copper layer on the first copper layer of the wafer submerged in the second electrolyte solution.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 23, 2021
    Assignee: Lam Research Corporation
    Inventors: Jeyavel Velmurugan, Bryan Buckalew, Thomas Ponnuswamy
  • Patent number: 10921649
    Abstract: A display device includes a first substrate, a second substrate, a first conductive layer, a first insulating layer, a second conductive layer and a spacer. The second substrate is disposed opposite to the first substrate. The first conductive layer is disposed on the first substrate and includes the first conductive line and the first dummy pad thereon. The first dummy pad and the first conductive line are disposed adjacent to each other. The first insulating layer is disposed on the first conductive layer. The second conductive layer is disposed on the first insulating layer and include a conductive pad partially overlap the first dummy pad. The spacer is disposed between the first substrate and the second substrate and partially overlaps the first conductive line.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 16, 2021
    Assignee: InnoLux Corporation
    Inventors: Chi-Hsuan Nieh, Yu-Chien Kao, Po-Ju Yang, Shih-I Huang
  • Patent number: 10916444
    Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5 exp(5.4×103tN?)??expression 1 ?: the lifetime of carriers in the drift layer tN?: the layer thickness of the drift layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 9, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 10916446
    Abstract: A method is provided for monitoring the laser annealing of a semiconductor wafer. After annealing, images of many regions of the wafer are captured. The surface brightness of these regions is measured by computer, and statistics of these surface brightness measurements are determined, such as their mean and their standard deviation. Using a correlation between the surface brightnesses and the electrical resistance of the annealed wafer, the surface brightness statistics can be used to determine whether the annealing process resulted in a wafer that meets end user specifications. The surface brightness statistics can also be used to monitor the annealing tool, both during manufacturing and periodically or following maintenance.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: February 9, 2021
    Assignee: X-FAB TEXAS, INC.
    Inventor: Frank Supplieth
  • Patent number: 10910302
    Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: February 2, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca Stella, Agatino Minotti
  • Patent number: 10903427
    Abstract: A deposition system that mitigates feathering in a directly deposited pattern of organic material is disclosed. Deposition systems in accordance with the present disclosure include an evaporation source, an electrically conductive shadow mask, and an electrically conductive field plate. The source imparts a negative charge on vaporized organic molecules as they are emitted toward a target substrate. The source and substrate are biased to produce an electric field having field lines that extend normally between them. The shadow mask and field plate are located between the source and substrate and each functions as an electrostatic lens that directs the charged vapor molecules toward propagation directions aligned with the field lines as the charged vapor molecules approach and pass through them.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: January 26, 2021
    Assignee: eMagin Corporation
    Inventors: Munisamy Anandan, Amalkumar P. Ghosh
  • Patent number: 10892431
    Abstract: An organic electroluminescent element includes, in order, a first electrode, an organic layer that includes an organic electroluminescent layer, an interface adjustment layer, a resistive layer, and a second electrode. The resistive layer has a specific resistance higher than a specific resistance of the second electrode. The interface adjustment layer has a specific resistance higher than the specific resistance of the second electrode and lower than the specific resistance of the resistive layer.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: January 12, 2021
    Assignee: JOLED INC.
    Inventors: Shina Kirita, Takayuki Shimamura
  • Patent number: 10879461
    Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyo June Kim, Chi Ho Kim, Sang Hoon Cho, Eung Rim Hwang