Abstract: A silver nano-twinned thin film structure and a method for forming the same are provided. A silver nano-twinned thin film structure, including: a substrate; an adhesive-lattice-buffer layer over the substrate; and a silver nano-twinned thin film over the adhesive-lattice-buffer layer, wherein the silver nano-twinned thin film comprises parallel-arranged twin boundaries, and a cross-section of the silver nano-twinned thin film reveals that 50% or more of all twin boundaries are parallel-arranged twin boundaries, wherein the parallel-arranged twin boundaries include ?3 and ?9 boundaries, wherein the ?3 and ?9 boundaries include 95% or more crystal orientation.

Abstract: The present application discloses a semiconductor device with a tapering impurity region and the method for fabricating the semiconductor device with the tapering impurity region. The semiconductor device includes a substrate, a word line structure positioned in the substrate, an impurity region including an upper portion positioned adjacent to the word line structure and a lower portion positioned below the upper portion. The upper portion has a tapering cross-sectional profile.

Abstract: A deposition system that mitigates feathering in a directly deposited pattern of organic material is disclosed. Deposition systems in accordance with the present disclosure include an evaporation source, an electrically conductive shadow mask, and an electrically conductive field plate. The source imparts a negative charge on vaporized organic molecules as they are emitted toward a target substrate. The source and substrate are biased to produce an electric field having field lines that extend normally between them. The shadow mask and field plate are located between the source and substrate and each functions as an electrostatic lens that directs the charged vapor molecules toward propagation directions aligned with the field lines as the charged vapor molecules approach and pass through them.

Abstract: An organic light-emitting display apparatus and a manufacturing method thereof have improved process stability and reliability by reducing damage to the organic light-emitting display apparatus during a manufacturing process. The organic light-emitting display apparatus includes: a substrate, a plurality of pixel electrodes, a pixel defining film, a plurality of hole control layers respectively arranged on the pixel electrodes, a plurality of emission layers respectively arranged on the hole control layers, a plurality of buffer layers respectively arranged on the emission layers, each of the buffer layers having a highest occupied molecular orbital (HOMO) energy level greater than the HOMO energy level of each of the plurality of emission layers, and an opposite electrode integrally provided over the buffer layers.

Abstract: A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

Abstract: Provided is a method of producing an electronic device, including a step of preparing a structure which includes an electronic component having a circuit forming surface, and an adhesive laminated film which includes a base material layer, an unevenness-absorptive resin layer, and an adhesive resin layer in this order and in which the adhesive resin layer is attached to the circuit forming surface of the electronic component such that the circuit forming surface is protected; and a step of forming an electromagnetic wave-shielding layer on the electronic component in a state of being attached to the adhesive laminated film.

Abstract: There is provided a processing method of a wafer having a functional layer on a front surface side. The processing method includes a laser processing step of forming laser processed grooves along streets while removing the functional layer along the streets by executing irradiation with a laser beam and a cut groove forming step of forming cut grooves inside the laser processed grooves along the streets by cutting the wafer by a cutting blade. The processing method also includes a grinding step of causing the cut grooves to be exposed on a back surface side of the wafer and dividing the wafer into plural device chips by grinding the back surface side of the wafer and thinning the wafer and a processing distortion removal step of supplying a gas in a plasma state to the back surface side of the wafer and removing processing distortion.

Abstract: A display device includes a base substrate, a plurality of display elements, a first light control layer, and a second light control layer. The base substrate includes a pixel region and a peripheral region adjacent to the pixel region. The display elements are disposed on the base substrate, overlap the pixel region in a plan view, and are configured to generate a first light. The first light control layer is disposed on the display elements, and includes a transmission part configured to transmit the first light, a first light conversion part configured to convert the first light into a second light, and a second light conversion part configured to convert the first light into a third light. The second light control layer overlaps at least a portion of the first light conversion part in the plan view and is configured to convert the first light into the second light.

Abstract: In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or tapered. Each of the plurality of bumps includes a first end connected to the semiconductor die and an opposing, second end connected to the lead frame. The first end has an end surface area A1. The second end has an end surface area A2. The end surface area A1 of the first end is less than the end surface area A2 of the second end. Other aspects are disclosed.

Abstract: A display apparatus is provided. The display apparatus includes a plurality of anode pads disposed on a substrate and spaced apart from each other along a first direction; a cathode pad disposed on the substrate and spaced apart from the plurality of anode pads along a second direction that crosses the first direction; a plurality of repair anode pads disposed on the substrate, spaced apart from each other along the first direction, and spaced apart from the plurality of anode pads and the cathode pad along the second direction; and a plurality of light emitting diodes (LEDs) disposed on the substrate and spaced apart from each other along the first direction, each of the plurality of LEDs including an anode that is electrically connected to a corresponding anode pad from among the plurality of anode pads and a cathode that is electrically connected to the cathode pad.

Abstract: A semiconductor device includes one or more fins extending from a substrate, the one or more fins having source/drain epitaxial grown material (S/D epitaxy) thereon that merges one or more fins, a gate formed over the one or more fins, the gate including high k metal gate disposed between gate spacers and a metal liner over the S/D epitaxy and sides of the gate spacers. The gate includes a self-aligned contact cap over the HKMG and the metal liner.

Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to ammonia vapor in a non-plasma process. Process parameters including exposure time, substrate temperature, and chamber pressure can be used to tune the inhibition profile. Also provided are methods of filling multiple adjacent lines with reduced or no line bending. The methods involve selectively inhibiting the tungsten nucleation to reduce sidewall growth during feature fill.

Abstract: A wafer has on one side a device area with a plurality of devices, partitioned by a plurality of division lines, and a peripheral marginal area formed around the device area. The device area is formed with a plurality of protrusions protruding from a plane surface of the wafer. The wafer is processed by providing a protective film, having a cushioning layer applied to a front surface thereof, attaching a front surface of the protective film, for covering the devices, wherein the protective film is adhered to at least the peripheral marginal area with an adhesive, and attaching a back surface of the protective film opposite to the front surface thereof to the cushioning layer. The protrusions are embedded in the cushioning. The side of the wafer opposite to the one side is ground for adjusting the wafer thickness.

Abstract: A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

Abstract: A method utilized at a sintered metal layer bonding a semiconductor element and a support substrate together suppresses cracks appearing in the sintered metal layer, and damage to the semiconductor element. A semiconductor device includes a support substrate, a semiconductor element, and a sintered metal layer bonding the support substrate and the semiconductor element. The sintered metal layer has a low porosity region disposed inward of an outer edge of the semiconductor element with the sintered metal layer bonded to the semiconductor element. The region is lower in porosity than the remaining sintered metal layer, and is formed as a wall-shaped structural body having an elongated string and extending from an upper surface to a lower surface of the sintered metal layer. The low porosity region is disposed to surround a region immediately below a center of the semiconductor element along the outer edge of the semiconductor element.

Abstract: A die-bonding method and a spraying device for an LED include: providing a substrate provided with a pad and a white oil layer covering wiring, placing a steel mesh on the substrate, and then spraying suspension containing solder paste on the pad by the spraying device, to form a solder paste film layer. Finally, a reflow process for the solder is performed. The solder paste is prepared on the pad by spraying, so that a crystal wafer is prevented from being tilted or short-circuited due to pulling or dragging of the solder paste during the reflow process for the solder, thereby improving uneven brightness of the surface light source.

Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.

Abstract: A display panel including a substrate, a buffer insulating layer, a plurality of pads, and a plurality of light emitting diodes is provided. The substrate has a display area and a peripheral area adjacent to the display area. The buffer insulating layer is disposed on the substrate. The Young's modulus of the buffer insulating layer is less than 10 GPa. The pads are located on the buffer insulating layer and disposed on the display area of the substrate. The light emitting diodes are electrically connected to the pads and bonding to the display area of the substrate by the pads. The buffer insulating layer is located between the light emitting diodes and the substrate. A normal projection of the light emitting diodes on the substrate is at least partially overlapped with a normal projection of the buffer insulating layer on the substrate.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure including a plurality of first conductive features adjacent to a top surface of the first semiconductor structure, a second semiconductor structure positioned above the first semiconductor structure and including a plurality of second conductive features adjacent to a bottom surface of the second semiconductor structure, and a connection structure positioned between the first semiconductor structure and the second semiconductor structure. The connection structure includes a connection layer electrically coupled to the plurality of first conductive features and the plurality of second conductive features, and a plurality of first porous interlayers positioned between the plurality of first conductive features and the plurality of second conductive features.

Abstract: A cutting method includes: forming a reformed region in a workpiece; and after forming the reformed region in the workpiece, forming a groove in the workpiece along an intended cut line. In the forming a groove, a first dry etching process is performed from a front surface toward a rear surface of the workpiece. After the first dry etching process, a first pressure-reducing process is performed in which the workpiece is placed under an atmosphere of reduced pressure as compared to pressure during the first dry etching process. After the first pressure-reducing process, a second dry etching process is performed from the front surface toward the rear surface of the workpiece.