Abstract: A semiconductor device manufacturing method includes a preparation step and a sinter bonding step. In the preparation step, a sinter-bonding work having a multilayer structure including a substrate, semiconductor chips, and sinter-bonding material layers is prepared. The semiconductor chips are disposed on, and will bond to, one side of the substrate. Each sinter-bonding material layer contains sinterable particles and is disposed between each semiconductor chip and the substrate. In the sinter bonding step, a cushioning sheet having a thickness of 5 to 5000 ?m and a tensile elastic modulus of 2 to 150 MPa is placed on the sinter-bonding work, the resulting stack is held between a pair of pressing faces, and, in this state, the sinter-bonding work between the pressing faces undergoes a heating process while being pressurized in its lamination direction, to form a sintered layer from each sinter-bonding material layer.

Abstract: A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.

Abstract: A technique regarding film formation capable of forming a three-dimensional pattern successfully is provided. A film forming method for a processing target object is provided. The processing target object has a supporting base body and a processing target layer. The processing target layer is provided on a main surface of the supporting base body and includes protrusion regions. Each protrusion region is extended upwards from the main surface, and an end surface of each protrusion region is exposed when viewed from above the main surface. The film forming method includes a first process of forming a film on the end surface of each protrusion region; and a second process of selectively exposing one or more end surfaces by anisotropically etching the film formed through the first process.

Abstract: An FDSOI device and fabrication method are disclosed. The device comprises: a buried oxide layer disposed on the silicon substrate; a SiGe channel disposed on the buried oxide layer, a nitrogen passivation layer disposed on the SiGe channel layer; a metal gate disposed on the nitrogen passivation layer, and sidewalls attached to sides of the metal gate; and a source and a drain regions disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

Abstract: A semiconductor manufacturing apparatus includes a thrust-up unit having a plurality of blocks in contact with a dicing tape, a head having a collet absorbing the die and capable of being moved up and down, and a control section controlling the operation of the thrust-up unit and the head. The thrust-up unit can operate each of the plurality of blocks independently. The control section configures the thrust-up sequences of the plurality of blocks in a plurality of steps, and controls the operation of the plurality of blocks on the basis of a time chart recipe capable of setting the height and the speed of the plurality of blocks for each block and in each step.

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

Abstract: Body-contacted semiconductor structures and methods of forming a body-contacted semiconductor structure. A semiconductor substrate, which contains of a single-crystal semiconductor material, includes a device region and a plurality of body contact regions each comprised of the single-crystal semiconductor material. A polycrystalline layer and polycrystalline regions are formed in the semiconductor substrate. The polycrystalline regions are positioned between the polycrystalline layer and the device region, and the polycrystalline regions have a laterally-spaced arrangement with a gap between each adjacent pair of the polycrystalline regions. One of the plurality of body contact regions is arranged in the gap between each adjacent pair of the polycrystalline regions.

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first nanosheet field effect transistor (NSFET). The first NSFET includes a first nanosheet channel structure arranged over a substrate, a second nanosheet channel structure arranged directly over the first nanosheet channel structure, and a first gate electrode structure. The first and second nanosheet channel structures extend in parallel between first and second source/drain regions. The first gate electrode structure includes a first conductive ring and a second conductive ring that completely surround outer sidewalls of the first nanosheet channel structure and the second nanosheet channel structure, respectively, and that comprise a first material.

Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.

Abstract: Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

Abstract: The present application discloses a semiconductor device with a tapering impurity region and the method for fabricating the semiconductor device with the tapering impurity region. The semiconductor device includes a substrate, a word line structure positioned in the substrate, an impurity region including an upper portion positioned adjacent to the word line structure and a lower portion positioned below the upper portion. The upper portion has a tapering cross-sectional profile.

Abstract: A silver nano-twinned thin film structure and a method for forming the same are provided. A silver nano-twinned thin film structure, including: a substrate; an adhesive-lattice-buffer layer over the substrate; and a silver nano-twinned thin film over the adhesive-lattice-buffer layer, wherein the silver nano-twinned thin film comprises parallel-arranged twin boundaries, and a cross-section of the silver nano-twinned thin film reveals that 50% or more of all twin boundaries are parallel-arranged twin boundaries, wherein the parallel-arranged twin boundaries include ?3 and ?9 boundaries, wherein the ?3 and ?9 boundaries include 95% or more crystal orientation.

Abstract: A deposition system that mitigates feathering in a directly deposited pattern of organic material is disclosed. Deposition systems in accordance with the present disclosure include an evaporation source, an electrically conductive shadow mask, and an electrically conductive field plate. The source imparts a negative charge on vaporized organic molecules as they are emitted toward a target substrate. The source and substrate are biased to produce an electric field having field lines that extend normally between them. The shadow mask and field plate are located between the source and substrate and each functions as an electrostatic lens that directs the charged vapor molecules toward propagation directions aligned with the field lines as the charged vapor molecules approach and pass through them.

Abstract: A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

Abstract: An organic light-emitting display apparatus and a manufacturing method thereof have improved process stability and reliability by reducing damage to the organic light-emitting display apparatus during a manufacturing process. The organic light-emitting display apparatus includes: a substrate, a plurality of pixel electrodes, a pixel defining film, a plurality of hole control layers respectively arranged on the pixel electrodes, a plurality of emission layers respectively arranged on the hole control layers, a plurality of buffer layers respectively arranged on the emission layers, each of the buffer layers having a highest occupied molecular orbital (HOMO) energy level greater than the HOMO energy level of each of the plurality of emission layers, and an opposite electrode integrally provided over the buffer layers.

Abstract: Provided is a method of producing an electronic device, including a step of preparing a structure which includes an electronic component having a circuit forming surface, and an adhesive laminated film which includes a base material layer, an unevenness-absorptive resin layer, and an adhesive resin layer in this order and in which the adhesive resin layer is attached to the circuit forming surface of the electronic component such that the circuit forming surface is protected; and a step of forming an electromagnetic wave-shielding layer on the electronic component in a state of being attached to the adhesive laminated film.

Abstract: There is provided a processing method of a wafer having a functional layer on a front surface side. The processing method includes a laser processing step of forming laser processed grooves along streets while removing the functional layer along the streets by executing irradiation with a laser beam and a cut groove forming step of forming cut grooves inside the laser processed grooves along the streets by cutting the wafer by a cutting blade. The processing method also includes a grinding step of causing the cut grooves to be exposed on a back surface side of the wafer and dividing the wafer into plural device chips by grinding the back surface side of the wafer and thinning the wafer and a processing distortion removal step of supplying a gas in a plasma state to the back surface side of the wafer and removing processing distortion.

Abstract: A display device includes a base substrate, a plurality of display elements, a first light control layer, and a second light control layer. The base substrate includes a pixel region and a peripheral region adjacent to the pixel region. The display elements are disposed on the base substrate, overlap the pixel region in a plan view, and are configured to generate a first light. The first light control layer is disposed on the display elements, and includes a transmission part configured to transmit the first light, a first light conversion part configured to convert the first light into a second light, and a second light conversion part configured to convert the first light into a third light. The second light control layer overlaps at least a portion of the first light conversion part in the plan view and is configured to convert the first light into the second light.

Abstract: In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or tapered. Each of the plurality of bumps includes a first end connected to the semiconductor die and an opposing, second end connected to the lead frame. The first end has an end surface area A1. The second end has an end surface area A2. The end surface area A1 of the first end is less than the end surface area A2 of the second end. Other aspects are disclosed.