Abstract: An input circuit for a charge-coupled device (CCD) delay line is comprised of a semiconductor substrate, a CCD delay line formed on the semiconductor substrate, first and second registers each having substantially the same maximum treating charge amount as that of the CCD delay line and formed on the semiconductor substrate, an input portion of the first register having substantially the same structure as that of the CCD delay line, output portions of the first and second registers having substantially the same structure each other, a control circuit for controlling the second register so that an output signal from the second register becomes a signal corresponding to the maximum treating charge amount, a comparing circuit for comparing output signals of the first and second registers, wherein an output signal of the comparing circuit is fed back to an input source of the input portion of the first register so that the output signal from the first register becomes equal to the output signal from the second re

Abstract: An improved liquid crystal device is described. The distance between a pair of substrates is kept constant by means of spacers interposed therebetween. The material, the size and the distribution density of the spacers are chosen in order that the distance between the mated substrates just before the liquid crystal is disposed in the formation of the liquid crystal device is 0.77-0.87 of that after the disposing.

Abstract: A timing adjusting circuit for single line serial data includes a synchronous data sampling circuit for sampling data input from the exterior synchronously with a reference clock pulse, a data edge detection circuit for outputting data edge detection signals, and a synchronous pulse generation circuit for generating repetitive pulses synchronized with output from the data edge detection circuit.

Abstract: An integrated circuit that is useful as a buffer is disclosed. The integrated circuit has an input voltage shifter circuit for shifting an input voltage and an output voltage shifter circuit for shifting an output voltage. It has a first comparator circuit for comparing the input voltage to the output voltage and a second comparator circuit for comparing the shifted input voltage to the shifted output voltage. The first comparator circuit produces a first control signal and the second comparator circuit produces a second control signal. A voltage driver circuit receives the control signals and produces the output voltage. A capacitor to compensate the output voltage can be connected to the output voltage before it is applied to the first comparator circuit and to the output voltage shifter circuit.

Abstract: A start circuit for a bandgap reference cell using CMOS transistors including a transistor connected between the bandgap reference cell and a differential amplifier in the feedback path to create an offset voltage in the bandgap reference cell when power is first applied, which offset insures the correct operation of the bandgap reference cell, and to turn off after correct operation has been achieved.

Abstract: The delay period of a delay circuit is maintained, over time, near to a desired delay, by generating information representative of the present delay period of the delay circuit, and altering the delay period, from time to time during operation, based on the present delay information and the desired delay. The present delay is measured by a reference circuit having a delay characteristic corresponding to the delay characteristic of the delay circuit. Both the reference and multiple delay circuits are formed with the same configuration on a single integrated circuit.

Abstract: A Costas loop carrier wave reproducing circuit includes a first differential amplifier circuit, a second differential amplifier circuit, a multiplying circuit, a first square circuit, a second circuit, and a double-balanced differential amplifier circuit. The first differential amplifier circuit obtains an inphase output from an inphase demodulated signal obtained by performing synchronous detection of a component inphase with a four-phase modulated wave. The second differential amplifier circuit obtains an orthogonal output from an orthogonal demodulated signal obtained by performing synchronous detection of an orthogonal component of the four-phase modulated wave. The multiplying circuit multiplies outputs from the first and second differential amplifier circuits. The first square circuit obtains a square output of an output from the first differential amplifier circuit. The second square circuit obtains a square output of an output from the second differential amplifier circuit.

Abstract: A monostable multivibrator comprises an input circuit receiving an trigger signal for generating an instantaneous pulse, a timing generation circuit receiving the instantaneous pulse for generating a timing defining signal after a predetermined time, and an output circuit for generating a output pulse starting in response to the instantaneous pulse and terminating at the timing defining signal.

Abstract: A liquid crystal light valve cell has two optically different states switchable therebetween by a bias voltage in response to incident light. A ferroelectric liquid crystal layer is sandwiched by a pair of front and rear alignment layers to establish the two bistable states in the ferroelectric liquid crystal layer. A front electrode layer is disposed on the front alignment layer. An optically reflecting layer is disposed on the rear alignment layer. A photo-conductive layer is disposed on the reflecting layer and responsive to the incident light incident from the rear face of cell to increase its electroconductivity.

Abstract: An input structure of CCD comprises a primary register having an input gate and a source region and an automatic biasing system which generates a feedback signal to be fed back to input of the primary register. The output of the automatic biasing system is connected to one of the input gate and the source of the primary register for supplying the feedback signal thereto for adjusting input bias level of the primary register. The other one of the input gate and the source is connected to an information signal input terminal to receive therefrom an information signal to be transferred therethrough.

Abstract: A bidirectional level shifting interface circuit has first and second I/O ports and an FET with a drain-source channel connected between the first and second I/O ports. The first I/O port is connected to an I/O port of a first digital circuit operating at a relatively low supply voltage, and the second I/O port is connected to an I/O port of a second digital circuit operating at a relatively high supply voltage. This channel passes communication signals in each direction between the first and second digital circuit. A latching circuit comprising a P Channel FET is biased by the relatively high voltage supply, has an output connected to the second I/O port, and has a control input.

Abstract: A circuit capable of being integrated into a self-isolated DMOST is driven by a sense resistor that is created from the DMOST drain metallization. The circuit produces an output current that is ratioed with respect to the DMOST current with the ratio being determined by the value of a single resistor. The output current is sourced when the DMOST conducts its source current and the output current is sunk when the DMOST shunt diode conducts. Thus, the circuit not only produces a DMOST current related output it also distinguishes the mode of DMOST conduction.

Abstract: An improved light addressed liquid crystal light valve incorporating electrically insulating light blocking material is disclosed. The light valve has a hydrogenated amorphous silicon photosensitive layer and a germanium containing or tin containing alloy film as a light blocking layer. The light blocking layer that may be used is a selected alloy which includes one or more elements from the group consisting of germanium and tin, one or more elements from the group consisting of hydrogen, nitrogen and oxygen, and zero or more elements from the group consisting of silicon and carbon. The light blocking layer has an optical density per unit thickness approximately equal to or greater than 3 OD/micron for visible light and a sheet resistivity approximately equal to or greater than 10.sup.10 ohms/square.

Abstract: A preamplifier interfaces low level current-mode signals, such as from a photodetector in a computerized tomography system, to a corresponding voltage-mode signals, with a dynamic range on the order of 120 dB. The preamplifier can be implemented in CMOS technology to allow for complete integration of the computerized tomography interface function, including analog-to-digital conversion, of several channels in a single integrated circuit. The CMOS circuit accepts a current signal at its input and, after integration of the signal, produces a voltage output wherein the low frequency noise that is normally encountered with MOS transistors is cancelled through the use of correlated-double sampling. The circuit limits high frequency noise through use of low-pass filtering.

Abstract: Disclosed is a color liquid crystal display device having a plurality of pixels, in which conductive films are arranged at regions corresponding to the respective pixels, a light-shielding conductive layer is connected to the conductive films and extends in a region between the pixels, and color filters are formed on the conductive films.

Abstract: A liquid crystal device including a ferroelectric liquid crystal disposed between plates treated to enforce a particular ferroelectric molecular orientation to the plates. The devices employ alone or in combination non-planar boundary conditions, polar boundary conditions, boundaries with multiple physical states, intrinic spontaneous splay distortion of the polarization orientation field, combined ferroelectric and dielectric torques, layers tilted with respect to the plates. The plates are spaced by a distance sufficiently small to ensure unwinding of the helix typical in a bulk of the material to form either monostable, bistable or multistable states which exhibit novel electro-optic properties. The liquid crystal is responsive to an externally applied electric field, temperature or the like to make a light valve or other electro-optical device.

Abstract: A first reference signal whose components have the same amplitude and are symmetrical is supplied to the bases of a first and second transistors, the collectors of which are each connected to a power supply. A first resistor is connected between the emitters of the first and second transistors. A first constant current source is connected to the emitter of the first transistor. A second reference signal of a constant amplitude is supplied to the bases of a third and fourth transistors, the collectors of which are each connected to a power supply. A second resistor different in resistance from the first resistor is connected between the emitters of the third and fourth transistors. A second constant current source is connected to both the emitters of the second and third transistors, while a fourth constant current source is connected to the emitter of the fourth transistor. These first, seocnd, and third constant current sources produce the same current.

Abstract: In direct digital synthesizers in the prior art, the output signal maintains a phase continuity whenever it switches, or hops, frequency. This phase continuity shows up as a smooth change in phase from one frequency to the next; the phase of the last frequency transitions into the phase of the new frequency without any discernable disruption. Thus, whenever the output signal returns to a switched frequency that it previously has, the output signal at the newly returned switched frequency has a new phase relative to its previous one at that frequency. For some applications, like simulating continuous different frequency sources, this phase continuity is not desirable. To overcome this disadvantage, the preferred embodiment of the present invention provides phase memory to a direct digital synthesizer so that regardless of the frequency that the output signal switches to, the output signal at that frequency is able to maintain a constant phase relative to a reference system clock pulse.

Abstract: There is disclosed a voltage control circuit for a semiconductor apparatus for controlling an output voltage to be applied from an external voltage source to a load circuit of the semiconductor apparatus therethrough. A reference voltage generator generates a predetermined reference voltage according to a source voltage outputted from an external voltage source, and an error amplifier compares the output voltage with the reference voltage, and outputs a comparison signal for representing the comparison result thereof. A voltage controller controls the output voltage according to the comparison signal. Further, a diode circuit which is connected in parallel with the voltage controller applies the source voltage to the load circuit in a forward direction thereof.

Abstract: An asynchronous circuit utilizes toggle flip-flops to receive a plurality of asynchronous input signals. The input signals are applied to the edge-triggered clock inputs of the toggle flip-flops so that outputs of the toggle flip-flops and other logic signals within the asynchronous circuit change with respect to particular edges of the input signals. An output signal is responsive to the changes in the outputs of the toggle flip-flops and is thus responsive to the changes in the asynchronous input signals. Since the input signals have well-defined transitions which cause the changes in the output signals, various parameters, such as propagation delays, can be measured and characterized. The asynchronous logic circuit thus provides the operational advantages of asynchronous circuits while exhibiting the testability characteristics of clocked logic circuits.