Abstract: A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.

Abstract: A multiplier comprises first and second squaring circuits each including first and second MOS transistors having their sources connected in common and third and fourth MOS transistors having their sources connected in common. The first and third transistors have a first gate W/L ratio and have their drains connected to each other, and the second and fourth transistors have their drains connected to each other and have a second gate W/L ratio different from the first ratio. Gates of the first and fourth transistors are connected to each other, and gates of the second and third transistors are connected to each other. A first input signal is supplied to the gates of the first and fourth transistors of each of the first and second squaring circuits, and a second input signal is supplied, without being inverted, to the gates of the second and third transistors of the first squaring circuit, and without being inverted, to the gates of the second and third transistors of the second squaring circuit.

Abstract: A liquid crystal color display provides a transmitted light output that is of one or more colors, black, and/or white, as a function of the color of the incident light input and controlled energization or not of respective optically serially positioned liquid crystal color layers and/or multicolor composite liquid crystal color layer(s) in the display. In one case, the display includes a plurality of liquid crystal color layers, each being dyed a different respective color, and apparatus for selectively applying a prescribed input, such as an electric field of a given voltage level or frequency, to a respective layer or layers or to a portion or portions thereof. Each liquid crystal layer includes plural volumes of operationally nematic liquid crystal material in a containment medium that tends to cause an alignment of the liquid crystal structure and, thus, pleochroic dye included or mixed with the liquid crystal material in each layer to absorb light.

Abstract: A method of conserving the battery power supply of a liquid crystal display including a ferroelectric liquid crystal layer having a bistability characteristic, and an electrode arrangement corresponding to an m x n matrix of picture elements where all the picture elements are elements of a display picture to be displayed by the display where first electric fields are applied from the electrode arrangement for a first period of time to the ferroelectric liquid crystal layer to display a first display picture. The first electric fields are then removed for a second period of time greater than the first period of time whereby the first display picture continues to be displayed due to the bistability characteristic of the ferroelectric liquid crystal layer; and then second electric fields are applied to the ferroelectric liquid crystal display to change the picture displayed by the display from the first display picture to a second display picture.

Abstract: An output circuit portion of a BiCMOS logic circuit adapted to operating on a low voltage has an npn transistor Q5 connected between the power source Vcc and an output N6, and has an npn transistor Q6 connected between the output N6 and ground potential GND. The base of the npn transistor Q5 is driven by the drain output of p-channel MOSFETs MP3, MP4, and the base of the npn transistor Q6 is driven by the drain output of p-channel MOSFET QP5. When the power source voltage Vcc drops, the voltage applied between the drain and the source of MOSFET MP5 becomes small by the effect of V.sub.BE of the transistor Q6, but the drain current of the MOSFET MP5 changes little. Therefore, the BiCMOS circuit operates at high speeds (see FIG. 1) even when the power source voltage drops.

Abstract: A gate biasing circuit including a Schottky barrier diode in series with an ion implanted resistor for use with a baseband MMIC control components such as an MESFET. The diode gate biasing scheme improves the low frequency distortion characteristics of GaAs MESFET control components significantly, allowing microwave power handling and distortion characteristics to be maintained below 100 Hz.

Abstract: A master/slave flipflop comprises a master flipflop including a first inverter having an input for receiving an input signal, and a second inverter having an input connected to an output of the first inverter, and a first switch means connected between an output of the second inverter and the input of the first inventer. A slave flipflop of the master/slave flipflop includes a third inverter having an input for receiving an output signal of the master flipflop, and a fourth inverter having an input connected to an output of the third inverter, and a second switch means connected between an output of the fourth inverter and the input of the third inverter. A third switch is connected between the output of the second inverter and the input of the third inverter, and a fourth switch is connected between the output of the first inverter and the input of the third inverter.

Abstract: A delay circuit includes an output voltage controllable BICMOS delay element that is coupled to a phase locked loop that develops a control voltage. The control voltage is applied to the output BICMOS delay element and to another BICMOS delay element in the phase locked loop. An input voltage is applied to the phase locked loop and, along with the output of the phase locked loop, to the output BICMOS delay element.

Abstract: An integrated binary amplifier connected to a bus such as a precharged bus and having a field effect transistor receiving an input signal and coupled to series-connected bipolar transistors including an output transistor. The base of the output transistor is connected to a fixed potential by a field effect transistor of which the type and the control means assure its conduction when the bipolar transistors are conductive. The output signal thus has its low level to ground.

Abstract: A liquid crystal display cell comprising a pair of flexible polymer film substrates having a transparent electrode disposed on the surface thereof and a liquid crystal material sandwiched therebetween. The transparent electrode is a metal oxide film which has a surface resistivity of not greater than 100 ohm per square, a bending property of not greater than 2.0, a curling degree, H, of 0<H<5 mm and a transmittance to light of 550 nm of not less than 75%. Further, this metal oxide is substantially amorphous, and is formed by a DC sputtering method.

Abstract: A liquid crystal display apparatus in which leakage of light caused by signal lines can be eliminated is disclosed. In the liquid crystal display apparatus, a predetermined potential corresponding to the black level is applied to the video signal lines during a period of time other than the horizontal blanking period, and image signals are transferred to one row of the pixels through the signal lines which the horizontal blanking period.

Abstract: An evaluating circuit for evaluating square wave signals is provided. A plurality of square wave signals are transmitted to a memory which has a number of bistable toggle stages which correspond to the number of square wave signals. The toggle stages are driven by an auxiliary clock signal. An up-down counter is also driven by the auxiliary clock. The circuit further includes a comparator which compares the square wave signals and the state of the up-down counter and generates a control signal over at least one control line to the up-down counter in response to the comparison. The state of the up-down counter is changed in an up or down direction or not changed in response to the control signal.

Abstract: A power-on reset circuit including a constant voltage circuit element in which a voltage drop is limited to within a fixed value, a transistor to which a source voltage is applied from the constant voltage circuit element and a gate voltage is applied from a power source voltage to be monitored, a current path forming element, connected to the drain of the transistor, fed with current from a power source voltage, and an invertor an input terminal of which is connected to a node of the current path forming element and the transistor.

Abstract: A liquid crystal apparatus, such as a display, film, or other material or device, includes liquid crystal material in a containment medium which are cooperative selectively to scatter or to transmit light. Fluorescent dye colors, brightens and/or whitens the scattered light and may effect a light amplification function.

Abstract: A liquid crystal display device includes a liquid crystal display panel for displaying picture elements in accordance with a predetermined voltage applied thereto. In the liquid crystal display device, a light shutter is arranged between the liquid crystal display panel and a light source, and the light shutter shades the light incident to the picture elements being rewritten from the light source.

Abstract: A variable width pulse generator includes a plurality of logic stages which are coupled cascade. Each stage is arranged to select one of a plurality of clock signals of differing phase applied thereto responsive to particular bits of a data word defining the pulse width. All of the stages are initially disabled by a precharge pulse occurring at the beginning of each variable pulse interval. The successive stages are enabled by the occurrence of a clock pulse of a clock signal selected by the previous stage. The lastmost stage provides an output corresponding to the width pulse.

Abstract: A matrix-type liquid-crystal display panel, in which thin-film transistors are used as address display elements, comprises an electroconductive film that is formed on at least one wiring pattern connected to an electrode of the thin-film transistor, the width of the electroconductive film being greater than that of the wiring pattern.

Abstract: A driving circuit for providing a predetermined voltage as a driving signal to a respective word line in a dynamic random access memory in a short time. The driving circuit includes an operation signal supply circuit portion for providing an operation signal, a driving signal output circuit portion which receives the operation signal and provides a driving signal as an output, and a voltage supply circuit portion for providing a predetermined voltage to the driving signal output circuit portion in producing the driving signal. A bipolar switching element is provided in the driving signal output circuit portion to control the voltage supply from the voltage supply circuit portion and responds to the operation signal to provide the voltage from the voltage supply circuit portion as the voltage producing the driving signal in a short time.

Abstract: An anti-noise circuit dissipates parasitic tank circuit energy which causes ground unershoot and V.sub.cc overshoot in the power rails (PG,PV) of an integrated circuit device. An anti-noise circuit transistor element, either an anti-undershoot circuit transistor element (AUCT) or an anti-overshoot circuit transistor element (AOCT) incorporates selected resistance in its primary current path for providing dissipating resistance. The anti-noise circuit couples a current source (PV), the anti-noise circuit transistor element (AUCT, AOCT) with dissipating resistance, and power rail parasitic lead inductance in series in a sacrificial current path. A control circuit coupled to the control node of the anti-noise circuit transistor element (AUCT,AOCT) causes sacrificial current flow following switching of potential levels at the output for dissipating parasitic tank circuit energy. The control circuit incorporates an active pullup and pulldown passgate (RST1,ICT1,OCT1) (RST2,ICT3, OCT2) between the data input (V.

Abstract: An active matrix liquid crystal display element comprises an active matrix substrate having an active element for each electrode for picture element, a counter electrode substrate provided with a counter electrode and a liquid crystal polymer composite material in which a nematic liquid crystal having a positive dielectric anisotropy is dispersed and held in a polymer matrix, said liquid crystal polymer composite material being held between the active matrix substrate and a counter electrode substrate, and the refractive index of the polymer matrix substantially agreeing with the ordinary refractive index (n.sub.0) of the liquid crystal used, wherein the refractive index anisotropy .DELTA.n of the nematic liquid crystal used is 0.18 or higher, and the average particle diameter R(.mu.m) of the liquid crystal dispersed and held in the polymer matrix, and the specific dielectric anisotropy .DELTA..epsilon., the elastic constant K33(10.sup.