Abstract: A data handoff controller includes a counter coupled to supply a count value indicative of a skew between a first clock signal and a second clock signal. The first and second clock signal have a fundamental beat frequency. A greatest common factor circuit is used to determine the fundamental beat frequency and the second is reset based on the beat frequency. A sampling circuit samples first clock domain data with the second clock signal. The sampling circuit is controlled to sample, at least in part, based on the count value. The count value can be used to impose a blackout window in which data is not sampled to avoid sampling data around data transitions of the first clock domain data. The count value can also be used to select an edge of the second clock signal to use for sampling the first clock domain data to ensure first clock domain data is not sampled during data transitions.

Abstract: A device interoperability system for one or more user devices associated with a user, wherein said one or more user devices comprises a first user device, said device interoperability system comprising a communications module, wherein a first connection is established between said first user device and said communications module; storage associated with said device interoperability system and coupled to said communications module, wherein said storage stores an operating system, one or more programs, and data associated with the user, further wherein said operating system is booted by said first user device via said first connection; and one or more processors to support said device interoperability system.

Abstract: In this method for controlling a server cluster, the cluster Including a plurality of nodes, automated agents measure the change in at least one metric quantifying the use of the nodes for the execution of an application, the agents determine, for each node, by measuring the metric, whether a change of phase has taken place in the executed application, and cause a change of the operation of the node if necessary; at regular intervals, an automated coordinator aggregates the metric measurements and the changes of operation of the nodes that have taken place and, on the basis of the aggregated measurements, the coordinator sends instructions to at least one of the agents.

Abstract: Methods and apparatus to dynamically throttle compute engines are disclosed. A disclosed example apparatus includes one or more compute engines to perform calculations, where the one or more compute engines are to cause a total power request to be issued based on the calculations. The example apparatus also includes a power management unit to receive the total power request and respond to the total power request. The apparatus also includes a throttle manager to adjust a throttle speed of at least one of the one or more compute engines based on comparing a minimum of the power request and a granted power to a total used power of the one or more compute engines prior to the power management unit responding to the total power request.

Abstract: Technologies for efficiently booting sleds in a disaggregated architecture include a sled. The sled includes a network interface controller, a set of processors, and firmware that includes an operating system. Additionally, the sled includes circuitry to perform, with multiple processors in the set of processors, a boot process. The circuitry is also to initialize the operating system present in the firmware, receive, with the network interface controller and from another sled, an assignment of a workload, and execute the assigned workload with the operating system.

Abstract: Systems and methods are disclosed method for controlling instantaneous current changes in parallel processors with arrays of parallel computing elements, such as neural processors. An exemplary method comprises monitoring the array of computing elements and determining a transition from a first activity level of the array to a second activity level of the array, such as an idle-to-active or active-to-idle transition. Once a transition is determined, the array is selectively controlled to minimize the instantaneous current change from the transition from the first activity level to the second activity level.

Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.

Abstract: A system may include a field-programmable gate array (FPGA). The FPGA may be configured to: determine a time corresponding to in which of x time periods a signal arrived at an input serializer based at least on a value; and determine a time when the signal arrived at an input pad based at least on a shift register latency value and the time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value.

Abstract: A method operates a first-in-first-out (FIFO) buffer with a first clock, and operates one of a read pointer or a write pointer of the FIFO buffer with the first clock while operating the other one of the read pointer or write pointer with a second clock. One of a serializer fed from the FIFO buffer output, or a de-serializer feeding the FIFO buffer input, is operated with the second clock. Timing pulses indicate that the pointer operating with the second clock has reached a predetermined point in its cycle. The phase of the second clock is adjusted based on a relationship between the timing pulses and an advance period of the pointer operating with the first clock. The pointer operating with the first clock is reset to achieve a desired value for the relationship. A skew created from adjusting the phase of the second clock is corrected.

Abstract: An information handling system includes a BIOS ROM that stores a first firmware volume of BIOS code. A non-volatile memory device includes a first boot partition that stores a second firmware volume of the BIOS code. A processor executes the first and second firmware volumes during a Pre-EFI Initialization phase of a Unified Extensible Firmware Interface boot process.

Abstract: A power management system including a first circuit board, a second circuit board and a connection cable is provided. The connection cable is compatible with USB type-C specification and connects the first circuit board and the second circuit board. When the first circuit board determines that a first power state of the first circuit board changes, the first circuit board transmits the first signal to the second circuit board through a configuration channel (CC) terminal of the connection cable, the second circuit board changes a second power state of the second circuit board according to the first signal.

Abstract: An access point, which is a Power over Ethernet (PoE) Powered Device (PD) measures input voltage and input current. The access point determines a power requirement of the access point based on the measured current, measured voltage, and information about power requirements of access point components or devices coupled to the access point a power requirement of the access point. The access point communicates the determined power request to a power sourcing equipment (PSE), e.g., a network switch. In some embodiments, the access point further communicates one of: measured input current and measured input voltage to the PSE. The PSE uses the information received from the access point, e.g., power request and power measurements to determine an amount of power to be granted to the access point. If the access point does not receive the requested power level the access point selects internal components and/or external devices to de-power.

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

Abstract: A BIOS setting modification system is provided in a computing device. During a computing device runtime for the computing device, an Out-Of-Band (OOB) controller device receives a first BIOS setting modification request and, in response, generates first BIOS setting modification information and causes the transmission of a System Management Interrupt (SMI). During the computing device runtime for the computing device, an SMI handler subsystem in the computing device retrieves, in response to the SMI, the first BIOS setting modification information, either directly from the OOB controller device, or from a storage subsystem in which it was provided by the OOB controller device. The SMI handler subsystem then applies the first BIOS setting modification information to at least one subsystem in the computing device such that a first BIOS setting modification provided by the first BIOS setting modification information takes effect during the computing device runtime for the computing device.

Abstract: A power control method applicable to an electronic apparatus having a first electronic element and a second electronic element which can be opened and closed toward to each other. The power control method includes the following steps: providing a plurality of power modes on the electronic apparatus; detecting a trigger signal generated from a close operation of the first electronic element and the second electronic element; detecting touch information generated in response to the first electronic element or the second electronic element being touched; determining a close gesture according to the trigger signal and the touch information; and selecting and operating in a corresponding power mode within the plurality of power modes by the electronic device according to a correspondence relationship of the close gesture and the plurality of power modes.

Abstract: The disclosed computer-implemented method may include (i) identifying an artificial neural network that processes each input to the artificial neural network in a fixed number of operations, (ii) performing an analysis on the artificial neural network to determine an execution metric that represents the fixed number of operations performed by the artificial neural network to process each input, (iii) determining a quality-of-service metric for an executing system that executes the artificial neural network, and (iv) optimizing power consumption of the executing system by configuring, based on the execution metric and the quality-of-service metric, a processing throughput of at least one physical processor of the executing system, thereby causing the executing system to execute the artificial neural network at a rate that satisfies the quality-of-service metric while limiting the power consumption of the executing system. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Techniques for configurable compute instance resets are described. A user can issue a request to securely reset one or more compute instances implemented within a service provider system. Each compute instance is reset to a previous point in time, such that any activity of the compute instance or effects thereof occurring since that point in time are completely eliminated. Each compute instance reset can include removing an existing volume of the compute instance, obtaining a volume, attaching the obtained volume to the compute instance, and rebooting the compute instance. Configuration data of the compute instance, such as an instance identifier or network addresses, can be maintained after the reset.

Abstract: A BIOS platform configuration system includes a BIOS coupled to hardware subsystems. During initialization operations, the BIOS communicates with each of the hardware subsystems and retrieves respective hardware subsystem information that is associated with each of the hardware subsystems and that describes at least a portion of a communication route between that hardware subsystem and at least one other hardware subsystem. The BIOS then combines the respective hardware subsystem information that is associated with each of the hardware subsystems to generate configuration information that describes complete communication routes between each of the hardware subsystems, and configures at least one of the hardware subsystems using the configuration information.

Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.