Abstract: This document describes systems and techniques for a hardware-based save-and-restore controller in an SoC. The described systems and techniques can automatically save and restore access control configurations (e.g., register states) of IP subsystems during a power-down and a power-up sequence, respectively. The save operation is initiated by a local save-and-restore (L SAR) controller and performed by the IP subsystems writing the configuration values to a central save-and-restore (C-SAR) controller before powering down a power domain. The C-SAR controller saves the configuration information in a memory located in an always-on power domain. The described systems and techniques initiate, via the L SAR controller, a restore operation as part of the power-up sequence. In this way, the described systems and techniques provide scalable save-and-restore services, support a large number of power domains, and allow a variable number of access control configurations to be saved and restored.

Abstract: An electronic device includes a first circuit block and a second circuit block. The first circuit block is allocated in a first power domain, and includes a first clock counter and an updating circuit. The first clock counter is arranged to generate a first counter value according to a first reference clock. The updating circuit is arranged to receive a second counter value, and update the first counter value according to the second counter value. The second circuit block is allocated in a second power domain, and includes a second clock counter arranged to generate the second counter value according to a second reference clock. The first power domain and the second power domain are controlled independently.

Abstract: Provided are a cloud computing power allocation method, a user terminal, a cloud computing power platform, and a system. The method includes: generating a computing power request including a computing power demand and account information of a computing power scheduling center; sending the computing power request to a cloud computing power platform, so that the cloud computing power platform sends a configuration instruction to a computing device cluster according to the computing power request, where the configuration instruction is to allocate to the user terminal a target computing device meeting the computing power demand from the computing device cluster and configure based on the account information the target computing device to execute a computing task issued by the computing power scheduling center; and acquiring from the computing power scheduling center computing power information determined according to a computing result from the target computing device, by using the account information.

Abstract: Implementations of the present disclosure disclose a memory system and an operation method thereof. The memory system comprises at least one memory device and a memory controller coupled with the at least one memory device. The memory controller is configured to: in respond to an instruction of a host coupled with the memory system, control the memory system to enter a first activation mode and a transition mode sequentially. The transition mode includes an idle mode and a first sleep mode. A power of the memory system in the first sleep mode is less than a power of the memory system in the idle mode. The power of the memory system in the idle mode is less than a power of the memory system in the first activation mode.

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

Abstract: Various examples are directed to a System on a Chip (SOC) and methods of operating the same. The SOC may access firmware code from a boot Read-Only Memory (ROM) of the SOC. The firmware code may comprise a plurality of functional blocks. The SOC may determine that firmware patching is active for the SOC and access patch data from a non-volatile memory of the SOC. The SOC may determine that a first functional block of the firmware code has been patched and access first patch code from the patch data. The first patch code may be associated with the first functional block. The SOC may execute the first patch code.

Abstract: Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.

Abstract: A power consumption control device applied to an electronic device includes an image signal processor (ISP), a storage device, a processing circuit, and a control circuit. The ISP is arranged to receive an image signal captured by a camera of the electronic device, and process the image signal to generate a processed image signal. The storage device is arranged to store at least one predetermined image class. The processing circuit is arranged to analyze the processed image signal to detect whether the processed image signal belongs to the at least one predetermined image class to generate a control signal. The control circuit is arranged to switch a mode of the electronic device to a first mode or a second mode according to the control signal, wherein power consumption and performance of the electronic device in the first mode are lower than that in the second mode.

Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

Abstract: Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.

Abstract: A power supply control method, system and device for a server are provided. The method includes: dividing a utilization rate of a system main power supply into different levels in advance, and setting a GPU power control policy corresponding to a respective one of the different levels of the utilization rate of the system main power supply, wherein a suppression degree, on a computing capability of GPUs in a system, of the set GPU power control policy increases with the increase in the level of the utilization rate of the system main power supply; acquiring an actual utilization rate of the system main power supply, and determining a target utilization rate level corresponding to the actual utilization rate; and performing power supply control on the GPUs in the system according to the GPU power control policy corresponding to the target utilization rate level.

Abstract: Provided are a chip, a series power supply circuit, a data processing device, and a computer server. The chip includes a plurality of units to be powered, the plurality of units to be powered are connected in parallel, and a voltage domain forms on each unit to be powered. Each unit to be powered is connected to a voltage regulation unit in series, and during power-on of the chip, the voltage regulation unit is regulated to control power-on time of the plurality of units to be powered.

Abstract: Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.

Abstract: A method and a system for impact detection in a stationary vehicle are provided. The method includes putting a telematics device into a sleep mode and performing a first micro wakeup. In response to determining that a first value read from a sensor during the micro wakeup is greater than a noise threshold, increasing a frequency of the micro wakeups and a sampling rate of the sensor. The method also includes reading a second value from the sensor during a second wakeup, performing a regular wakeup, and sending the first and second values during the regular wakeup.

Abstract: An electronic device is provided. The electronic device includes a first controller, a first memory configured to store a first basic input output system (BIOS) and first firmware for controlling the first controller and functionally connected to the first controller, a second memory configured to store second firmware corresponding to the first firmware and a second BIOS corresponding to the first BIOS, and a second controller functionally connected to the first memory, the second memory, and the first controller, wherein the second controller is configured to compare the first firmware and the second firmware during power-on when the electronic device is applied with power, and turn on the first controller at least based on a result of the comparison, and wherein the first controller is configured to, in response to being turned on by the second controller, control a system of the electronic device to be booted.

Abstract: The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.

Abstract: Methods and apparatus for adaptive power profiling in a baseband processing system. In an exemplary embodiment, an apparatus includes one or more processing engines. Each processing engine performs at least one data processing function. The apparatus also includes an adaptive power profile (APP) and a job manager that receives job requests for data processing. The job manager allocates the data processing associated with the job requests to the processing engines based on the adaptive power profile. The adaptive power profile identifies a first group of the processing engines to perform the data processing associated with the job requests, and identifies remaining processing engines to be set to a low power mode.

Abstract: Systems and methods are disclosed for harvesting electrical energy from mechanical components of hard disk drives (HDDs) in a data storage system and propagating the electrical energy to devices outside of the HDDs. A power distribution board (PDB) may be coupled to a plurality of HDDs and used to detect a voltage drop on a connection between the PDB and the HDDs indicative of a power loss condition, and, in response, enable the flow of electrical energy from the HDDs to the PDB. The electrical energy from the HDDs may be converted for use by the PDB and/or distribution to other components of the data storage system.

Abstract: The described technology provides a method including reserving a portion of a volatile memory on a system on chip (SOC) including one or more processors, decompressing at least a portion of the firmware code from a non-volatile memory; programming one or more volatile memory access control registers to remove write access to the reserved portion of the volatile memory, programming a memory activation table (MAT), wherein the MAT includes a set of memory access controller register addresses and values of the memory access controller register addresses, and communicating an address of the reserved portion of the volatile memory and the MAT to a trusted execution engine (TEE) on the SOC.

Abstract: Systems and methods for managing peripheral device settings based upon context using heterogeneous computing platforms are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a heterogeneous computing platform and a memory coupled to the heterogeneous computing platform, where the memory comprises a plurality of sets of firmware instructions, where each of the sets of firmware instructions, upon execution by a respective device among a plurality of devices of the heterogeneous computing platform, enables the respective device to provide a corresponding firmware service, and where at least one of the plurality of devices operates as an orchestrator configured to: receive context or telemetry data collected by at least one of the plurality of devices; and trigger a modification of a setting for a peripheral device based, at least in part, upon the context or telemetry data.