Abstract: A reboot control system includes an information processing device and a reboot management device connected over a network. The reboot management device includes a first storage unit that stores device management information including information related to each information processing device, a reboot time setting unit that sets a reboot time, and a reboot time notification unit that transmits the set reboot time to each information processing device. The information processing device includes a reboot information acquisition unit that acquires the transmitted reboot time, and a reboot execution unit that executes a reboot at the acquired reboot time. The reboot time setting unit takes Into account a positional relationship of multiple information processing devices existing in a predetermined neighboring relationship to set the reboot times of the multiple information processing devices existing in the predetermined neighboring relationship to mutually different times.

Abstract: In some embodiments, power may be temporarily removed from a first portion of a computer system (such as a display), and that power redirected to a second portion (such as a processor or System on a Chip), so that extra performance may be obtained from the second portion without exceeding the power budget for the system. If the first portion is a display, the time period of removed power may be short enough that the absence of luminance during that time period will not be noticeable to the human vision system. In a similar embodiment, power may be delivered to the first portion using pulse width modulation, using the time between pulses to redirect power to the other portion.

Abstract: The technology described herein is related to a two-phase deployment-initiated wakeup mechanism for a body-mountable electronic device. During a first phase of the two-phase wakeup mechanism, a motion sensor detects an acceleration event indicative of deployment of the device onto the body of the user. During a second phase of the two-phase mechanism, control circuitry can be adapted to be enabled by the acceleration event. Once enabled, the control circuitry can verify that the device has been launched onto the body of a user via a deployment applicator in which the device is retained until deployment. Once verified, the control circuitry can wake up the body-mountable electronic device by transitioning the device from a sleep state to a functional (or operational) state.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and a computer system are provided. The computer system includes a BMC. The BMC receives, through a management platform on the BMC, a first part of initialization data from an initialization component of a host of the BMC. The BMC also receives an indication of a location at an initialization storage device of the host. The BMC then obtains access to the initialization storage device. The BMC reads a second part of the initialization data from the location of the initialization storage device.

Abstract: An apparatus is provided which comprises: a first circuitry to estimate variation of an internal impedance of a battery; a second circuitry to estimate a high power that the battery can supply for a first time-period, based on the estimated variation of the impedance of the battery; and a third circuitry to facilitate operation of one or more components of the apparatus in accordance with the estimated high power for the first time-period.

Abstract: Systems and methods for reduced boot power consumption using early BIOS controlled CPU power states to enhance power budgeting and allocation. An information handling system may include a server. The server may include a central processing unit (CPU), a memory, a non-volatile random-access memory (NVRAM) device, a performance state (P-state) limiting indicator stored in the NVRAM device, a P-state value stored in the NVRAM, and a basic input/output system (BIOS) stored in the memory. The BIOS may read a power state limiting indicator stored in the NVRAM device and when the power state limiting indicator indicates that power state limiting is enabled, read a power state value stored in the NVRAM, and program the power state of the CPU to the power state value to cause the CPU to limit power supplied to the CPU to the power state value.

Abstract: For a user group to which a first user is assigned, a plurality of configuration settings on client devices used by respective other users in the user group can be identified. A respective homogeneity score can be assigned to each of the identified plurality of configuration settings. For each of the respective configuration settings, at least one configuration setting value can be selected as a candidate configuration setting value based on, at least in part, the homogeneity score assigned to each configuration setting. The candidate configuration setting value for each confirmation setting can be communicated to a client device used by the first user, wherein the client device sets at least one of the configuration settings with a respective candidate configuration setting value.

Abstract: Apparatus, systems, or methods for a programmable circuit to facilitate a processor to boot a computing device having the processor. A programmable circuit may include non-volatile storage and firmware stored in the non-volatile storage. The firmware may configure the programmable circuit as a memory controller of a memory device coupled to the programmable circuit, to facilitate the processor to boot the computing device having the processor, the programmable circuit, and the memory device, into operation. Other embodiments may also be described and claimed.

Abstract: Systems, apparatuses, and methods for reducing chiplet interrupt latency are disclosed. A system includes one or more processing nodes, one or more memory devices, a communication fabric coupled to the processing unit(s) and memory device(s) via link interfaces, and a power management unit. The power management unit manages the power states of the various components and the link interfaces of the system. If the power management unit detects a request to wake up a given component, and the link interface to the given component is powered down, then the power management unit sends an out-of-band signal to wake up the given component in parallel with powering up the link interface. Also, when multiple link interfaces need to be powered up, the power management unit powers up the multiple link interfaces in an order which complies with voltage regulator load-step requirements while minimizing the latency of pending operations.

Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.

Abstract: Embodiments of the present application relate to a method, apparatus, and system for waking up an app. The method includes adding an application (app) to a wake-up alarm group comprising a plurality of apps, adjusting a plurality of alarm wake-up times corresponding to the plurality of apps, wherein the plurality of alarm wake-up times corresponding to the plurality of apps are adjusted to be consistent, and waking up the plurality of apps belonging to the wake-up alarm group according to the adjusted alarm wake-up times corresponding to the plurality of apps belonging to the wake-up alarm group.

Abstract: An apparatus is provided which comprises: a first Power Management Unit (PMU); and a second PMU, wherein the first PMU is to manage transition of the apparatus from a low power state to a first active state, wherein the second PMU is to manage transition of the apparatus from the first active state to a second active state, and wherein the second PMU is to be powered down while the apparatus is to be in the low power state.

Abstract: An exemplary computing environment having a DNN module can maintain one or more bandwidth throttling mechanisms. Illustratively, a first throttling mechanism can specify the number of cycles to wait between transactions on a cooperating fabric component (e.g., data bus). Illustratively, a second throttling mechanism can be a transaction count limiter that operatively sets a threshold of a number of transactions to be processed during a given transaction sequence and limits the number of transactions such as multiple transactions in flight to not exceed the set threshold. In an illustrative operation, in executing these two exemplary calculated throttling parameters, the average bandwidth usage and the peak bandwidth usage can be limited. Operatively, with this fabric bandwidth control, the processing units of the DNN are optimized to process data across each transaction cycle resulting in enhanced processing and lower power consumption.

Abstract: Aspects of the present disclosure involving tuning clock signal sources for communication. As may be implemented in accordance with one or more embodiments, trustworthiness of a message or a source of the message is validated, as indicated by data received over a data bus that communicatively couples a plurality of circuits respectively including an independent clock signal source. Data sent between the circuits can be received by adaptively sampling data that is carried by the data bus. Timing information is calculated relative to data frames of the data received over the data bus, and a clock signal source at one of the circuits is tuned in response to the validating and the calculating.

Abstract: A processor includes a plurality of voltage droop detectors positioned at multiple points of a processor. The detectors monitor voltage levels and alert the processor if a droop event has been detected in real time. Multiple droops can be detected simultaneously, with each detected droop event generating an alert that is sent to a processor module, such as a clock control module, to act based on the detected droop. Each detector employs a ring oscillator that generates a periodic signal and a corresponding count based on that signal, where the frequency of the signal varies based on a voltage at the corresponding point being monitored.

Abstract: A High Speed Inter Chip (HSIC) system and method for minimizing power consumption by controlling the state of the HSIC module through a control line are provided. The method between a host and a slave includes transitioning, when no communication request exists for a first reference time in an active state where all functions of the HSIC modules are enabled, to a suspend state where least functions used for maintaining a communication link of the HSIC modules and transitioning, when no communication request exists for a second reference time in the suspend state, to a power-off state where the HSIC modules turn off. The HSIC communication method and apparatus are advantageous to minimize the electric current consumption of the HSIC consumption system.

Abstract: A configurable device includes computing resources. The configurable device further includes an out-of-band management platform that obtains a configuration request for the configurable device to place the configurable device into a predetermined state; in response to obtaining the configuration request, obtains a configurable device profile associated with the configurable device using an out-of-band channel; instantiates a pre-operating system agent based on the configurable device profile using the computing resources; loads an operating system package into the computing resources using an in-band channel secured by the pre-operating system agent; boots the configurable device using: the operating system package, and the computing resources; and, after booting the configurable device, orchestrates post-operating system automation of the configurable device to place the configurable device into the predetermined state.

Abstract: In one embodiment, a processor includes a plurality of cores to execute instructions, a first identification register having a first field to store a feedback indicator to indicate to an operating system (OS) that the processor is to provide hardware feedback information to the OS dynamically and a power controller coupled to the plurality of cores. The power controller may include a feedback control circuit to dynamically determine the hardware feedback information for at least one of the plurality of cores and inform the OS of an update to the hardware feedback information. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes: one or more cores to execute instructions; a first request register to store hardware performance state control information for a first core of the one or more cores obtained from an operating system; a second request register to store hardware performance state control override information, the hardware performance state control override information to be received from a management controller coupled to the processor; and a power controller coupled to the one or more cores to control a performance state of the first core based at least in part on the hardware performance state override information when at least one override indicator of the second request register is set. Other embodiments are described and claimed.

Abstract: Aspects of the present disclosure are directed to a power specification and Network on Chip (NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC with power domains and clock domains. The PS is configured with one or more power domain finite state machines (PDFSMs) that drive signaling for the power domains of the NoC, and is configured to power the NoC elements of the power domain on or off. NoC elements are configured to conduct fencing or draining operations to facilitate the power state transitions.