Patents Examined by Stefan Stoynov
  • Patent number: 10360042
    Abstract: The method includes authenticating a chip card terminal to a chip card by a chip card operating system, verifying the authorization of the chip card terminal to load executable program instructions by the chip card operating system, storing data in a predefined memory region of the NVM, which data indicate a successful execution of the authentication and the verification, by the chip card operating system, starting execution of a boot loader by the chip card operating system and interrupting the execution of the chip card operating system following the start of the boot loader, reading the data from the predefined memory region by the boot loader, loading the program instructions from the chip card terminal into the NVM by the boot loader on the precondition that the data indicate the successful authentication and verification in the predefined memory region.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: July 23, 2019
    Inventors: Steffen Scholze, Matthias Schwan, Frank Muller, Klaus-Dieter Wirth, Elke Filzhuth
  • Patent number: 10359826
    Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A maximum number of pages that may be treated as non-volatile may be determined based on an amount of energy available in a battery and an amount of energy needed to transfer a page of memory to the non-volatile storage device.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: July 23, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan D. Kelly, Mark A. Santaniello, Sriram Govindan, Anirudh Badam
  • Patent number: 10353858
    Abstract: A system for controlling a subsystem of a vehicle includes a memory, a first processor, and a second processor. The first processor allocates a portion of the memory upon booting to perform operations to control the subsystem and generates an indication when an amount of memory used from the allocated portion of the memory is greater than or equal to a threshold. The first processor monitors times when the vehicle is turned on and off and determines a time period during which the vehicle remains turned off. After the vehicle is turned off, the first processor enters a power save mode. The memory and the second processor continue to receive power. During the time period, on receiving the indication, the second processor wakes up the first processor, which performs a reboot operation, reallocates the memory, and reenters the power save mode. The memory continues to receive power.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: July 16, 2019
    Inventors: Scott A. Rush, Vadim Draluk
  • Patent number: 10345877
    Abstract: Various embodiments of the present technology provide methods for boosting a voltage differential of an energy storage by using a boost component, determining a server system being switched to a boost mode, and discharging the energy storage to provide additional power supplies to the server system during the boost mode. In some embodiments, processing demands of a server system can be monitored. In response to determining that a boost mode is needed to support processing demands of the server system or detecting a component being a bottleneck in processing pipelines of the server system, a boost activation signal can be generated. The boost activation signal can cause a CPU, the bottleneck component, or another component of the server system to operate under a higher clock speed such that a higher processing capacity can be achieved.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: July 9, 2019
    Inventors: Kuang-Hua Ou Yang, Kuo-Chan Hsu, Yun-Teng Shih
  • Patent number: 10345887
    Abstract: Methods and apparatus are provided for adaptive optimization of low-power strategies. In one novel aspect, the device monitors one or more thermal-performance parameters and determines a plurality of operation scenarios for a plurality of corresponding low-power policies. Based on corresponding operation scenarios, the device selects corresponding low-power policy. The device applies different low-power strategy for temperature control based on low-power policies. Different low-power policy is applied to different low-power techniques, such as the DVFS, the CPU hot-plug, and the task migration. In another novel aspect, the device obtains one or more user-defined policy for each corresponding low-power technique. The selection of each low-power policy is further based on its corresponding user-defined policy. In one embodiment, the user-defined DVFS policy includes power policy, performance policy, and DVFS-balanced policy.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: July 9, 2019
    Assignee: MEDIATEK INC.
    Inventors: Kuo-SU Hsiao, Yen-Lin Lee, Shih-Yen Chiu, Jia-Ming Chen, Mark Shane Peng, Ya-Ting Chang
  • Patent number: 10345886
    Abstract: An image forming apparatus includes a display unit with a power saving function, where the display unit is turned off after a predetermined period of time has elapsed to save power. If however, the display unit is displaying a code used by external devices to establish communication with the image forming apparatus, the power saving function is disabled during the time period the code is being displayed.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 9, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kou Hiraike
  • Patent number: 10338659
    Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: July 2, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
  • Patent number: 10324516
    Abstract: A method for detecting and responding to a configuration setting capable of causing undesired energy consumption in a configurable electronic device comprises measuring a power state of at least one connection point of the configurable electronic device to establish a measured power state value; comparing the measured power state value with a stored power state value for the connection point; and responsive to a discrepancy between the measured power state value and the stored power state value for the connection point where the discrepancy is capable of causing undesired energy consumption, emitting a condition signal.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: June 18, 2019
    Assignee: ARM IP Limited
    Inventors: Brendan James Moran, James Crosby, Milosch Meriac
  • Patent number: 10317971
    Abstract: Provided are an electronic device and method for controlling functions of the electronic device according to attachment of an external device. The electronic device includes an interface part that electrically contacts an external device, and a processor that determines, when an external device is electrically connected, whether the external device has a second power source, and controls usage of a first power source of the electronic device according to a result of the determination.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaeyoung Shin, Woongeun Kwak, Sangyong Kim, Jinwoo Kim, Jungsik Park, Seungwon Oh, Byounguk Yoon, Sehwan Choi, Hyunju Hong
  • Patent number: 10320577
    Abstract: In one example, a method for inhibiting input at a remotely-booted computer. A wake-on-LAN signal is received at the computer from a network while the computer is in a low-power state. A boot function of the computer sets an indicator indicative of a wake-on-LAN condition, the indicator accessible by an operating system of the computer. The operating system is loaded, including a filter driver for an input device of the computer. The filter driver is to intercept input from the device to a function driver for the device. When the indicator is set, input received from the input device is disregarded.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: June 11, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Chin-Yu Wang
  • Patent number: 10303203
    Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: May 28, 2019
    Inventors: Ho Yeon Jeon, Ah Chan Kim, Jae Gon Lee
  • Patent number: 10296062
    Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that require an operation voltage. The memory devices are capable of obtaining the operation voltage either from a power supply external to the memory device or from respective charge pumps internal to the memory devices. The processor is configured to predict storage activity in the memory devices, and to cause the memory devices to select a source for the operation voltage between the power supply and the respective charge pumps in accordance with the predicted storage activity.
    Type: Grant
    Filed: February 18, 2018
    Date of Patent: May 21, 2019
    Assignee: APPLE INC.
    Inventors: Barak Rotbard, Assaf Shappir
  • Patent number: 10281965
    Abstract: In an embodiment, a system may support a “coast mode” in which the power management unit (PMU) that supplies the supply voltage to an integrated circuit is disabled temporarily for certain modes of the integrated circuit. The integrated circuit may continue to operate, consuming the energy stored in capacitance in and/or around the integrated circuit. When coast mode is initiated, a time interval for coasting may be determined. When the time interval expires, the PMU may re-enable the power supply voltage.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: May 7, 2019
    Assignee: Apple Inc.
    Inventors: Joseph T. DiBene, II, Inder M. Sodhi, Gerard R. Williams, III
  • Patent number: 10268631
    Abstract: A programming file including a first module is loaded to a programmable component. And then, the programmable component is dis-reset. Subsequently, first data is loaded to a memory connecting with the programmable component, to enable the first module in the programmable component to convert the first data of the memory into second data. After the first module of the programmable component converts the first data of the memory into the second data, a second module is loaded to the programmable component. The first module in the programming file is then replaced with the second module, to enable the second module to access the second data.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 23, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Changzhong Ge, Jianming Song, Kai Ren
  • Patent number: 10261920
    Abstract: An apparatus and method of a static image RAM drive is provided. The system includes a field programmable gate array (FPGA), a volatile memory drive, a non-volatile memory drive, and a power source. The non-volatile memory drive has a secure memory space. The secure memory space is programmed with an encryption key and an encrypted disk image. In response to a power cycle, the FPGA reads the encrypted disk image from the non-volatile memory, authenticates the disk image using the encryption key, decrypts the encrypted disk image, and writes the decrypted disk image to the volatile memory. The decrypted disk image is used to boot a computer. The computer is booted to a known good state each time the power is cycled.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: April 16, 2019
    Assignee: The United States of America as presented by the Secretary of the Navy
    Inventor: Donna Bell
  • Patent number: 10209755
    Abstract: A system comprises a first domain 4 and second domain 6 which communicate via an interface 8. The first domain 4 transmits power state commands to the second domain 6 for controlling transitions of power states at the second domain 6. The power state commands include at least a power up command 50 for triggering a transition to a power up state and a power no-operation command 52 in response to which the second domain remains in the current one of the power states. The no-operation command 52 enables the second domain 6 to be left in either the power up state or a different power state even if the first domain 4 is powered down.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: February 19, 2019
    Assignee: ARM Limited
    Inventors: David Walter Flynn, Vasan Venkataraman
  • Patent number: 10209754
    Abstract: A communication apparatus comprises: a power supply; a communication unit configured to operate by using power from the power supply or a communication partner; an operation unit; a control unit configured to execute software for controlling processing of each unit of the communication apparatus, wherein the control unit starts processing to stop execution of the software if an operation to the operation unit is started while the control unit is executing the software; a power supply control unit configured to control power that is supplied to the control unit, in accordance with a state of as operation with respect to the operation unit; and a disabling unit configured to disable the communication unit, based on the state of the operation with respect to the operation unit and an execution state of the software.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: February 19, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shuya Kaechi
  • Patent number: 10210046
    Abstract: A computer system includes a memory unit and a processing unit. The memory unit is configured to store a default setting value with an image file form. The processing unit is electrically connected to the memory unit, and configured to read the default setting value with the image file form from the memory unit. When the computer system is unable to be activated, the processing unit is configured to trigger the computer system to activate a safe mode of a basic input/output system, and to compare the default setting value with a system setting value of the computer system to generate a comparison result, so as to adjust and reactivate the computer system according to the comparison result.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: February 19, 2019
    Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventors: Chien-Chih Wang, Yung-Sheng Chiang
  • Patent number: 10198270
    Abstract: At initiation of boot of a computing device, a processor executes a firmware interface of the computing device, like a basic input/output system (BIOS) or a unified extended firmware interface (UEFI). The processor executes the firmware interface to detect whether a dynamic hardware configuration (DHC) function has been enabled. In response to detecting that the DHC function has been enabled, the processor executes the firmware interface to configure hardware components of the computing device according to a DHC, such as to selectively disable the hardware components. After configuring the hardware components according to the DHC, the processor proceeds to boot the computing device.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: February 5, 2019
    Assignee: Lenovo Enterprise Solutions (Singapore) PTE. LTD.
    Inventors: Ralph Saul Cooper, Michael Charles Elles, Robert Anthony Fenoglio, Paul Klustaitis, Luis Rene Quinones Supelveda, Jeffrey B. Williams
  • Patent number: 10180846
    Abstract: What is disclosed is a device interoperability system for one or more user devices associated with a user, wherein said one or more user devices comprises a first user device, said device interoperability system comprising a communications module, wherein a first connection is established between said first user device and said communications module; storage associated with said device interoperability system and coupled to said communications module, wherein said storage stores an operating system, one or more programs, and data associated with the user, further wherein said operating system is booted by said first user device via said first connection; and one or more processors to support said device interoperability system.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: January 15, 2019
    Assignee: Simpleway Technologies Ltd.
    Inventors: Artem Bohdan, Ievgen Krutov