Abstract: A processor system and method is described. The processor system includes a central processing unit (CPU) comprising a register for storing a stack pointer value, a non-volatile memory coupled to the CPU and having a first non-volatile memory region configured to store instructions executable by the CPU and a second non-volatile memory region configured to store a RAM-image comprising program context data. The processor system includes a random-access memory (RAM) coupled to the CPU and having a first RAM region and a second RAM region. The processor system is configured to have a first operating mode where the RAM data values are not retained and a second operating mode where the RAM is powered on.

Abstract: Methods, systems, apparatuses, and computer-readable storage mediums are described for altering a power consumption of a battery-powered device. In an example system, a power monitor is configured to measure, for each of a plurality of components in the battery-powered device, a power consumption of the component during execution of an AI model that is stored on the device. A consumption analyzer is configured to predict whether a battery criterion would be satisfied during operation of the battery-powered device based on the measured power consumption of the components. In examples, operation of the device may include operation of the device in which the AI model is executed. A model retraining engine retrains the AI model if the battery criterion is not predicted to be satisfied during operation of the device, and a retrained AI model may be provided for execution on the battery-powered device.

Abstract: A computer system having a firmware verification mechanism includes a plurality of non-transitory storage circuits and a processing circuit. Each of the non-transitory storage circuits stores at least one of a plurality of strings not generated by using a random number. The processing circuit is configured to perform steps for firmware verification. The firmware verification includes the following steps. A to-be verified block of the device firmware is loaded. A plurality of public key composition strings of the strings are retrieved from the non-transitory storage circuits to combine the public key composition strings into a public key. The to-be verified block is compared with the public key to determine whether the to-be verified block is generated based on a private key calculated from the public key. When the to-be verified block is generated by the private key, it continues to perform a chain of trust verification.

Abstract: An embedded electronic device, a boot method, and an electronic device readable recording medium with a stored program are provided. A processor in the embedded electronic device executes a plurality of stage boot procedures after the embedded electronic device is powered on. Each of the stage boot procedures includes: executing current-stage boot firmware; reading a test request message and a firmware location message from a first memory; loading next-stage boot firmware according to the firmware location message in response to the test request message being a current-stage request; and updating the test request message to a next-stage request and updating the firmware location message to a next boot firmware location when the loading of the next-stage boot firmware succeeds, or otherwise, updating the test request message to a failure message and soft rebooting the embedded electronic device.

Abstract: An example of an apparatus is provided. The apparatus includes a power supply to connect to a power source. The power supply is to receive and to distribute a total power from the power source. The apparatus further includes a first device to receive a first portion of the total power from the power supply. The apparatus further includes a second device to receive a second portion of the total power from the power supply. A sum of the first portion and the second portion is the total power. In addition, the apparatus includes a controller to control the second device, wherein the controller is to determine the total power demanded by the first device and the second device. The controller is to reduce the second portion of the total power and to restore the second portion of the total power.

Abstract: A computing system has a first processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. In one approach, the computing system is configured to: collect data associated with operation of an autonomous vehicle; monitor, by a first processing device, the collected data; and based on the monitoring, determine that an event on the autonomous vehicle has occurred. The computing system is further configured to, in response to determining that the event has occurred, initiate a transfer of data controlled by a second processing device, the transfer including copying data stored in volatile memory of the autonomous vehicle to non-volatile memory of the autonomous vehicle, wherein the second processing device controls copying of the data independently of the first processing device.

Abstract: A processing system comprises a first subsystem comprising at least one host processor and one or more storage units, and a second subsystem comprising at least one second processor. Each second processor comprises a plurality of tiles. Each tile comprises a processing unit and memory. At least one storage unit stores bootloader code for each of first and second subsets of the plurality of tiles of at least one second processor. The first subsystem writes bootloader code to each of the first subset of tiles of the at least one second processor. At least one of the first subset of tiles requests at least one of the storage units to return the bootloader code to the second subset of the plurality of tiles. Each tile to which the bootloader code is written retrieves boot code from the storage unit and then runs said boot code.

Abstract: A system for controlling a processor, comprising a processor configured to load one or more instructions into a register for execution, a non-volatile memory coupled to the processor and configured to store data in a format that can be read by the processor and a description file stored in the non-volatile memory, the description file further comprising a plurality of information files, wherein each information file includes two or more types of predetermined data.

Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

Abstract: Examples include a computing system including a network input/output (I/O) device, the network I/O device including a microcontroller, a network controller, and a proxy mode monitor to enter a proxy mode by causing transfer of control of the network controller from a processor to the microcontroller without resetting the network controller, and to exit the proxy mode by causing transfer of control of the network controller from the microcontroller to the processor without resetting the network controller.

Abstract: In certain embodiments, an electronic device comprises a temperature sensor; and a processor, wherein the processor is configured to: detect that a temperature of the electronic device exceeds a predetermined temperature; when the temperature exceeds the predetermined temperature, drive at least one process satisfying a predetermined condition for a proportion of time periods and not driving the at least one process during remaining time periods.

Abstract: An information processing apparatus includes: a power supply unit that supplies power to a connection terminal for connection to an external device; a communication control unit that performs data communication with an external device connected to the connection terminal; an operating state detection unit that detects a signal indicating that a controller including at least the communication control unit has entered hibernation; and a power supply control unit that stops power supply to the connection terminal when the signal indicating that the controller has entered hibernation is detected by the operating state detection unit.

Abstract: A wireless mobile device in a public communication network receives network-initiated signaling or messaging, while operating in a battery-conserving mode, or modes that, keep(s) minimal baseband processing functions awake. The baseband processing functions process incoming signaling or data in a received message to determine whether to act further on information in the incoming message by enabling additional processing capability in the mobile device. The mobile device may have permanent template criteria values, either coded in firmware or implemented in hardware, or temporary template criteria values, stored in RAM or processor registers, that are compared to values of an incoming message or datagram from the mobile network to determine whether to perform additional actions, such as awakening an application processor.

Abstract: An electronic device includes a plurality of cores, and a clock generator configured to provide a plurality of clock signals to the plurality of cores, respectively, wherein the plurality of cores includes a system core that controls the clock generator to generate the clock signals having frequencies of the respective cores, wherein the frequencies are optimized and determined based on a type of an event of the electronic device, and wherein to clock signals with optimized frequencies are applied to the respective cores in order to perform the event.

Abstract: This disclosure describes systems, devices, and techniques for quick restarts of virtualized resources hosted by a cloud-based network. In an example method, a request to restart a virtualized resource hosted by a first server can be received. A second server, with a capacity to host the virtualized resource, may be identified. In response to identifying the second server, the virtualized resource can be migrated from the first server to the second server. A message confirming that the virtualized resource has been restarted may be transmitted.

Abstract: Described are context-aware low-power systems and methods that reduce power consumption in compute circuits such as commonly available machine learning hardware accelerators that carry out a large number of arithmetic operations when performing convolution operations and related computations. Various embodiments exploit the fact that power demand for a series of computation steps and many other functions a hardware accelerator performs is highly deterministic, thus, allowing for energy needs to be anticipated or even calculated to a certain degree. Accordingly, power supply output may be optimized according to actual energy needs of compute circuits. In certain embodiments this is accomplished by proactively and dynamically adjusting power-related parameters according to high-power and low-power operations to benefit a machine learning circuit and to avoid wasting valuable power resources, especially in embedded computing systems.

Abstract: The present disclosure relates to a method for expanding a functionality of a field device for process automation technology in a system using a configuration device, comprising the steps of: establishing a connection from the configuration device to the field device; reading out an order code using the configuration device, wherein the order code represents the current functionalities of the field device; displaying the functionality of the field device on the configuration device; selecting additional, alternative, or lessened functionality of the field device using the configuration device; establishing a connection to a central station; sending information about the additional, alternative, or lessened functionality of the field device to the central station; sending an activation code to activate the additional, alternative, or lessened functionality from the central station; and sending the activation code from the configuration device to the field device and activating the additional, alternative, or l

Abstract: A memory includes writable memory units. Each memory unit is configurable: in a retention state wherein the memory unit is capable of retaining data until a subsequent power-off of the memory unit, and in a non-retention state wherein the memory unit does not retain data and consumes less power than in the first state. A controller configures any memory unit of the memory having undergone at least one write access since its last power-up to be in the retention state. The controller further configures at least one memory unit of the memory that has not undergone any write access since its last power-up in the non-retention state.

Abstract: A system with improved power performance for tasks executed in parallel. A plurality of processing cores each to execute tasks. An inter-core messaging unit to conveys messages between the cores. A power management agent transitions a first core into a lower power state responsive to the first core waiting for a second core to complete a second task. In some embodiments long messages are subdivided to allow a receiving core to resume useful work sooner.

Abstract: A self-tuning computing system and a method for self-tuning a computing system. The method includes measuring a current operation metric representing a current performance of the computing system; determining, based on the current operation metric and a target metric, at least one optimization scheme for improving the current operation metric, wherein the at least one optimization scheme includes at least a plurality of system knobs each having a respective optimal value; and setting each of the system knobs listed in the at least one determined optimization scheme to its respective optimal value.