Patents Examined by Stefan Stoynov
  • Patent number: 10180846
    Abstract: What is disclosed is a device interoperability system for one or more user devices associated with a user, wherein said one or more user devices comprises a first user device, said device interoperability system comprising a communications module, wherein a first connection is established between said first user device and said communications module; storage associated with said device interoperability system and coupled to said communications module, wherein said storage stores an operating system, one or more programs, and data associated with the user, further wherein said operating system is booted by said first user device via said first connection; and one or more processors to support said device interoperability system.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: January 15, 2019
    Assignee: Simpleway Technologies Ltd.
    Inventors: Artem Bohdan, Ievgen Krutov
  • Patent number: 10182398
    Abstract: An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service latency tolerance value for a first state and a service latency tolerance value for a second state. The service latency tolerance value for the first state is greater than the service latency tolerance value for the second state.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Jaya L. Jeyaseelan, Jim Walsh, Robert E. Gough, Barnes Cooper, Neil W. Songer
  • Patent number: 10175717
    Abstract: An information handling system includes a processor complex and a microcontroller unit (MCU). The processor complex includes a Real-Time Clock (RTC) function associated with a port of the processor complex, and that can be invoked on the processor complex by a call to the port. The MCU includes RTC logic to maintain time base information for the information handling system. When the RTC function is invoked, the processor complex traps the call to the port and redirects the call to the MCU. When the MCU receives the redirected call, the MCU invokes the RTC logic to respond to the redirected call and to provide the time base information to the processor complex.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 8, 2019
    Assignee: DELL PRODUCTS, LP
    Inventors: Timothy M. Lambert, Jeffrey L. Kennedy
  • Patent number: 10152111
    Abstract: A network device includes a network interface circuit, a microprocessor, a timing circuit, and a microsequencer. The timing circuit is configured to, based on a primary timing signal, generate a time signature and switch the network device from an inactive state to an active state when the time signature satisfies a predetermined threshold length of time for packet transmission. The microsequencer circuit is configured to, in response to the network device being switched to the active state, activate and configure the network interface circuit for the packet transmission, independent of the microprocessor and delays encountered by the microprocessor. The device also reduces energy consumption by using a lower frequency secondary oscillator to maintain timing information when a higher frequency primary oscillator is inactivated.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: December 11, 2018
    Assignee: Linear Technology Corporation
    Inventors: Brett Warneke, Maxim Moiseev
  • Patent number: 10146557
    Abstract: A method for initializing a memory that is part of an electronic device, comprising: receiving a sequence for initializing the memory from an external booting device; and causing the memory to perform initialization by using a first command that is generated based on the sequence.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: December 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Suk Jung, Jeong-Han Kim, Woo-Kwang Lee
  • Patent number: 10133331
    Abstract: Various embodiments are generally directed to operation of a computing device powered with first and second sets of energy storage cells, the cells of the first set structurally optimized for higher density storage of electric power, and the cells of the second set structurally optimized for providing electric power at a high electric current level. A battery module includes a casing, a first cell disposed within the casing to store electric energy with a high density, and a second cell disposed within the casing to provide electric energy stored therein with a high current level. Other embodiments are described and claimed herein.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: November 20, 2018
    Assignee: INTEL CORPORATION
    Inventors: Tawfik M. Rahal-Arabi, Alexander B. Uan-Zo-Li, Mark MacDonald, Vivek M. Paranjape, Andy Keates, Don J. Nguyen
  • Patent number: 10127055
    Abstract: Various examples of the present technology provide a method for iSCSI based bare metal OS image deployment and diskless boot in a server system. In some examples, methods for iSCSI based bare metal OS image deployment and diskless boot in a server system comprise setting a boot order of a BIOS of the server system to iSCSI NIC of a controller (e.g., BMC) of the server system, setting iSCSI boot configuration to the controller, updating the boot order based at least upon information from the controller, syncing the iSCSI boot configuration to the BIOS of the server system based upon the information from the controller, and causing the server system to be booted from a specific target IP and LUN of an iSCSI storage server of a SAN.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: November 13, 2018
    Assignee: QUANTA COMPUTER INC.
    Inventor: Ching-Chih Shih
  • Patent number: 10126799
    Abstract: Systems and methods for providing diagnostic information by an intelligent power tap is disclosed. The intelligent power tap includes a circuit board. The intelligent power tap includes a microcontroller disposed on the circuit board, where the microcontroller is configured to report the geographical location of the intelligent power tap. The intelligent power tap includes a physical layer network interface connected to the microcontroller and the physical network. The intelligent power tap includes a switch controlled by the microcontroller, where the switch is capable of shutting off a network power to be injected into the network system.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: November 13, 2018
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Steven T Haensgen, John P Caspers
  • Patent number: 10120435
    Abstract: An integrated circuit device includes a peripheral control circuit configured to receive a low power intent signal from a first processor, and a first control register in the peripheral control circuit. The first control register includes a peripheral enable indicator for each processor that can use a first peripheral. Acknowledgement logic circuitry is configured to assert a first low power acknowledgement signal when the first processor issuing the low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the first processor in the first control register.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 6, 2018
    Assignee: NXP USA, Inc.
    Inventors: Simon J. Gallimore, Colin MacDonald, James H. Carlquist
  • Patent number: 10115442
    Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A number of pages that may be treated as non-volatile may be determined based on demand for non-volatile storage by at least one application executing on the computing device.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 30, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan D. Kelly, Mallik Bulusu, Ravi Mysore Shantamurthy, Tom L. Nguyen
  • Patent number: 10114441
    Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Paul S. Diefenbaugh, Eugene Gorbatov, Andrew Henroid, Eric C. Samson, Barnes Cooper
  • Patent number: 10108238
    Abstract: Systems and methods for providing diagnostic information by an intelligent power tap is disclosed. The power tap includes a circuit board and a microcontroller disposed on the circuit board. The microcontroller is configured to provide a status report of the intelligent power tap. The power tap further includes a physical layer network interface connected to the microcontroller and the physical network. The intelligent power tap is configured to inject at least one of a network power and a switched power into the network system.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: October 23, 2018
    Assignee: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
    Inventors: Steven T Haensgen, John P Caspers, Yutao Wang, Jeffrey A Kilburn, Darryl E Whitley
  • Patent number: 10108216
    Abstract: Systems and methods are provided for a power tap with adjustable configuration. The power tap includes a circuit board that acts on the adjustable configuration to define the function of the power tap in the system. The power tap may include a microcontroller or a set of discrete logic disposed on a circuit board connected to an adjustable configuration mechanism, which defines the intelligent power tap's function in the network system.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: October 23, 2018
    Assignee: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
    Inventors: Steven T Haensgen, John P Caspers, Yutao T Wang, Jeffrey A Kilburn, Darryl E Whitley
  • Patent number: 10102006
    Abstract: Embodiments of the disclosure provide a method and apparatus for controlling a startup bootstrap program of an intelligent TV set, and relate to the field of an embedded system so as to shorten a period of time for startup boot while initializing a screen normally. In the disclosure, after a system is powered on, a first task of initializing a screen in a startup bootstrap program is executed, and the length of preset time required for executing the first task is obtained, wherein the startup bootstrap program is a bootstrap program for initializing pieces of software/hardware of the system; executing a second initialization task unrelated to initializing the screen in the startup bootstrap program is executed while the first task is being executed, thus addressing the problem in the related art.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 16, 2018
    Assignees: HISENSE ELECTRIC CO., LTD., HISENSE USA CORPORATION, HISENSE INTERNATIONAL CO., LTD.
    Inventors: Zengbo Li, Jian Zuo, Dejin Chu
  • Patent number: 10102377
    Abstract: Protecting secured boot secrets while starting an operating system. Embodiments include identifying that a second operating system is to be started to replace a first operating system, and loading code of the second operating system in a protected portion of the system memory. The protected portion of the system memory is then unprotected, and processor state is set to initiate execution of the code of the second operating system, while using one or more secured boot secrets that were stored in the protected portion of the system memory by the first operation system to attest a security status of the second operating system. The portion of the system the memory is re-protected, including preventing access to the portion of the system memory by the second operating system.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: October 16, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Alain Gefflaut, Andrey Shedel
  • Patent number: 10095291
    Abstract: An information processing apparatus includes a first power supply unit, a first device and a second device to which power is supplied from the first power supply unit, a second power supply unit, a third device to which power is supplied from each of the first power supply unit and the second power supply unit, and a power control unit configured to perform control to switch a power supply source for the third device from the first power supply unit to the second power supply unit, and then to cause power to be supplied from the first power supply unit to the second device.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: October 9, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Katsuhiko Yanagawa
  • Patent number: 10067769
    Abstract: A checking method for electronic device includes receiving a fast boot signal and entering into a fast boot stage in response to the fast boot signal. The fast boot stage includes executing a part of bootstrap program, reading machine information of an electronic device after the execution of the part of bootstrap program is finished, driving an output module of the electronic device, outputting an external signal by the output module according to the machine information, and staying in the fast boot stage after the external signal is output.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: September 4, 2018
    Assignee: WISTRON CORPORATION
    Inventor: Cheng-Chia Lai
  • Patent number: 10054977
    Abstract: Managing system clocks of virtual machines. A host system clock value of a host system clock of a host system is obtained, and a virtual machine system clock value of a system clock of a virtual machine managed by the host system is determined. The determining of the virtual machine system clock value includes using the host system clock value and a system clock adjustment value. The system clock of the virtual machine is adjusted using the virtual machine system clock value.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ivan Mikhaylov, Ivan Mironov, Petr Petrov
  • Patent number: 10054998
    Abstract: A portable power device including an enclosure, a plurality of power elements housed within the enclosure, and a controller housed within the enclosure and configured to control the power output of the plurality of power elements. The controller is configured to determine if the portable power device is located on an aircraft that is operating in a stationary, taxiing, or flight mode, and if the aircraft is in the stationary, taxiing, or flight mode, to prevent power to be supplied from the plurality of power elements.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: August 21, 2018
    Assignee: CARRIER CORPORATION
    Inventors: Stephen Varga, Craig Stephen Blumsack
  • Patent number: 10054978
    Abstract: Managing system clocks of virtual machines. A host system clock value of a host system clock of a host system is obtained, and a virtual machine system clock value of a system clock of a virtual machine managed by the host system is determined. The determining of the virtual machine system clock value includes using the host system clock value and a system clock adjustment value. The system clock of the virtual machine is adjusted using the virtual machine system clock value.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ivan Mikhaylov, Ivan Mironov, Petr Petrov