Abstract: A system and method for managing energy consumption of one or more processor cores in a multicore processing device. The method includes translating each activity level of the one or more processor cores to a respective charge value. The method also includes generating, at least partially subject to each translated charge value, one or more charge replenishment requests associated with the one or more processor cores. The method further includes transmitting the one or more charge replenishment requests to a pending queue prior to a delay queue.

Abstract: A semiconductor device includes an intellectual property (IP) block, a clock management unit, a critical path monitor (CPM), and a CPM clock manager included in the clock management unit. The clock management unit is configured to receive a clock request signal, indicating whether the IP block requires a clock signal, from the IP block and perform clock gating for the IP block based on the received clock request signal. The CPM is configured to monitor the clock signal provided to the IP block to adjust at least one of a frequency of the clock signal provided to the IP block and a voltage supplied to the IP block. The CPM clock manager is configured to perform the clock gating for the CPM.

Abstract: A device for monitoring the execution of an application on a processor, the device comprising: a time counter, a control module configured to reset the time counter at the end of a time period if a reset command has been received by the monitoring device in a time window and to generate a sanction command of the processor otherwise, an inhibition module configured to inhibit the time counter during the reception of an inhibition command at the input of the monitoring device, and a reactivation module configured to reactivate the time counter during the reception of a reactivation command at the input of the monitoring device.

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Abstract: An information handling system may include a processor, a data processing unit communicatively coupled to the processor, a logic device communicatively coupled to processor and configured to, responsive to a shutdown event associated with the information handling system, cause a power system of the information handling system to maintain delivery of electrical energy to the data processing unit until receiving a command to cause withdrawal of the electrical energy to the data processing unit, and a management controller communicatively coupled to the processor, the data processing unit, and the logic device, and configured for out-of-band management of the information handling system.

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

Abstract: A portable computing device including a central processing unit (CPU) and a controller is provided. The controller is coupled between the CPU, a graphics processing unit, and a battery module. The controller determines whether to adjust performance of the CPU and the graphics processing unit according to at least one of a battery capacity, a battery power, a battery current, a battery voltage, or a battery temperature of the battery module.

Abstract: The present disclosure provides systems and techniques for reducing power consumption at an electromechanical gun. The electromechanical gun may transition to an inactive state to reduce power consumption, and the electromechanical gun may transition to an active state to perform a system check procedure or to allow a projectile to be fired from the electromechanical gun. The electromechanical gun may identify a sleep event based on an analysis of an output of a first electronic component, compute an estimated time duration based on an amount of electric charge remaining in the energy store, set a sleep timer according to the estimated time duration, and transition to the inactive state by terminating a power supply of a second electronic component. The electromechanical gun may transition to the active state in response to the sleep timer elapsing or a second output indicating that a user is touching the electromechanical gun.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may: determine a difference between a first voltage value associated with an electrical power output of a power system of an information handling system (IHS) and a second voltage value associated with a battery system of the IHS is greater than a first voltage value threshold; turn a first switch on to conduct electrical power from the battery system to an electrical power output of the power system; set a voltage value associated with the electrical power output to a voltage value associated with the battery system; permit an amount of time to transpire; determine a difference between a third voltage value associated with the electrical power output and a fourth voltage value associated with the battery system is less than a second voltage value threshold; and turn the first switch off.

Abstract: A method and apparatus for performing dynamic current scaling of an input current of a voltage regulator are provided. The method and apparatus allow tuning current consumption in various applications, calculating a duration of an activity phase in which various algorithms are executed and activating dynamic current scaling of a regulator if the activity duration is shorter than a programmable threshold. A controller receives a threshold for an activity duration and a window size in which to evaluate the activity duration.

Abstract: Systems and methods are disclosed for reducing the power consumption of a system. Techniques are described that queue a message, sent by a source engine of the system, in a queue of a destination engine of the system that is in a sleep mode. Then, a priority level associated with the queued message is determined. If the priority level is at a maximum level, the destination engine is brought into an active mode. If the priority level is at an intermediate level, the destination engine is brought into an active mode when a time, associated with the intermediate level, has elapsed. When the destination engine is brought into an active mode it processes all messages accumulated in its queue in an order determined by their associated priority levels.

Abstract: Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.

Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

Abstract: The technology described herein is related to a two-phase deployment-initiated wakeup mechanism for a body-mountable electronic device. During a first phase of the two-phase wakeup mechanism, a motion sensor detects an acceleration event indicative of deployment of the device onto the body of the user. During a second phase of the two-phase mechanism, control circuitry can be adapted to be enabled by the acceleration event. Once enabled, the control circuitry can verify that the device has been launched onto the body of a user via a deployment applicator in which the device is retained until deployment. Once verified, the control circuitry can wake up the body-mountable electronic device by transitioning the device from a sleep state to a functional (or operational) state.

Abstract: Example implementations relate to a power sourcing equipment (PSE), and a method of reallocating power to one or more powered devices (PDs) by the PSE, before a swap event of a power supply unit (PSU). The method includes receiving an information about the swap event, determining based on the information that the swap event is expected to cause powering down of the one or more PDs, and requesting a first PD among the one or more PDs to permit the PSE to reduce an initial value of power allocated to the first PD. Further, the method includes reducing an amount of power to the first PD from the initial value to a reduced value of power based on a response from the first PD, and reallocating the reduced value of the power to the first PD to avoid powering down of the one or more PDs during the swap event.

Abstract: Described are context-aware low-power systems and methods that reduce power consumption in compute circuits such as commonly available machine learning hardware accelerators that carry out a large number of arithmetic operations when performing convolution operations and related computations. Various embodiments exploit the fact that power demand for a series of computation steps and many other functions a hardware accelerator performs is highly deterministic, thus, allowing for energy needs to be anticipated or even calculated to a certain degree. Accordingly, power supply output may be optimized according to actual energy needs of compute circuits. In certain embodiments this is accomplished by proactively and dynamically adjusting power-related parameters according to high-power and low-power operations to benefit a machine learning circuit and to avoid wasting valuable power resources, especially in embedded computing systems.

Abstract: Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.

Abstract: An electronic system has a plurality of power domains, and each domain includes a subset of one or more processor clusters, first memory, PMIC, and second memory. A plurality of power sensors are distributed on the electronic system and configured to collect a plurality of power samples from the power domains. A power management engine is configured to process the power samples based on locations of the corresponding power sensors to generate one or more power profiles and a plurality of power throttling thresholds. The power manage engine is configured to implement a global power control operation by determining power budgets of the power domains on a firmware level and enabling operations of the power domains accordingly. The power manage engine is also configured to enable a plurality of local power control operations to be directly implemented on the power domains based on the power throttling thresholds.

Abstract: A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.

Abstract: Aspects of the disclosure provide an apparatus for executing a program that involves a plurality of operators. For example, the apparatus can include an executor and an analyzer. The executor can be configured to execute the program with at least a first one of the operators loaded on a second memory from a first memory that stores the operators and to generate a signal based on a progress of the execution of the program with the first operator. The analyzer can be coupled to the executor, the first memory and the second memory, and configured to load at least a second one of the operators of the program next to the first operator stored in the first memory to the second memory before the executor finishes execution of the program with the first operator based on the signal from the executor and an executing scheme stored in the second memory.