Abstract: An information processing apparatus includes a first memory configured to retain a request group, based on requests received by a reception interface, a second memory configured to retain a request group, based on requests received by the reception interface, and a first transmission interface configured to transmit the request group retained in the first memory to the first storage and a second transmission interface configured to transmit the request group retained in the second memory to the second storage. The request group transmitted by the first transmission interface and the request group transmitted by the second transmission interface are different request groups.

Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.

Abstract: An information handling system may include at least one processor; a network interface; and a physical storage resource including a flash translation layer (FTL) operable to provide a mapping between logical storage addresses and physical storage addresses. The information handling system may be configured to: receive a request for a snapshot; for used portions of the physical storage resource, change a metadata identifier from a used status to a snapshot status; prevent deletion of those portions associated with the snapshot status; and transmit, via the network interface, information associated with the portions that are associated with the snapshot status.

Abstract: There is provided a technique to enable a specific IC chip to reliably activate the other IC chips. An information processing apparatus has first to third IC chips and, after loading an activation program for the third IC chip from a first storage unit connected to the first IC chip into a third storage unit connected to the third IC chip, accesses a register and activates the third control unit.

Abstract: A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata.

Abstract: An apparatus has processing circuitry (18), and memory access circuitry (35) to control access to a memory system based on memory attribute data identifying each memory region as one of a plurality of region types. A speculation-restricted region type is supported, for which: at least when a first read request is non-speculatively issued to a region of the speculation-restricted type, a subsequent read request is permitted to be serviced using data obtained in response to the first read request; and for a speculatively issued read request to the region of the speculation-restricted type, at least when caching the read data would require allocation of a new entry in the cache, at least one response action, which is permitted for non-speculatively issued read requests specifying a target memory region of the speculation-restricted region type, may be prohibited from being performed before the first read request has been resolved as correct.

Abstract: A storage system stores data in a primary block and a copy of the data in a secondary block. Parity bits are stored with the data and the copy of the data. A header with logical block information is stored with the copy of the data in the secondary block. The data in the primary block is not stored with a header, which allows more parity bits to be stored with the data in the primary block. This provides more robust error protection for the data stored in the primary block and reduces the need to rely upon the copy of the data in the secondary block.

Abstract: A zone is loaded onto a first memory component of a storage system, wherein the zone comprises one or more regions of data blocks comprising a first plurality of logical block addresses (LBAs), and a snapshot of each of the one or more regions is stored on a second memory component of the storage system and is associated with a version identifier. A particular version identifier associated with a respective snapshot of a region is identified, and a set of journals stored on the second memory component are identified, wherein the set of journals comprise a second plurality of LBAs mapped to a second plurality of physical block addresses.

Abstract: A method for dynamically managing host read operation and read refresh operation in a storage device, a storage device and a storage medium thereof are provided. The method includes: controlling, by a controller of the storage device, a ratio of the number of host read operation to the number of read refresh operation in the storage device to be in line with a first value and obtaining a total read request count which accumulates in the storage device; when a criterion for updating the ratio is satisfied, determining, by the controller, a second value for the ratio of the number of host read operation to the number of read refresh operation according to the total read request count and information of blocks to be refreshed in the storage device; and controlling, by the controller, the number of host read operation and the number of read refresh operation so that a ratio of the number of host read operation to the number of read refresh operation is in line with the second value.

Abstract: An apparatus comprises memory management circuitry to perform a translation table walk for a target address of a memory access request and to signal a fault in response to the translation table walk identifying a fault condition for the target address, prefetch circuitry to generate a prefetch request to request prefetching of information associated with a prefetch target address to a cache; and faulting address prediction circuitry to predict whether the memory management circuitry would identify the fault condition for the prefetch target address if the translation table walk was performed by the memory management circuitry for the prefetch target address. In response to a prediction that the fault condition would be identified for the prefetch target address, the prefetch circuitry suppresses the prefetch request and the memory management circuitry prevents the translation table walk being performed for the prefetch target address of the prefetch request.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a data map configured to manage validity of data written in the non-volatile memory. The data map includes a plurality of first fragment tables corresponding to a first hierarchy and a second fragment table corresponding to a second hierarchy higher than the first hierarchy. Each of the first fragment tables is used to manage the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second fragment table is used for each of the first fragment tables to manage reference destination information for referencing the first fragment table.

Abstract: A zone is loaded onto a first memory component of a storage system, wherein the zone comprises one or more regions of data blocks comprising a first plurality of logical block addresses (LBAs), and a snapshot of each of the one or more regions is stored on a second memory component of the storage system and is associated with a version identifier. A particular version identifier associated with a respective snapshot of a region is identified, and a set of journals stored on the second memory component are identified, wherein the set of journals comprise a second plurality of LBAs mapped to a second plurality of physical block addresses.

Abstract: Techniques for managing a disk involve acquiring a message for an access operation for a disk, the message including a first status code at an operating system level for the access operation. The techniques further involve acquiring a second status code at a disk hardware level for the access operation if it is determined that the first status code indicates that the access operation fails. The techniques further involve determining, according to a handling policy corresponding to the second status code, whether the disk will be marked as faulty. The techniques further involve managing the disk based on a count of failed access operations for the disk if it is determined that the disk is not marked as faulty. Such techniques may quickly determine a specific reason for a failure of a disk access operation, making it possible to solve problems quickly, save time and improve the user experience.

Abstract: Memory management apparatus comprises input circuitry to receive a translation request defining a first memory address within a first memory address space; prediction circuitry to generate a predicted second memory address within a second memory address space as a predicted translation of the first memory address, the predicted second memory address being a predetermined function of the first memory address; control circuitry to initiate processing of the predicted second memory address; translation and permission circuitry to perform an operation to generate a translated second memory address for the first memory address associated with permission information to indicate whether memory access is permitted to the translated second memory address; and output circuitry to provide the translated second memory address as a response to the translation request when the permission information indicates that access is permitted to the translated second memory address.

Abstract: A storage device is provided to comprise a memory device for storing data, a cache memory device including a first cache memory configured to cache certain data stored in the memory device and a second cache memory configured to store data evicted from the first cache memory, and a memory controller configured to receive a read request for first data from a host, evict second data from the first cache memory based on a reuse distance of the second data, store the second data in the second cache memory, load the first data to the first cache memory, and transmit the first data to the host.

Abstract: Techniques for managing a redundant array of independent disks (RAID) involve detecting an abnormality of a storage device in a RAID. The techniques further involve resetting the storage device in response to detecting the abnormality. The techniques further involve storing an address of a write operation for the RAID within a preset time period, so as to rebuild the RAID in the case that the storage device is recovered within the preset time period. Accordingly, temporary errors of the RAID can be efficiently handled, the number of downtime of the RAID caused by the storage device or the back end can be reduced, and computing resources and time required to rebuild the RAID can be significantly reduced.

Abstract: Storage devices are often configured to receive and process commands from a host-computing device. These commands can vary in size and priority with larger sizes of command data being processed by storage devices more frequently. As these sizes increase, more situations occur when newly received high priority commands are received and ready for processing, but must wait for the current data associated with a normal priority command to be fetched and/or processed. Traditionally, the high priority command must wait, no matter how long, until the currently underway normal priority command is fetched and/or completed. However, methods and system described herein allow for the interruption of normal priority data fetching prior to completion. In this way, lower latencies may be achieved as high priority commands are not required to wait for processing. The previously fetched data may be dumped and re-fetched again or may be stored until normal operations can resume.

Abstract: A computer system is provided, including a first data storage with a first retrieval latency, a second data storage with a second retrieval latency that is higher than the first retrieval latency, and a processor coupled to a memory that stores instructions, which cause the processor to store a series of recovery points of a data collection in the first data storage. For a current recovery point of the series of recovery points, the processor is further configured to compute a difference between an incremental changed block value of one or more prior recovery points and a number of memory blocks inherited from the one or more prior recovery points. The processor generates and outputs a storage transfer recommendation to store a subset of the one or more of the prior recovery points in the second data storage rather than the first data storage, based on the computed difference.

Abstract: A tiering service enables a client to custom specify service level agreements for data items to be tiered and automatically promotes and demotes the data items amongst a warm tier, a plurality of intermediate tiers, and a cold tier to ensure the service level agreement commitments are met. In some embodiments, a client specifies segmentation criteria for defining multiple segments of data items included in a data scope or table and assigns latency targets to the segments in order to define the service level agreement. Also, in some embodiments, a plurality of intermediate tiers are implemented on common underlying hardware by varying metadata management to implement intermediate tiers that have progressively increasing latencies.

Abstract: Systems and methods are disclosed for maintaining insertion policies of a lower-level cache. Techniques are described for selecting, based on metadata of an evicted data block received from an upper-level cache, an insertion policy out of the insertion policies. Then, determining, based on the selected insertion policy, whether to insert the data block into the lower-level cache. If it is determined to insert, the data block is inserted into the lower-level cache according to the selected insertion policy. Techniques for dynamically updating the insertion policies of the lower-level cache are also disclosed.