Abstract: A tiering service enables a client to custom specify service level agreements for data items to be tiered and automatically promotes and demotes the data items amongst a warm tier, a plurality of intermediate tiers, and a cold tier to ensure the service level agreement commitments are met. In some embodiments, a client specifies segmentation criteria for defining multiple segments of data items included in a data scope or table and assigns latency targets to the segments in order to define the service level agreement. Also, in some embodiments, a plurality of intermediate tiers are implemented on common underlying hardware by varying metadata management to implement intermediate tiers that have progressively increasing latencies.

Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.

Abstract: Coordinating a reclaiming of data storage space among processing nodes of a data storage system includes, by a first node in response to an event, performing local cleanup of first-node mapping data and issuing a request message to a second node, the request message identifying the data storage space to be reclaimed. The event may be a notification from a RAID component rebuilding a RAID volume. In response to the request message, the second node performs local cleanup of second-node mapping data and issues a completion message to the first node indicating that the second node has completed its part of the reclaiming of the data storage space. The first node responds to the completion message by marking the data storage space as being reclaimed and signaling to a source of the event that the data storage space is available for new use.

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

Abstract: Metadata logic switches selection of a metadata track from multiple available metadata tracks in a volatile cache to fill the selected metadata track in a metadata track selection interval with metadata entries as source tracks of a source volume are copied to a backup volume of a copy relationship. Destage logic destages to storage a deselected metadata track containing metadata entries generated in a prior metadata track selection interval, while the metadata logic continues to generate and fill additional metadata entries in the selected metadata track in a concurrent metadata track selection interval. Other features and aspects may be realized, depending upon the particular application.

Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: In some embodiments, a logging framework reserves space in an in-memory storage for a log entry upon receiving a first function call from an application being executed. Upon receiving a second function call from the application being executed, the framework writes the log entry in the space in the in-memory storage. Upon receiving a third function call from the application being executed, the framework selects a configuration for the application and comparing an indicator that is generated based on the executing of the application to the configuration. When the indicator meets a condition of the configuration, the framework copies the log entry from the space in the in-memory storage to a persistent storage space. The log entry is deleted from the space in the in-memory storage at a time after performing the comparing.

Abstract: A memory structure having 2m read ports allowing for concurrent access to n data entries can be constructed using three memory structures each having 2m?1 read ports. The three memory structures include two structures providing access to half of the n data entries, and a difference structure providing access to difference data between the halves of the n data entries. Each pair of the 2m ports is connected to a respective port of each of the 2m?1-port data structures, such that each port of the part can access data entries of a first half of the n data entries either by accessing the structure storing that half directly, or by accessing both the difference structure and the structure containing the second half to reconstruct the data entries of the first half, thus allowing for a pair of ports to concurrently access any of the stored data entries in parallel.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: Memory may be used more efficiently for snapshot metadata by reducing a size of a snapshot metadata object, for example, by removing free nodes from the snapshot metadata object. Removing free nodes may include consolidating free nodes into a single page of a snapshot metadata object and de-allocating the page from the memory allocated for the data structure. Consolidation of free nodes may be achieved by identifying active nodes in the single page, and swapping these active nodes with free nodes from other pages until the single page includes only free nodes. The nodes of the single page that were already free and the active nodes that were swapped with free nodes from another page may be designated for de-allocation. This designating may result in all nodes of the single page being designated for de-allocation, after which the single page of nodes may be de-allocated.

Abstract: A temperature control method is provided according to an exemplary embodiment of the invention. The method includes: sensing a temperature by a temperature sensor and obtaining a temperature value; performing a cooling-down operation based on a first cooling-down level and updating a level parameter to a first level parameter if the temperature value reaches a first threshold value; and performing the cooling-down operation based on a second cooling-down level according to the first level parameter and updating the level parameter to a second level parameter if the temperature value is not less than the first threshold value during a first time range after the cooling-down operation based on the first cooling-down level is performed, and a cooling-down ability of the cooling-down operation performed based on the second cooling-down level is higher than a cooling-down ability of the cooling-down operation performed based on the first cooling-down level.

Abstract: Systems and methods for object load introspection using guarded storage are disclosed. In embodiments, a computer-implemented method includes: determining objects of interest designated by a user; splitting a first subset of a predetermined memory heap into guarded regions based on a number of objects of interest; allocating each of the objects of interest to a respective one of the guarded regions and remaining objects to a second subset of the predetermined memory heap; executing a program; detecting one of the objects of interest is loaded from one of the guarded regions; generating a trap that transfers control of the executing the program to a signal handler, wherein the signal handler is designated to perform a user-defined task associated with the one of the objects of interest; and executing, by the signal handler of the computing device, the user-defined task.

Abstract: A technique for managing metadata in a data storage system includes receiving a set of data to be stored in a file system of the data storage system and calculating values of metadata blocks that the file system will use to organize the set of data in the file system. The technique aggregates values of the metadata blocks and sends them in a single, atomic transaction to a persistent cache. The transaction either succeeds, in which case the persistent cache stores the values of all of the metadata blocks, or it fails, in which case the persistent cache stores none of the values of the metadata blocks. Over time, the persistent cache flushes the values of the metadata blocks to a set of non-volatile storage devices that back the metadata blocks in the data storage system.

Abstract: A method, computer program product, and computer system for executing one of a reboot and a startup process. A write I/O may be received at a DRAM cache. Data may be written to at least two different NVMe devices. When the data of the write I/O is completely written to the at least two different NVMe devices, a response may be sent to a driver layer.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: An information processing system includes a first processor, a second processor, a first buffer circuit, a second buffer circuit, and a first memory, wherein the first processor is configured to generate a first read command specifying a first data stored in a first address area of the first memory, the second processor is configured to, based on the first read command, generate a second read command specifying a second data stored in a second address area of the first memory, the first buffer circuit is configured to store the first read command, the second buffer circuit is configured to store the second read command, the second processor is configured to execute the first read command stored in the first buffer circuit, and the second processor is configured to execute the second read command stored in the second buffer circuit when the first buffer circuit is in an empty state.

Abstract: A portion of a logical block address to physical block address (“L2P”) translation map may be identified. A last snapshot of the portion of the L2P translation map may be identified. One or more write operations may be determined, where the write operations are associated with logical block addresses of the portion of the L2P translation map. The write operations may have been performed after the last snapshot of the portion of the L2P translation map was stored. An address on the portion of the L2P translation map may be updated by a processing device based on the determined one or more write operations and the last snapshot of the portion of the L2P translation map.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.