Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A data service layer running on a storage director node generates a request to destage host data from a plurality of cache slots in a single back-end track. The destage request includes pointers to addresses of the cache slots and indicates an order in which the host application data in the cache slots is to be included in the back-end track. A back-end redundant array of independent drives (RAID) subsystem running on a drive adapter is responsive to the request to calculate parity information using the host application data in the cache slots. The back-end RAID subsystem assembles the single back-end track comprising the host application data from the plurality of cache slots of the request, and destages the single back-end track to a non-volatile drive in a single back-end input-output (IO) operation.

Abstract: Methods, systems, and computer storage media for providing log files using logging system operations in a logging system. The logging system operations support memory mapping log files and asynchronously managing file operations. The logging system operations support selectively mapping segments of log files during write operations. The logging operations also support performing file operations (e.g., closing, opening, deleting and serializing files) advantageously as background processes. Selective memory mapping specifically includes incrementally mapping new segments of a log file up to a predetermined log file size limit. The logging operations support processing spare files using spare file memory mapping. A spare file replaces an existing log file to continue writing logging data using the spare file.

Abstract: A controller includes: a command queue scheduler for queuing normal commands, and providing a priority order to a suspend command, when the suspend command is input; a data input/output component for outputting data in response to a data output signal output the command queue scheduler, and stopping the output of the data in response to a data output stop signal; and a data monitor for dividing data input to the data input/output component into a plurality of data groups, and monitoring information of a data group including data currently output from the data input/output component. The data input/output component outputs data up to the currently output data included in the data group and then stops the output of the data, in response to the data output stop signal. The command queue scheduler outputs the suspend command, when the output of the data group is stopped.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A method for managing HDD expanders in a cluster storage system is provided. The method according to one embodiment is implemented by each of the HDD expanders, and includes: indicating a device type of HDD expander to a parent node thereof when a device-type request originates from the parent node; and indicating a device type not of HDD expander to the parent node otherwise. The method according to another embodiment is implemented by each HDD expander connected indirectly to a root node, and includes: indicating a device type not of HDD expander to the root node when a device-type request originates from the root node; and indicating a device type of HDD expander to a node that initiates the device-type request otherwise.

Abstract: Systems and methods for dynamic and automatic data storage scheme switching in a distributed data storage system. A machine learning-based policy for computing probable future content item access patterns based on historical content item access patterns is employed to dynamically and automatically switch the storage of content items (e.g., files, digital data, photos, text, audio, video, streaming content, cloud documents, etc.) between different data storage schemes. The different data storage schemes may have different data storage cost and different data access cost characteristics. For example, the different data storage schemes may encompass different types of data storage devices, different data compression schemes, and/or different data redundancy schemes.

Abstract: A method for managing memory addresses in a memory subsystem is described. The method includes determining that a chunk of logical addresses is sequentially written such that a set of physical addresses mapped to corresponding logical addresses in the chunk are sequential. Thereafter, the memory subsystem updates an entry in a sequential write table for the chunk to indicate that the chunk was sequentially written and a compressed logical-to-physical (L2P) table based on (1) the sequential write table and (2) a full L2P table. The full L2P table includes a set of full L2P entries and each entry corresponds to a logical address in the chunk and references a physical address in the set of physical addresses. The compressed L2P table includes an entry that references a first physical address of the first set of physical addresses that is also referenced by an entry in the L2P table.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A memory system include: a plurality of first memory devices each coupled to a first channel and including a plurality of first memory blocks; a plurality of second memory devices each coupled to a second channel and including a plurality of second memory blocks; a first access controller suitable for controlling an access to the first memory blocks; a second access controller suitable for controlling an access to the second memory blocks; and a bad block controller suitable for: selecting one between the first and second access controllers by comparing bad physical addresses corresponding to bad blocks included in each of the first and second memory devices with first and second physical addresses respectively corresponding to the first and second memory blocks, and transferring one of the first and second physical addresses and substitute physical address that replace the bad physical addresses.

Abstract: In a data restoration method and apparatus, after a data restoration request is received, all metadata corresponding to each deduplication index is determined based on a deduplication index corresponding to metadata of each data slice in backup data. Then, the data slice is stored to a distribution location described in each piece of metadata corresponding to the deduplication index.

Abstract: Provided herein may be a storage device and a method of operating the same. The storage device may include: a memory device including a memory cell array and a page buffer; and a memory controller including a write buffer. The memory device may further include a page buffer state determiner configured to generate a page buffer state signal based on a state of the page buffer and provide the page buffer state signal to the memory controller. The memory controller may further include a write operation controller configured to provide data provided from a host to either the page buffer or the write buffer in response to the page buffer state signal, and control the memory device to program data stored in the page buffer to the memory cell array based on the state of the write buffer.

Abstract: A storage cluster includes a plurality of storage nodes. Each of the plurality of storage nodes includes nonvolatile solid-state memory and each of the plurality of storage nodes is configured to cooperate with others of the plurality of storage nodes having differing storage capacities in applying erasure coding. The plurality of storage nodes are configured to distribute the user data and metadata throughout the plurality of storage nodes.

Abstract: Techniques for managing disks involve: in response to a number of a plurality of disks to be partitioned being greater than a predetermined number of disks in a disk set, determining a plurality of candidate combinations of disk sets from the plurality of disks. The techniques further involve selecting a target combination from the plurality of candidate combinations, a first disk set of the target combination comprising at least a first subset corresponding to a first disk array, a second disk set of the target combination comprising at least a second subset corresponding to a second disk array, a number of disks in the first subset and a number of disks in the second subset being both equal to a first number and the disks in the first subset being different from the disks in the second subset. Accordingly, such techniques improve the storage efficiency of the disk array.

Abstract: A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata.

Abstract: First and second-level caches are provided. Cache control circuitry performs a first-level cache lookup of the first-level cache based on a lookup address, to determine whether the first-level cache stores valid cached data corresponding to the lookup address. When lookup hint information associated with the lookup address is available, the cache control circuitry determines based on the lookup hint information whether to activate or deactivate a second-level cache lookup of the second-level cache. The lookup hint information is indicative of whether the second-level cache is predicted to store valid cached data associated with the lookup address. When the second-level cache lookup is activated, the second-level cache lookup of the second-level cache is performed based on the lookup address to determine whether the second-level cache stores valid cached data corresponding to the lookup address.

Abstract: Example embodiments of the present invention relate and a method and an apparatus for double hashing. The method including receiving a hash signature, including a short hash handle, for a data block. The method then includes determining a bucket with which the hash signature should be associated and associating the hash signature with the bucket.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.