Patents Examined by Stephen Bradley
  • Patent number: 10256326
    Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 10242975
    Abstract: A flexible display apparatus includes: a flexible substrate including a first surface and a second surface which is opposite to the first surface; a first display unit which displays an image with light and is on the first surface of the flexible substrate, the first display unit including a transmission area at which light from the flexible substrate passes through the first display unit to outside the first display unit; and a second display unit which displays an image with light and is on the second surface of the flexible substrate, the second display unit disposed corresponding to the transmission area of the first display unit on the first surface of the flexible substrate.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 26, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Mugyeom Kim
  • Patent number: 10232471
    Abstract: The invention relates to a method for dividing a composite into a plurality of semiconductor chips along a dividing pattern. A composite, which comprises a substrate, a semiconductor layer sequence, and a functional layer, is provided. Separating trenches are formed in the substrate along the dividing pattern. The functional layer is cut through along the dividing pattern by means of coherent radiation. Each divided semiconductor chip has part of the semiconductor layer sequence, part of the substrate, and part of the functional layer. The invention further relates to a semiconductor chip.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 19, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Mathias Kaempf
  • Patent number: 10224466
    Abstract: Embodiments of the invention include a semiconductor light emitting device, a first wavelength converting member disposed on a top surface of the semiconductor light emitting device, and a second wavelength converting member disposed on a side surface of the semiconductor light emitting device. The first and second wavelength converting members include different wavelength converting materials.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 5, 2019
    Assignee: Lumileds LLC
    Inventors: Kenneth Vampola, Han Ho Choi
  • Patent number: 10217684
    Abstract: A resin molding includes a semiconductor element, a circuit board, and a resin. A conductor connected to the semiconductor element is formed on the circuit board. The resin is adhered and integrated with the circuit board. A resin leakage suppression layer including a material having a higher thermal conductivity than that of a material forming a surface layer of the circuit board is provided in an edge region extending along a portion adhered to the resin in the circuit board and extending along at least one-side side surface of the resin.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: February 26, 2019
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Tsubasa Watanabe, Tsutomu Kono, Takayuki Yogo, Hiroaki Hoshika
  • Patent number: 10205124
    Abstract: An organic light-emitting display apparatus includes a substrate, a pixel electrode disposed on the substrate, a pixel-defining layer (PDL) disposed on the pixel electrode and having an opening exposing at least a part of the pixel electrode, an intermediate layer, a protective layer, and an opposite electrode be disposed on the PDL and having an opening exposing at least a part of the protective layer, wherein the opposite electrode is electrically connected to the protective layer. The intermediate layer may include a central portion disposed on the pixel electrode, an edge portion that extends from the central portion and contacts the PDL, at least one common layer, and an organic emission layer. The protective layer may include a central portion disposed on the central portion of the intermediate layer and an edge portion that extends from the central portion of the protective layer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: February 12, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jungsun Park, Hyunsung Bang, Duckjung Lee, Jiyoung Choung, Arong Kim
  • Patent number: 10197877
    Abstract: An array substrate includes multiple pattern layers disposed in a display region and a test unit disposed in a non-display region, the test unit includes at least one of a test component and a test transistor. The test component includes a test block pattern and a test line pattern; the test block pattern is disposed in the same layer as one layer of the multiple pattern layers, the test line pattern is disposed in the same layer as one layer of the multiple pattern layers, and the test block pattern and the test line pattern are disposed in different layers; the orthographic projection of the test line pattern on the array substrate surrounds the periphery of the orthographic projection of the test block pattern on the array substrate; and the test block pattern or the test line pattern is connected to the test transistor.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 5, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yucheng Chan, Shuai Zhang
  • Patent number: 10197831
    Abstract: A flexible TFT backplane includes, a flexible substrate, a first set of address line contacts associated with the substrate, and a second set of address line contacts associated with the substrate. The first set of address line contacts and the second set of address line contacts are located at opposite sides of the substrate from each other, defining a vertical direction. A first set of address lines designed to run in one of the vertical direction and a diagonal or non-vertical direction with respect to the defined vertical direction, with the first set of address lines connected to the first set of address line contacts. Also provided is a second set of address lines designed to run in one of a diagonal or non-vertical direction with respect to the defined vertical direction, and a combination of diagonal and horizontal directions with respect to the vertical direction, with the second set of address lines connected to the second set of address line contacts.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: February 5, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Robert A. Street, Julie A. Bert, John C. Knights
  • Patent number: 10197520
    Abstract: Disclosed is an integrated circuit comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising a first metal portion (20) and a second metal portion (21); a passivation stack (24, 26, 28) covering the metallization stack; a gas sensor including a sensing material portion (32, 74) on the passivation stack; a first conductive portion (38) extending through the passivation stack connecting a first region of the sensing material portion to the first metal portion; and a second conductive portion (40) extending through the passivation stack connecting a second region of the sensing material portion to the second metal portion. A method of manufacturing such an IC is also disclosed.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: February 5, 2019
    Assignee: ams International AG
    Inventors: Matthias Merz, Aurelie Humbert, Roel Daamen, David Tio Castro
  • Patent number: 10186560
    Abstract: Provided are an organic light-emitting display apparatus and a method of manufacturing the same. The organic light-emitting display apparatus includes: a substrate on which a display area is defined, wherein an image is displayed on the display area; a thin film transistor arranged on the display area of the substrate; a via-insulating layer covering the thin film transistor; a pixel electrode arranged on the via-insulating layer and electrically connected to the thin film transistor; a pixel-defining layer including an opening exposing a central portion of the pixel electrode, and covering an edge of the pixel electrode; a counter electrode facing the pixel electrode; an organic emission layer arranged between the pixel electrode and the counter electrode; a wire arranged on the via-insulating layer to be spaced apart from the pixel electrode and including a spacer area and a non-spacer area; and a spacer arranged on the spacer area.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 22, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jungkyu Lee, Taehyun Kim, Seungmin Lee, Sangho Park, Joosun Yoon
  • Patent number: 10186544
    Abstract: An image sensor includes a semiconductor substrate and a photoelectric conversion device on the semiconductor substrate and including a plurality of pixel electrodes, a light absorption layer, and a common electrode. The plurality of pixel electrodes may include a first pixel electrode and a second pixel electrode. The photoelectric conversion device may include a first photoelectric conversion region defined in an overlapping region with the first pixel electrode, the light absorption layer, and the common electrode, and a second photoelectric conversion region defined in an overlapping region with the second pixel electrode, the light absorption layer, and the common electrode. Sensitivity of the first photoelectric conversion region may be higher than sensitivity of the second photoelectric conversion region. An electronic device may include the image sensor.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gae Hwang Lee, Kwang Hee Lee, Kyu Sik Kim, Sung Young Yun, Dong-Seok Leem, Yong Wan Jin
  • Patent number: 10177071
    Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: January 8, 2019
    Inventor: Mattias E. Dahlstrom
  • Patent number: 10170366
    Abstract: A semiconductor device is provided as follows. Active fins protrude from a substrate, extending in a first direction. A first device isolation layer is disposed at a first side of the active fins. A second device isolation layer is disposed at a second side of the active fins. A top surface of the second device isolation layer is higher than a top surface of the first device isolation layer and the second side is opposite to the first side. A normal gate extends across the active fins in a second direction crossing the first direction. A first dummy gate extends across the active fins and the first device isolation layer in the second direction. A second dummy gate extends across the second device isolation layer in the second direction.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: January 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gun You, Jeong-Hyo Lee
  • Patent number: 10170438
    Abstract: A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential. The charge distribution structure is capacitively coupled to a first terminal of the semiconductor device. The static discharge system removes charge that accumulates on at least a subset of the conductors. The static discharge system removes the charge that accumulates on the subset of conductors when the semiconductor device is in a first state while allowing charge to accumulate on the subset of conductors when the semiconductor device is in a second state.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: January 1, 2019
    Assignee: POWER INTEGRATIONS. INC.
    Inventors: Alexey Kudymov, Jamal Ramdani
  • Patent number: 10163728
    Abstract: In manufacturing a semiconductor device, a stack of first and second semiconductor layers are formed. A fin structure is formed by patterning the first and second semiconductor layers. A cover layer is formed on a bottom part of the fin structure so as to cover side walls of the bottom portion of the fin structure and a bottom part of side walls of the upper portion of the fin structure. An insulating layer is formed so that the fin structure is embedded in the insulating layer. A part of the upper portion is removed so that an opening is formed in the insulating layer. A third semiconductor layer is formed in the opening on the remaining layer of the second semiconductor layer. The insulating layer is recessed so that a part of the third semiconductor layer is exposed from the insulating layer, and a gate structure is formed.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chen Wang, Kai-Hsuan Lee, Sai-Hooi Yeong, Chia-Ta Yu
  • Patent number: 10157960
    Abstract: A light-emitting device includes a substrate; a light-emitting unit formed on the substrate, comprising a first conductivity type semiconductor; a second conductivity type semiconductor; an active layer formed between the first and the second conductivity type semiconductors; and an exposed region formed in the light-emitting unit, exposing the first conductivity type semiconductor; a first electrode extending layer formed on the first conductivity type semiconductor in the exposed region; a second electrode extending layer formed on the second conductivity type semiconductor; a transparent insulator, formed on the light-emitting unit and filled in the exposed region; a first electrode formed on the transparent insulator; and a plurality of conductive channel layers formed in the transparent insulator; wherein one of the plurality of conductive channel layers connects the first electrode and one of the first and the second electrode extending layers.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: December 18, 2018
    Assignee: EPISKY CORPORATION (XIAMEM) LTD
    Inventors: Che-Shiung Wu, Chan-Yang Lu, Jian-Ke Liu, Mei-Ying Bai, Cong-Hui Lin, Xiao-Qiang Zeng
  • Patent number: 10155659
    Abstract: A vacuum sealed MEMS and CMOS package and a process for making the same may include a capping wafer having a surface with a plurality of first cavities, a first device having a first surface with a second plurality of second cavities, a hermetic seal between the first surface of the first device and the surface of the capping wafer, and a second device having a first surface bonded to a second surface of the first device. The second device is a CMOS device with conductive through vias connecting the first device to a second surface of the second device, and conductive bumps on the second surface of the second device. Conductive bumps connect to the conductive through vias and wherein a plurality of conductive bumps connect to the second device. The hermetic seal forms a plurality of micro chambers between the capping wafer and the first device.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Yi-Chuan Teng, Hung-Chia Tsai, Chia-Hua Chu
  • Patent number: 10157748
    Abstract: A finFET semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first fin formed in a first semiconducting layer, a second fin formed in a second semiconductor layer, and an insulating layer disposed between the first fin and the second fin. The first fin, the second fin, and the insulating layer form a stacked structure above a substrate. Sidewalls of the first fin are substantially more vertical than sidewalls of the second fin.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Ka-Hing Fung
  • Patent number: 10147848
    Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include a n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary. A n-type contact region can be located over a second portion of the surface of the n-type semiconductor contact layer entirely distinct from the first portion, and be at least partially defined by the mesa boundary. A first n-type metallic contact layer can be located over at least a portion of the n-type contact region in proximity of the mesa boundary, where the first n-type metallic contact layer forms an ohmic contact with the n-type semiconductor layer. A second n-type metallic contact layer can be located over a second portion of the n-type contact region, where the second n-type metallic contact layer is formed of a reflective metallic material.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 4, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Mikhail Gaevski, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur
  • Patent number: 10147744
    Abstract: An array substrate, a method of manufacturing the same, and a display device are provided. In the array substrate of the present disclosure, the gate cutout is formed in the area where the gate line intersects the data line. The array substrate can reduce the coupling capacitance between the data line and the gate line. When the gate cutout extends beyond the area between the first thin film transistor and the second thin film transistor, the mutual interference between two thin film transistors of each pixel region can be further reduced.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: December 4, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongfei Cheng, Jianbo Xian, Pan Li, Xueguang Hao