Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and an interconnect structure formed over the substrate. The interconnect structure includes a first dielectric layer formed over the substrate, and a first graphene layer formed in and on the first dielectric layer. The first graphene layer includes a first portion in the first dielectric layer and a second portion on the first dielectric layer and a first insulating layer formed over the first portion of the first graphene layer.

Abstract: A method of producing an optoelectronic component includes providing a carrier having a carrier surface, a first lateral section of the carrier surface being raised relative to a second lateral section of the carrier surface; arranging an optoelectronic semiconductor chip having a first surface and a second surface on the carrier surface, wherein the first surface faces toward the carrier surface; and forming a molded body having an upper side facing toward the carrier surface and a lower side opposite the upper side, the semiconductor chip being at least partially embedded in the molded body.

Abstract: An insulating liner layer has an extra-pixel removal region located outside a pixel region in a region of a vertical angle of at least one of four corners of the pixel region and having the insulating liner layer removed therefrom.

Abstract: Improvements are achieved in the characteristics of a nonvolatile memory. In plan view, in a first isolation region which is an element isolation region surrounded by a first fin, a second fin, a memory gate electrode, and another memory gate electrode, a protruding portion is provided. In a second isolation region which is the element isolation region overlapping the memory gate electrode in plan view, a second isolation portion is provided to set the protruding portion higher in level than the second isolation portion. In a step of lowering a top surface of the element isolation region located between the first and second fins, a part of the element isolation region located between the first and second fins is covered with a mask film to form the protruding portion. Using the protruding portion, a short circuit between the memory gate electrodes due to a gate residue is prevented.

Abstract: The purpose of the invention is to eliminate an abnormal current at an edge of a semiconductor layer in a thin film transistor. The invention is: A thin film transistor having a semiconductor layer comprising: a channel, a drain and a source are formed in the semiconductor layer, the channel has a channel length and a channel width, a LDD (Light Doped Drain) is formed between the channel and the drain or between the channel and the source, the LDD including a first LDD area, which is formed at a center of the LDD in the direction of the channel width, and a second LDD area, which is formed at an edge of the LDD in the direction of the channel width, wherein a width of the second LDD area in the channel length direction is bigger than a width of the first LDD area in the channel length direction.

Abstract: An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO2) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NO2 layer formed on the graphene channel, a high-k dielectric formed over the adsorbed NO2 layer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NO2 layer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (Vg) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.

Abstract: A semiconductor chip package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, a chip pad, and electrical contact elements connected with the semiconductor chip and extending outwardly. The encapsulation body has six side faces and the electrical contact elements extend exclusively through two opposing side faces which have the smallest surface areas from all the side faces. The semiconductor chip is disposed on the chip pad, and a main face of the chip pad remote from the semiconductor chip is at least partially exposed to the outside.

Abstract: A bipolar transistor comprises a semiconductor body including a collector region and a base region arranged on top of the collector region. The base region has a first crystalline structure and is at least partly doped with dopants of a first doping type. The collector region is laterally enclosed by a trench isolation and is doped with dopants of a second doping type. The transistor further comprises a conductive base contact layer laterally enclosing the base region which is doped with dopants of the first doping type. The base contact layer comprises a part with the first crystalline structure and a part with a second crystalline structure, wherein the part with the second crystalline structure laterally encloses the part with the first crystalline structure. The transistor further comprises an emitter region arranged on the base region.

Abstract: Semiconductor devices are provided which have MIM (metal-insulator-metal) capacitor structures that are integrated within air gaps of on-chip interconnect structures, as well as methods for integrating MIM capacitor formation as part of an air gap process flow for fabricating on-chip interconnect structures. For example, a semiconductor device includes a dielectric layer with a first pattern of metal lines and second pattern of metal lines. Air gaps are disposed in spaces between the metal lines. Portions of the spaces between the metal lines of the first pattern of metal lines include a conformal layer of insulating material disposed on sidewalls of the metal lines and metallic material that fills the spaces between the metal lines. The first pattern of metal lines comprises a first capacitor electrode, the metallic fill material comprises a second capacitor electrode, and the conformal layer of insulating material comprises an insulating layer of a MIM capacitor structure.

Abstract: A method for making a CMOS device includes: providing a substrate with a semiconductor layer and a photoresist layer; irradiating the photoresist layer through a mask to obtain a first photoresist and a second photoresist having a height smaller than that of the first photoresist; first implanting ions to the semiconductor layer; ashing the first and second photoresists to expose a first region of the semiconductor layer and removing the second photoresist to expose a second region of the semiconductor layer; secondly implanting ions to the semiconductor layer; removing the first photoresist to expose a third region of the semiconductor layer surrounded by the second region; forming a third photoresist and a fourth photoresist on the semiconductor layer; etching the semiconductor layer to remove the semiconductor layer not covered by the third and fourth photoresists; removing the third and fourth photoresists; and thirdly implanting ions to the semiconductor layer.

Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region. The metal stud bumps include a portion that is partially embedded in a solder joint.

Abstract: Disclosed herein are methods of forming non-volatile storage. An opening may be etched through a stack of two alternating materials to a semiconductor substrate. A silicon nitride film may be formed on a vertical sidewall of the opening. The semiconductor substrate may be cleaned to remove oxide from the semiconductor substrate. The silicon nitride film protects the materials in the stack while cleaning the semiconductor substrate. The silicon nitride film may be converted to an oxide after cleaning the semiconductor substrate. A semiconductor region may be formed in contact with the cleaned semiconductor substrate. A memory cell film may be formed over the oxide in the opening. Control gates may be formed by replacing one of the materials in the stack with a conductive material. The oxide may serve as a blocking layer between the control gates and charge storage regions in the memory cell film.

Abstract: A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function.

Abstract: This hetero-junction bipolar transistor includes a first n-type GaN layer, an AlxGa1-xN layer (0.1?x?0.5), an undoped GaN layer having a thickness of not less than 20 nm, a Mg-doped p-type GaN layer having a thickness of not less than 100 nm, and a second n-type GaN layer which are sequentially stacked. The first n-type GaN layer and the AlxGa1-xN layer form an emitter, the undoped GaN layer and the p-type GaN layer form a base, and the second n-type GaN layer forms a collector. During non-operation, two-dimensional hole gas is formed in a part of the undoped GaN layer near the hetero interface between the AlxGa1-xN layer and the undoped GaN layer. When the thickness of the p-type GaN layer is b [nm], the hole concentration of the p-type GaN layer is p [cm?3], and the concentration of the two-dimensional hole gas is Ps [cm?2], p×b×10?7+Ps?1×1013 [cm?2] is satisfied.

Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN-junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor substrate; forming a first dielectric layer covering a side surface of the metal gate structure on the semiconductor substrate; forming a cap layer on the metal gate structure; etching a top portion of the first dielectric layer using the cap layer as an etching mask; forming a protective sidewall spacer on a side surface of the cap layer and a side surface of a portion of the first dielectric layer under the cap layer; forming a second dielectric layer to cover the cap layer, the protective sidewall spacer and a top surface of the etched first dielectric layer; forming at least a first through-hole in the second dielectric layer; and forming a first conductive via in the first through-hole.

Abstract: The invention provides an OLED display panel and the production process thereof, which relates to the technical field of display, may improve the surface flatness and the water-oxygen permeation resistance of the flexible base substrate, improve the light output ratio of the display panel, and may control the center wavelength of the electroluminescence spectrum.

Abstract: Embodiments of the invention include a semiconductor light emitting diode attached to a substrate. A first region of wavelength converting material is disposed on the substrate. The wavelength converting material is configured to absorb light emitted by the semiconductor light emitting diode and emit light at a different wavelength. In the first region, the wavelength converting material coats an entire surface of the substrate. The substrate is disposed proximate a bottom surface of an optical cavity. A second region of wavelength converting material is disposed proximate a top surface of the optical cavity.

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

Abstract: Methods for forming semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a hard mask structure over a substrate and etching the substrate through an opening of the hard mask structure to form a trench. The method for manufacturing a semiconductor structure further includes removing a portion of the hard mask structure to enlarge the opening and forming an epitaxial-growth structure in the trench and the opening.