Abstract: A system, method and data structure for error correction for use in the transmission of content data distribution networks uses a compressed memory, for example a bitmap, to identify portions of transmitted content data files where transmission errors have occurred. The error memory, is used to generate an error status report that is returned to a transmission controller via a low bandwidth back channel, for example the Internet. The information in multiple error status reports is aggregated by the control system of the transmitter and used to re-transmit those portions of previously transmitted content data files that were not properly received due to error. By re-transmitting only the data packets of the transmitted content data files that contain errors, overall transmission speed is increased and bandwidth usage is conserved.

Abstract: Techniques to issue a single application programming interface (API) to request both data copy and CRC validation operations. In some embodiments, a receiver of the API may observe which logic (e.g., software or hardware and/or combinations of software and hardware) is available to execute instructions for data copy and CRC validation operations.

Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part for coding an input multiplexed code string to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string , for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string to assemble an output code string.

Abstract: An interleaver address generator is provided with pruning avoidance technology. It anticipates the points in time when incorrect addresses are computed by an IAG, and bypasses these events. It produces a stream of valid, contiguous addresses for all specified code block sizes. A single address computation engine firstly ‘trains’ itself about violating generated addresses (for a related block size) during the initial H1 half-iteration of decoder operation, and then produces a continuous, correct stream of addresses as required by the turbo decoder. Thus regions of pruned addresses are determined, and then training is performed only in these regions. Thus, computation and population of a pruned event table is determined in less than 1/10 the time required to do a conventional style full training. The resulting pruned event table is compressed down to 256 bits.

Abstract: A write-back cache has error-correction code (ECC) fields storing ECC bits for cache lines. Clean cache lines are re-fetched from memory when an ECC error is detected. Dirty cache lines are corrected using the ECC bits or signal an uncorrectable error. The type of ECC code stored is different for clean and dirty lines. Clean lines use an error-detection code that can detect longer multi-bit errors than the error correction code used by dirty lines. Dirty lines use a correction code that can correct a bit error in the dirty line, while the detection code for clean lines may not be able to correct any errors. Dirty lines' ECC is optimized for correction while clean lines' ECC is optimized for detection. A single-error-correction, double-error-detection (SECDED) code may be used for dirty lines while a triple-error-detection code is used for clean lines.

Abstract: When received data is decoded, a CPU stores a value “1”, which is included in a vector obtained by multiplying the received data by a parity check matrix, as the number of parity errors and also stores hard-decision result information corresponding to the number of parity errors in an output candidate information storage area. If the CPU determines that the received data is uncorrectable after the received data is decoded a given number of times, it reads hard-decision result information corresponding to the smallest number of parity errors, which are included in the number of parity errors stored in the output candidate information storage area and outputs it as a decoding result.

Abstract: Methods, circuits, architectures, and systems for error detection in transmitted data. The method generally includes the steps of (a) performing an error checking calculation on the transmitted data and appended error checking code; (b) determining the calculated error checking code state; and (c) if it has a predetermined state, indicating that there is no error in the transmitted data. The circuitry generally comprises (1) an error checking code calculation circuit configured to calculate error checking code on the transmitted data and the appended error checking code; (2) a vector selector configured to select one of a plurality of error checking vectors; and (3) a logic circuit configured to determine the calculated error checking code state and, if it has a predetermined state, indicate that there is no error in the transmitted data. The software generally includes a set of instructions configured to implement or carry out the present method.

Abstract: A method of retransmitting a data frame and a network apparatus using the method are provided. In the method performed in a wireless network, a first network apparatus transmits a data frame requesting a response frame. A second network apparatus determines a type of response frame according to a reception mode of the data frame. The second network apparatus transmits the determined type of response frame to the first network apparatus. The first network apparatus retransmits the data frame according to the type of the response frame transmitted to the first network apparatus.

Abstract: Data communication over a block-coherent channel in a communication system is described. Low-complexity demodulation techniques that allow good performance are described. A dwell, e.g., a set of block coherent symbols transmitted including a known symbol, e.g., a pseudo pilot symbol, are received, demodulated and decoded by a joint decoder/demodulator employing soft inputs, soft outputs, and interleaving of messages. Low-complexity SISO demodulator is suitable for processing pseudo-pilot modulated information corresponding to each of one or more dwells. The low-complexity method achieves good performance when turbo equalization is used. Some decoding and demodulation embodiments include independent phase estimates and updated independent phase estimates following the extrinsic principle to generate soft symbol values and soft bits.

Abstract: An integrated circuit that accesses memory from data lines in multiple word increments having distributed error correction coding circuitry is described. The data lines are selectively coupled to a portion of the memory for a read of data stored in the portion of the memory. The read includes providing in parallel in the multiple word increments the data stored in the portion of the memory. The data lines are selectively tapped to provide the data from the read to flow in parallel in a first direction and in a second direction. The first direction provides the data to the data registers, and the second direction provides the data to be propagated in an error checking matrix of the distributed error correction coding circuitry.

Abstract: A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.

Abstract: In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part for coding an input multiplexed code string to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string to assemble an output code string.

Abstract: One or more methods and systems of effectively retrieving data stored in a media of a storage device are presented. The one or more methods and systems are implemented by way of correcting and detecting errors using a multi-stage decoding process. In one embodiment, the storage device comprises a magnetic hard drive. In one embodiment, the system and method applies an encoding/decoding technique that allows error correction and detection to be performed over a number of successive decode stages or processing stages. Use of the system and method increases the maximum number of symbol errors that may be corrected in an encoded codeword, providing an improvement in data recovery.

Abstract: A digital data transmission error checking method and system is proposed, which is designed for use with a data source unit and a data reception unit for providing a error checking function, and which is characterized by the use of an improved checksum algorithm that initially sets a checksum variable to a fixed value and then repetitively increases the value of the checksum value by adding the value of each data unit in the original digital data stream plus the resulted value of an exclusive-OR operation on the previous checksum value and the index number of the current data unit in the original digital data stream. This feature allows the reception side to determine whether there are erroneous bits in the received data stream even if the sequential order of the bytes in the original digital data stream is mistakenly disordered.

Abstract: Methods and apparatus to extract audio codes are disclosed. An example method includes receiving signals on a plurality of channels and ranking the signals based on at least one characteristic of the signals. A first channel from the plurality of channels is selected based upon the ranking of the signals. The example method further include determining whether a first signal on the first channel includes at least one code and extracting the at least one code from the first signal when the first signal includes the at least one code.

Abstract: An apparatus, a carrier medium storing instructions to implement a method, and a method in a node of a wireless network able to receive packets that exactly or substantially conform to a wireless network standard according to which each packet includes a header having bits that have respective correct values in the case that the packet exactly conforms to the standard. The method includes receiving a start-of-packet (SOP) trigger that indicates that a packet may have been received, checking one or more bits in the header to determine whether or not they have their respective correct values, and continuing to process the packet in the case that the checking indicates that the checked bits have their respective correct values. In one implementation, the header includes a first field modulated at a known rate that has one or more reserved bit locations, and a second field modulated at a data rate indicated in the first field.

Abstract: A detection and recovery mechanism is herein disclosed for soft errors corrupting TLB data. The mechanism works with a hardware page walker (HPW) and instruction steering control mechanisms in a processor to provide soft error recovery in the TLB arrays and latches. Through use of the disclosed detection and recovery mechanism, efficient and robust protection from silent data corruption is provided without requiring more expensive built-in redundancy.

Abstract: An encoder uses output symbol subsymbols to effect or control a tradeoff of computational effort and overhead efficiency to, for example, greatly reduce computational effort for the cost of a small amount of overhead efficiency. An encoder reads an ordered plurality of input symbols, comprising an input file or input stream, and produces output subsymbol. The ordered plurality of input symbols are each selected from an input alphabet, and the generated output subsymbols comprise selections among an output subsymbol alphabet. An output subsymbol is generated using a function evaluator applied to subsymbols of the input symbols. The encoder may be called one or more times, each time producing an output subsymbol. Output subsymbols can then be assembled into output symbols and transmitted to their destination.

Abstract: An electronic device under test (DUT) responds to a digital input signal by generating a digital DUT output signal conveying a repetitive digital signal pattern. An apparatus for measuring various characteristics of the DUT output signal includes a trigger generator for generating a series of trigger signal edges in response to selected DUT output signal edges occurring during separate repetitions of the digital signal pattern. The trigger generator can be configured to generate each trigger signal edge in response to the same or a different edge of the digital signal pattern. The apparatus determines when a DUT output signal edge occurs by determining when the DUT output signal rises above or falls below adjustable reference voltages. The apparatus alternatively responds to each trigger signal edge by measuring a period between two different edges of the digital signal pattern and or by repetitively sampling the DUT output signal to determine its state.

Abstract: Efficient design to implement LDPC decoder. The efficient design presented herein provides for a solution that is much easier, smaller, and has less complexity than other possible solutions. The use of a ping-pong memory structure (or pseudo-dual port memory structure) in conjunction with a metric generator near the decoder's front end allows parallel bit/check node processing. An intelligently operating barrel shifter operates with a message passing memory that is operable to store updated edges messages with respect to check nodes as well as updated edges messages with respect to bit nodes. Using an efficient addressing scheme allows the same memory structure to store the two types of edges messages with respect to bit nodes: (1) corresponding to information bits and (2) corresponding to parity bits. In addition, an intelligently designed hardware macro block may be instantiated a number of times into the decoder design to support ever greater design efficiency.