Abstract: Prediction circuitry predicts a number of iterations of a fetching process to be performed to control fetching of data/instructions for processing operations that are predicted to be performed by processing circuitry. The processing circuitry can tolerate performing unnecessary iterations of the fetching process following an over-prediction of the number of iterations. In response to the processing circuitry resolving an actual number of iterations, the prediction circuitry adjusts the prediction state information used to predict the number of iterations, based on whether a first predicted number of iterations, predicted based on a first iteration prediction parameter, provides a good prediction (when the first predicted number of iterations is in a range i_cnt to i_cnt+N, where i_cnt is the actual number of iterations and N?1), or a misprediction (when the first predicted number of iterations is outside the range i_cnt to i_cnt+N).

Abstract: A network device includes one or more ports, match-action circuitry, and an action processor. The one or more ports are to exchange packets between the network device and a network. The match-action circuitry is to match at least some of the packets to one or more rules so as to set respective actions to be performed, at least one of the actions including a programmable action. The instruction processor is to perform the programmable action by running user-programmable software code. The instruction processor includes architectural registers, one or more of the architectural registers being accessible by the match-action circuitry, and the match-action circuitry is to write into the architectural registers information for performing the programmable action.

Abstract: Apparatuses, systems, and techniques to determine a matrix multiplication algorithm for a matrix multiplication operation. In at least one embodiment, a matrix multiplication operation is analyzed to determine an appropriate matrix multiplication algorithm to perform the matrix multiplication algorithm.

Abstract: An addition mask value generator is provided. A first operation circuit is configured to obtain first intermediate data according to first output mask value and fourth output mask value. A second operation circuit is configured to obtain the addition output mask value of a first mask group according to first intermediate data and fourth input mask value. A third operation circuit is configured to obtain second intermediate data according to second output mask value and third output mask value. A fourth operation circuit is configured to obtain the addition output mask value of a second mask group according to second intermediate data and second input mask value. The first and second addition input mask values of first mask group are first and second input mask values. The first and second addition input mask values of second mask group are third input mask value and first intermediate data.

Abstract: Systems, methods, and computer-readable media are provided for variable precision first in, first out (FIFO) buffers (VPFB) that dynamically changes the amount of data to be stored in the VPFB based on a current amount of data stored in the VPFB and/or based on a current amount of available memory space of the VPFB. The currently unavailable memory space (or the current available memory space) is used to select the size of a next data block to be stored in the VPFB. Other embodiments are disclosed and/or claimed.

Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described.

Abstract: A method for identifying and clustering worker agents for processing requests includes receiving, by a core node, from a user agent, a user request. The core node updates, for each of the plurality of worker agents, an availability status, thereby producing a plurality of availability statuses. The core node computes, for each of the plurality of worker agents, a value of a drift metric. The core node clusters the plurality of worker agents to produce a plurality of clusters of worker agents, wherein each of the plurality of clusters contains worker agents that have similar semantic capabilities. Based at least on the user request, the plurality of availability statuses, and the plurality of clusters, the core node identifies a subset of the plurality of worker agents that are both available to process the user request and that are suitable for processing the user request.

Abstract: A new approach of systems and methods to support automatic generation of multiple platform-dependent instruction sets from a single specification of an integrated circuit (IC). First, a specification compiler accepts as input a first instruction set of a plurality of first instructions in a specification format, wherein the first instruction set defines a design pattern of one or more specifications and/or requirements of the IC and is independent of any implementation or platform of the IC. The design tool then converts the first instruction set into a second instruction set of a plurality of second instructions in an intermediate format. A language compiler then accepts and compiles the second instruction set into a plurality of third instruction sets, wherein each of the plurality of third instruction sets comprises a plurality of third instructions in a specific language for a specific platform targeting a specific implementation or application of the IC.

Abstract: A systolic neural CPU (SNCPU) including a two-dimensional systolic array of reconfigurable processing elements (PE's) fuses a conventional CPU with a convolutional neural network (CNN) accelerator in four phases of operation: row-CPU, column-accelerator, column-CPU, and row-accelerator. The SNCPU cycles through the four phases to avoid costly data movement across cores, reduce overhead, and reduce latency. The PE's communicate bidirectionally with neighboring PE's and memory units at an outer edge of the array. A row of PE's is configurable into a first deep neural network (DNN) accumulator at a first time and configurable into a first CPU pipeline at a second time. A column of PE's is configurable into a second DNN accumulator at a third time and configurable into a second CPU pipeline at a fourth time.

Abstract: A process control system 100 includes a plurality of controller devices 10 each of which performs process control on a plant, and an input-output device 20 that is connected to a target device of the process control. The input-output device 20 is installed in a different on-premise environment from the plurality of controller devices 10. Each of the controller devices 10 is connected to the input-output device 20 by a different closed network 40, and transmits and receives information on the process control on the plant to and from the input-output device 20.

Abstract: A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a display system, and a controller. The controller is configured to receive and execute one or more commands from the host computer system to cause a data transfer between the host computer system and the storage medium of the data storage device. The controller generates performance data representing the performance of the data storage device, wherein the performance data includes an efficiency ratio value representing a relative utilization of an operational capability of the data storage device in conducting the data transfer. The controller generates one or more control signals to cause the display system to visually indicate at least the efficiency ratio value of the performance data.

Abstract: Systems and methods for managing peripheral device connectivity based on context are described. In an embodiment, an IHS may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: select a first radio to communicate with a peripheral device; determine that at least one of: a distance between the IHS and the peripheral device, a battery level of the IHS, or a battery level of the peripheral device is greater or smaller than a threshold value; and, in response to the determination, select a second radio to communicate with the peripheral device.

Abstract: A data processing apparatus and a method for processing data are disclosed. The data processing apparatus comprises: multithreaded processing circuitry to perform processing operations of a plurality of micro-threads, each micro-thread operating in a corresponding execution context defining an architectural state. Thread control circuitry collects runtime data indicative of a performance metric relating to the processing operations. Decoder circuitry is responsive to a detach instruction in a first micro-thread of instructions executed in a first execution context defining a first architectural state, the detach instruction specifying an address, to provide detach control signals to the thread control circuitry.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3PP instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and executing, by execution circuitry, the decoded XOR3PP instruction to determine a first rotational value and a second rotational value, perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value, perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate

Abstract: A storage system includes N horizontal backplanes and a first mirror backplane. Each horizontal backplane includes a first controller and a second controller on a same plane. The N first controllers and the N second controllers of the storage system form a first column and a second column in a vertical direction. The first mirror backplane is perpendicular to the horizontal backplanes, a first side of the first mirror backplane is connected to the horizontal backplanes, and a second side is connected to the controllers. A second side of the first controller has N second mirror ports and N second heartbeat ports, and a first side of the second controller has N first mirror ports and N first heartbeat ports. Wiring on the first mirror backplane includes wiring that interconnects the first mirror port of the second controller to the second mirror port of the first controller.

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

Abstract: A computer processor comprises: a fetch unit that reads and writes instructions and data, a register file including a plurality of registers, which includes a general-purpose register and a special register, an arithmetic logic unit that performs computational processing, a decoder/controller that interprets the instructions and generates a control signal, a symmetric network interface that includes a master interface and a slave interface and that is connected to an on-chip network; and a service controller that receives a service request from the external source through the on-chip network and the symmetric network interface, that communicates with the decoder/controller to send and receive a state of the service request and a state of the computer processor, and that copies an instruction address of a subroutine for executing the service request to a program counter to perform an operation of a designated code when the decoder/controller determines execution of the service request.

Abstract: There is provided an apparatus, method and medium. The apparatus comprises processing circuitry to process instructions and a reorder buffer identifying a plurality of entries having state information associated with execution of one or more of the instructions. The apparatus comprises allocation circuitry to allocate entries in the reorder buffer, and to allocate at least one compressed entry corresponding to a plurality of the instructions. The apparatus comprises memory access circuitry responsive to an address associated with a memory access instruction corresponding to access-sensitive memory and the memory access instruction corresponding to the compressed entry, to trigger a reallocation procedure comprising flushing the memory access instruction and triggering reallocation of the memory access instruction without the compression.

Abstract: Disclosed herein are an intelligent scheduling apparatus and method. The intelligent scheduling apparatus includes one or more processors, and an execution memory for storing at least program that is executed by the one or more processors, wherein the at least one program is configured to, in a hybrid cloud environment including a cloud, an edge system, and a near-edge system, configure schedulers for scheduling tasks of the cloud, the edge system, and the near-edge systems, store data, requested by a client, in a work queue by controlling the schedulers based on a scheduler policy and process the tasks based on data stored in the work queue, and collect history data resulting from processing of the tasks depending on the scheduler policy, and train the scheduler policy based on the history data.