Abstract: An EtherCAT bus system includes an EtherCAT master, EtherCAT nodes, and an EtherCAT star hub arranged and/or assembled on the same printed circuit board with the EtherCAT master.

Abstract: A (controller area network) CAN filter combining method and a CNA controller are provided. The CAN filter includes a special filter and one or more common filters. The method includes: initializing a mask code and at least two filter codes of the special filter, acquiring a first total number of the filter codes in the special filter and a second total number of the common filters, acquiring mask codes and filter codes of the common filters, and adjusting the mask code and the filter codes of the special filter on the basis of the first total number, the second total number, and the mask codes and the filtering codes of all of the common filters. The method reduces the load of a processor, and prevents the CAN controller from processing a large amount of irrelevant data, thereby accelerating communications.

Abstract: A discrete three-dimensional (3-D) processor a plurality of storage-processing units (SPU's), each of which comprises a non-memory circuit and more than one 3-D memory (3D-M) array. The preferred 3-D processor further comprises communicatively coupled first and second dice. The first die comprises the 3D-M arrays and the in-die peripheral-circuit components thereof; whereas, the second die comprises the non-memory circuits and off-die peripheral-circuit components of the 3D-M arrays.

Abstract: In one embodiment, a system includes a memory and a processor core. The processor core includes functional units and an instruction decode unit configured to determine whether an execute packet of instructions received by the processing core includes a first instruction that is designated for execution by a first functional unit of the functional units and a second instruction that is a condition code extension instruction that includes a plurality of sets of condition code bits, wherein each set of condition code bits corresponds to a different one of the functional units, and wherein the sets of condition code bits include a first set of condition code bits that corresponds to the first functional unit. When the execute packet includes the first and second instructions, the first functional unit is configured to execute the first instruction conditionally based upon the first set of condition code bits in the second instruction.

Abstract: The present disclosure provides a DIDT control method. The method includes, at each of a plurality of DIDT control modules: obtaining a local operation load of a local ALU in each clock cycle; obtaining a global operation load of a plurality of ALUs in each cycle period; determining an operation load index of the local ALU based on local historical load information and a local historical load weight set of the local ALU and global historical load information and a global historical load weight set of the multiple ALUs, the global historical load information includes a first number of the global operation loads, the local historical load information includes a second number of the local operation loads; and adjusting an operation load of the local ALU based on the operation load index of the local ALU and a predetermined load threshold to control a DIDT of the local ALU.

Abstract: Disclosed embodiments relate to a new instruction for performing data-ready memory access operations.

Abstract: This application discloses example synchronization instruction insertion methods and example apparatuses. One example method includes obtaining a first program block comprising one or more statements, where each of the one or more statements includes one or more function instructions. A first function instruction and a second function instruction between which data dependency exists in the first program block can then be determined. A synchronization instruction pair between a first statement including the first function instruction and a second statement including the second function instruction can then be inserted.

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory controller. The memory controller has a memory pipeline. The memory controller is coupled to control the cache memory and communicatively coupled to the processor core. The memory controller is configured to receive the memory write requests from the processor core; schedule the memory write requests on the memory pipeline; and contemporaneously with scheduling respective ones of the memory write requests on the memory pipeline, send to the processor core a write acknowledgment confirming that writing of a data payload of the respective memory write request to the cache memory has completed.

Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described.

Abstract: In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.

Abstract: A processor circuit includes an instruction decode unit, an instruction detector, an address generator and a data buffer. The instruction decode unit is configured to decode a first load instruction included in a plurality of load instructions to generate a first decoding result. The instruction detector, coupled to the instruction decode unit, is configured to detect if the load instructions use a same register. The address generator, coupled to the instruction decode unit, is configured to generate a first address requested by the first load instruction according to the first decoding result. The data buffer is coupled to the instruction detector and the address generator. When the instruction detector detects that the load instructions use the same register, the data buffer is configured to store the first address generated from the address generator, and store data requested by the first load instruction according to the first address.

Abstract: A method increases user interaction with deep learning agents. A generation request for a content slot is received. A subsequent tag vector, for the content slot, is generated from a previous tag, for a previous content slot, using a subsequent tag model. A context vector is generated from a set of subsequent tag vectors, which include the subsequent tag vector, using a context vector generator. A selection vector is generated from the context vector using a contextual bandit model. A content set is generated for a content slot using the selection vector. The content set for the content slot is presented.

Abstract: Disclosed are a processor, a processor operation method and an electronic device comprising same. The disclosed processor operation method comprises the steps of: identifying an instruction for instructing the execution of a first operation and address information of an operand corresponding to the instruction; and executing the instruction on the basis of whether or not the address information of the operand satisfies a predetermined condition. In the step of executing the instruction, a second operation configured to the instruction is executed for the operand if the address information of the operand satisfies the predetermined condition, and the first operation is executed for the operand if the address information of the operand does not satisfy the predetermined condition.

Abstract: There is provided a configuration that includes a substrate holder configured to hold substrates; a transfer mechanism configured to transfer the substrates to the substrate holder; and a controller configured to: acquire a number of substrates mountable on the substrate holder and a number of the product substrates to be mounted on the substrate holder; divide the product substrates into product substrate groups; divide the dummy substrates into dummy substrate groups based on the number of the product substrates, the number of the substrates mountable on the substrate holder, and a number of the product substrate groups; combine the product substrate groups and the dummy substrate groups; create substrate arrangement data for distributing and mounting the product substrates on the substrate holder; and cause the transfer mechanism to transfer the substrates according to the substrate arrangement data.

Abstract: A method of activating scheduling instructions within a parallel processing unit includes checking if an ALU targeted by a decoded instruction is full by checking a value of an ALU work fullness counter stored in the instruction controller and associated with the targeted ALU. If the targeted ALU is not full, the decoded instruction is sent to the targeted ALU for execution and the ALU work fullness counter associated with the targeted ALU is updated. If, however, the targeted ALU is full, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state. When an ALU changes from being full to not being full, the scheduler is triggered to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.

Abstract: Aspects of the embodiments are directed to systems and methods for performing link training using stored and retrieved equalization parameters obtained from a previous equalization procedure. As part of a link training sequence, links interconnecting an upstream port with a downstream port and with any intervening retimers, can undergo an equalization procedure. The equalization parameter values from each system component, including the upstream port, downstream port, and retimer(s) can be stored in a nonvolatile memory. During a subsequent link training process, the equalization parameter values stored in the nonvolatile memory can be written to registers associated with the upstream port, downstream port, and retimer(s) to be used to operate the interconnecting links. The equalization parameter values can be used instead of performing a new equalization procedure or can be used as a starting point to reduce latency associated with equalization procedures.

Abstract: Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.

Abstract: An orchestrator ensures the best available vehicle communication technology is selected. In the computer architecture, the orchestrator is injected on the data bus line is also coupled to a plurality of independent silos of vehicle communication technologies for autonomous driving vehicle technologies. Real-time accurate strength signals associated with the plurality of independent silos are received. One of the independent silos of communication is selected for rerouting the data transfer, based on a type of data involved in the data transfer, and based on a best available of the plurality of independent silos for the data transfer type. The data transfer is directed over the selected independent silo that is the best available.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Abstract: A model conversion method is disclosed. The model conversion method includes obtaining model attribute information of an initial offline model and hardware attribute information of a computer equipment, determining whether the model attribute information of the initial offline model matches the hardware attribute information of the computer equipment according to the initial offline model and the hardware attribute information of the computer equipment and in the case when the model attribute information of the initial offline model does not match the hardware attribute information of the computer equipment, converting the initial offline model to a target offline model that matches the hardware attribute information of the computer equipment according to the hardware attribute information of the computer equipment and a preset model conversion rule.