Abstract: Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.

Abstract: An orchestrator ensures the best available vehicle communication technology is selected. In the computer architecture, the orchestrator is injected on the data bus line is also coupled to a plurality of independent silos of vehicle communication technologies for autonomous driving vehicle technologies. Real-time accurate strength signals associated with the plurality of independent silos are received. One of the independent silos of communication is selected for rerouting the data transfer, based on a type of data involved in the data transfer, and based on a best available of the plurality of independent silos for the data transfer type. The data transfer is directed over the selected independent silo that is the best available.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Abstract: A model conversion method is disclosed. The model conversion method includes obtaining model attribute information of an initial offline model and hardware attribute information of a computer equipment, determining whether the model attribute information of the initial offline model matches the hardware attribute information of the computer equipment according to the initial offline model and the hardware attribute information of the computer equipment and in the case when the model attribute information of the initial offline model does not match the hardware attribute information of the computer equipment, converting the initial offline model to a target offline model that matches the hardware attribute information of the computer equipment according to the hardware attribute information of the computer equipment and a preset model conversion rule.

Abstract: A System-On-Chip (SoC) includes a set of registers, a processor, and Out-Of-Order Write (OOOW) circuitry. The processor is to execute instructions including write instructions. After issuing a first write instruction to any of the registers in the set, the processor is to await an acknowledgement for the first write instruction before issuing a second write instruction to any of the registers in the set. The OOOW circuitry is to identify the write instructions issued by the processor to the registers in the set, to perform the identified write instructions in the registers irrespective of acknowledgements from the registers, and to send to the processor imitated acknowledgements for the identified write instructions.

Abstract: A method for clearing a register, including: causing the PLD to set preset bits of a first register and a second register as an invalid state, detect whether a command is received from a MCU; when the command being received, parsing the command and determining whether a reading or writing event is triggered; when the reading event being triggered, setting the preset bit of the first register as a valid state, reading data of the preset bit of the first register, postponing clearing, by the PLD, the preset bit of the first register for a preset time; when the writing event being triggered, setting the preset bit of the second register as the valid state, writing, by the MCU, data into the preset bit of the second register, causing the PLD to acquire the data, postpone clearing the preset bit of the second register for a second preset time.

Abstract: In one example, a hardware accelerator comprises: a programmable hardware instruction decoder programmed to store a plurality of opcodes; a programmable instruction schema mapping table implemented as a content addressable memory (CAM) and programmed to map the plurality of opcodes to a plurality of definitions of operands in a plurality of instructions; a hardware execution engine; and a controller configured to: receive an instruction that includes a first opcode of the plurality of opcodes; control the hardware instruction decoder to extract the first opcode from the instruction; obtain, from the instruction schema mapping table and based on the first opcode, a first definition of a first operand; and forward the instruction and the first definition to the hardware execution engine to control the hardware execution engine to extract the first operand from the instruction based on the first definition, and execute the instruction based on the first operand.

Abstract: A power evaluation tool for a system on a chip is disclosed. The tool includes a power profiling plug-in module executed by a processor on the chip to collect a snapshot of register data of components on the chip associated with power consumption by the system during a certain time. The collected register data is streamed to an external computing device. A data parser module receives the streamed collected register data on the external computing device. A spreadsheet generator module creates a spreadsheet of the collected register data. An interface module displays a graphic representation of the collected register data on a display.

Abstract: The present disclosure provides a data processing method and an apparatus and a related product. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By adopting the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.

Abstract: Disclosed herein are an intelligent scheduling apparatus and method. The intelligent scheduling apparatus includes one or more processors, and an execution memory for storing at least program that is executed by the one or more processors, wherein the at least one program is configured to, in a hybrid cloud environment including a cloud, an edge system, and a near-edge system, configure schedulers for scheduling tasks of the cloud, the edge system, and the near-edge systems, store data, requested by a client, in a work queue by controlling the schedulers based on a scheduler policy and process the tasks based on data stored in the work queue, and collect history data resulting from processing of the tasks depending on the scheduler policy, and train the scheduler policy based on the history data.

Abstract: Interactions between a classical computing system and a quantum computing system can be structured to increase the effective memory available to hold instructions for a quantum processor. The system stores a schedule of compiled quantum processing instructions in a memory storage location on a classical computing system. A small program memory is included in close proximity to a control system for the quantum processor on the quantum computing system. The classical computing system sends a subset of instructions from the schedule of quantum instructions to the program memory. The control system manages execution of the instructions by accessing them at the program memory and configuring the quantum processor accordingly. While the quantum processor executes the instructions, additional instructions are transferred from the classical computing system to the program memory to await execution.

Abstract: A document to be stored on a network-based storage system is identified. The document includes one or more macros in a first programming language. An object referenced by a function defined by a macro of the one or more macros is identified. The function is converted into one or more sets of operations represented in a second programming language. Each set of operations corresponds to one of one or more candidate object types associated with the object. At least one of the one or more sets of operations is to be performed with respect to the object responsive to indication of a corresponding candidate object type for the object during execution of the macro. The document including the one or more sets of operations represented in the second programming language is stored on the network-based storage system.

Abstract: An adder and a method for calculating 2n+x are provided, where x is a variable input expressed in a floating point format and n is an integer. The adder comprises: a first path configured to calculate 2n+x for x<0 and 2n?1?|x|<2n+1; a second path configured to calculate 2n+x for |x|<2n; a third path configured to calculate 2n+x for |x|?2n; and selection logic configured to cause the adder to output a result from one of the first, second, and third paths in dependence on the values of x and n.

Abstract: A processor may initialize a fetch of a first instruction. The processor may determine whether there is an icache miss for the first instruction. The processor may fetch the next instruction from a cache.

Abstract: Embodiments of the disclosure discloses a method and system for a virtualization environment for a data processing (DP) accelerator. In one embodiment, a data processing (DP) accelerator includes one or more statically partitioned resources and one or more virtual functions (VFs) each associated with one of the one or more statically partitioned resources. A virtual machine (VM) of a host is assigned one of the one or more VFs to access the statically partitioned resources associated with the assigned VF. The VM has no access to the rest of the one or more statically partitioned resources of the DP accelerator.

Abstract: Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.

Abstract: A network hub device used for building a simple network configuration in an in-vehicle network system is provided. A network hub device (35) is coupled to a trunk network and performs input/output of a signal to/from an in-vehicle device via a plurality of device side communication ports. A signal conversion section (35a, 35b) configured to perform signal conversion between a digital control signal and an analog control signal is provided between a trunk side communication port and an analog port. A second signal conversion section (70) configured to perform signal conversion between a digital control signal and an analog control signal is provided between a digital port (49) and a predetermined in-vehicle device (353).

Abstract: The systems and methods described herein relate to a bi-directional data path (DQ) symbol map generated based on error correction operations. A device may include sub-wordline drivers and bi-directional data paths (DQs) that couple between the sub-wordline drivers and input/output (I/O) interface circuitry based on assignments indicated by the DQ symbol map. The assignments may be generated based on error correction operations performed on data of the memory bank. In particular, the DQ symbol map may be generated to avoid some conditions that, if occurring, may render one or more data errors uncorrectable. These systems and methods may reduce a likelihood of a data error associated with a DQ being uncorrectable.

Abstract: An electronic device includes a communication unit, a control unit, and a display unit. The communication unit communicates with an external device using one of communication methods. The control unit determines a communication method, from among the communication methods, unable to be used in communication with the external device. The display unit displays an user interface that is not capable of selecting the determined communication method.

Abstract: The technology disclosed herein pertains to a system and method for profiling performance of an embedded computation instruction set (CIS), the method including receiving a profiling component to a computational storage device (CSD), the profiling component being configured to measure one or more execution parameters of a computational instruction set (CIS), executing the CIS at a program slot in a computational storage processor of the CSD, monitoring the execution of the CIS to generate a log of the execution parameters of the CIS, and communicating the log to a host in response to receiving a get-log page command.